plic.hh

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#ifndef __DEV_RISCV_PLIC_HH__
#define __DEV_RISCV_PLIC_HH__
 
#include <bitset>
#include <map>
 
#include "arch/riscv/interrupts.hh"
#include "dev/io_device.hh"
#include "dev/reg_bank.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Plic.hh"
#include "params/PlicBase.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
using namespace RiscvISA;
struct PlicOutput
{
  std::vector<uint32_t> maxID;
  std::vector<uint32_t> maxPriority;
};
 
class PlicBase : public BasicPioDevice
{
  public:
    typedef PlicBaseParams Params;
    PlicBase(const Params &params) :
      BasicPioDevice(params, params.pio_size)
    {}
 
    // Interrupt interface to send signal to PLIC
    virtual void post(int src_id) = 0;
    // Interrupt interface to clear signal to PLIC
    virtual void clear(int src_id) = 0;
};
 
class Plic : public PlicBase
{
  // Params
  protected:
    System *system;
 
    // Number of interrupt sources
    int nSrc;
    int nSrc32;
    int nContext;
 
  public:
    typedef PlicParams Params;
    Plic(const Params &params);
 
  // External API
  public:
    void post(int src_id) override;
    void clear(int src_id) override;
 
    void init() override;
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
  protected:
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
 
  // Register bank
  private:
 
    class PlicRegisters: public RegisterBankLE
    {
      public:
        const Addr pendingStart = 0x1000;
        const Addr enableStart = 0x2000;
        const Addr thresholdStart = 0x0200000;
        const Addr enablePadding = 0x80;
        const Addr thresholdPadding = 0x1000;
        const Addr maxBankSize = 0x4000000;
 
 
        std::vector<Register32> priority;
        std::vector<Register32> pending;
        std::vector<std::vector<Register32>> enable;
        std::vector<Register32> threshold;
        std::vector<Register32> claim;
        std::vector<RegisterRaz> enable_holes;
        std::vector<RegisterRaz> claim_holes;
        std::vector<RegisterRaz> reserved;
 
        PlicRegisters(const std::string &name, Addr base, Plic* plic) :
          RegisterBankLE(name, base),
          plic(plic) {}
 
        Plic* plic;
 
        void init();
 
    } registers;
 
    using Register32 = PlicRegisters::Register32;
 
    void writePriority(Register32& reg, const uint32_t& data,
      const int src_id);
 
    void writeEnable(Register32& reg, const uint32_t& data,
      const int src32_id, const int context_id);
 
    void writeThreshold(Register32& reg, const uint32_t& data,
      const int context_id);
 
    uint32_t readClaim(Register32& reg, const int context_id);
 
    void writeClaim(Register32& reg, const uint32_t& data,
      const int context_id);
 
  // Latency Model
  private:
 
    // Internal states
    // per-source pending * priority
    std::vector<uint32_t> pendingPriority;
    // per-context, per-source pendingPriority * enable
    std::vector<std::vector<uint32_t>> effPriority;
    // per-context last-claimed id
    std::vector<uint32_t> lastID;
    PlicOutput output;
 
    void propagateOutput();
    std::map<Tick, PlicOutput> outputQueue;
    EventFunctionWrapper update;
 
    void updateOutput();
 
    void updateInt();
};
 
} // namespace gem5
 
#endif // __DEV_RISCV_PLIC_HH__