PerfectCacheMemory.hh

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#ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
#define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__
 
#include <type_traits>
#include <unordered_map>
 
#include "base/compiler.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/protocol/AccessPermission.hh"
#include "mem/ruby/system/RubySystem.hh"
 
namespace gem5
{
 
namespace ruby
{
 
template<class ENTRY>
struct PerfectCacheLineState
{
    PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
    AccessPermission m_permission;
    ENTRY m_entry;
};
struct PerfectCacheLineState {…};
 
template<class ENTRY>
inline std::ostream&
operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
{
    return out;
}
inline std::ostream& {…}
 
template<class ENTRY>
class PerfectCacheMemory
{
  public:
    PerfectCacheMemory();
 
    void setRubySystem(RubySystem *rs);
 
    // tests to see if an address is present in the cache
    bool isTagPresent(Addr address) const;
 
    // Returns true if there is:
    //   a) a tag match on this address or there is
    //   b) an Invalid line in the same cache "way"
    bool cacheAvail(Addr address) const;
 
    // find an Invalid entry and sets the tag appropriate for the address
    void allocate(Addr address);
 
    void deallocate(Addr address);
 
    // Returns with the physical address of the conflicting cache line
    Addr cacheProbe(Addr newAddress) const;
 
    // looks an address up in the cache
    ENTRY* lookup(Addr address);
    const ENTRY* lookup(Addr address) const;
 
    // Get/Set permission of cache block
    AccessPermission getPermission(Addr address) const;
    void changePermission(Addr address, AccessPermission new_perm);
 
    // Print cache contents
    void print(std::ostream& out) const;
 
  private:
    // Private copy constructor and assignment operator
    PerfectCacheMemory(const PerfectCacheMemory& obj);
    PerfectCacheMemory& operator=(const PerfectCacheMemory& obj);
 
    // Data Members (m_prefix)
    std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map;
 
    RubySystem *m_ruby_system = nullptr;
    int m_block_size = 0;
 
    static constexpr bool entryRequiresRubySystem =
        std::is_member_function_pointer_v<decltype(&ENTRY::setRubySystem)>;
};
class PerfectCacheMemory {…};
 
template<class ENTRY>
inline std::ostream&
operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
{
    obj.print(out);
    out << std::flush;
    return out;
}
inline std::ostream& {…}
 
template<class ENTRY>
inline
PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
{
}
PerfectCacheMemory<ENTRY>::PerfectCacheMemory() {…}
 
template<class ENTRY>
inline
void PerfectCacheMemory<ENTRY>::setRubySystem(RubySystem *rs)
{
    m_ruby_system = rs;
    m_block_size = rs->getBlockSizeBytes();
}
void PerfectCacheMemory<ENTRY>::setRubySystem(RubySystem *rs) {…}
 
// tests to see if an address is present in the cache
template<class ENTRY>
inline bool
PerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const
{
    return m_map.count(makeLineAddress(address, floorLog2(m_block_size))) > 0;
}
PerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const {…}
 
template<class ENTRY>
inline bool
PerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const
{
    return true;
}
PerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const {…}
 
// find an Invalid or already allocated entry and sets the tag
// appropriate for the address
template<class ENTRY>
inline void
PerfectCacheMemory<ENTRY>::allocate(Addr address)
{
    PerfectCacheLineState<ENTRY> line_state;
    line_state.m_permission = AccessPermission_Invalid;
    line_state.m_entry = ENTRY();
    if constexpr (entryRequiresRubySystem) {
        line_state.m_entry.setRubySystem(m_ruby_system);
    }
    Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
    m_map.emplace(line_addr, line_state);
}
PerfectCacheMemory<ENTRY>::allocate(Addr address) {…}
 
// deallocate entry
template<class ENTRY>
inline void
PerfectCacheMemory<ENTRY>::deallocate(Addr address)
{
    Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
    [[maybe_unused]] auto num_erased = m_map.erase(line_addr);
    assert(num_erased == 1);
}
PerfectCacheMemory<ENTRY>::deallocate(Addr address) {…}
 
// Returns with the physical address of the conflicting cache line
template<class ENTRY>
inline Addr
PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const
{
    panic("cacheProbe called in perfect cache");
    return newAddress;
}
PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const {…}
 
// looks an address up in the cache
template<class ENTRY>
inline ENTRY*
PerfectCacheMemory<ENTRY>::lookup(Addr address)
{
    Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
    return &m_map[line_addr].m_entry;
}
PerfectCacheMemory<ENTRY>::lookup(Addr address) {…}
 
// looks an address up in the cache
template<class ENTRY>
inline const ENTRY*
PerfectCacheMemory<ENTRY>::lookup(Addr address) const
{
    Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
    return &m_map[line_addr].m_entry;
}
PerfectCacheMemory<ENTRY>::lookup(Addr address) const {…}
 
template<class ENTRY>
inline AccessPermission
PerfectCacheMemory<ENTRY>::getPermission(Addr address) const
{
    Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
    return m_map[line_addr].m_permission;
}
PerfectCacheMemory<ENTRY>::getPermission(Addr address) const {…}
 
template<class ENTRY>
inline void
PerfectCacheMemory<ENTRY>::changePermission(Addr address,
                                            AccessPermission new_perm)
{
    Addr line_addr = makeLineAddress(address, floorLog2(m_block_size));
    PerfectCacheLineState<ENTRY>& line_state = m_map[line_addr];
    line_state.m_permission = new_perm;
}
PerfectCacheMemory<ENTRY>::changePermission(Addr address, {…}
 
template<class ENTRY>
inline void
PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
{
}
PerfectCacheMemory<ENTRY>::print(std::ostream& out) const {…}
 
} // namespace ruby
} // namespace gem5
 
#endif // __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__