| NDRAMSim | Forward declaration to avoid includes |
| Ndramsim3 | Forward declaration to avoid includes |
| ►Ngem5 | Copyright (c) 2024 Arm Limited All rights reserved |
| NAMBA | |
| ►NAMDGPU | |
| Cbinary32_u | |
| Cfp16_e5m10_info | |
| Cfp16_e8m7_info | |
| Cfp8_e4m3_info | |
| Cfp8_e5m2_info | |
| Cmxfp | |
| ►NArmISA | |
| Ncc_reg | |
| Nint_reg | |
| ►Nmisc_regs | |
| CFarAccessor | |
| CMpamAccessor | |
| ►Nmpam | |
| CPartitionFieldExtension | |
| ►Nvector_element_traits | |
| Cextend_element | |
| CAbortFault | |
| ►CArmFault | |
| CFaultVals | |
| CArmFaultVals | |
| CArmSev | |
| CArmStaticInst | |
| CBaseISADevice | Base class for devices that use the MiscReg interfaces |
| CBigFpMemImmOp | |
| CBigFpMemLitOp | |
| CBigFpMemPostOp | |
| CBigFpMemPreOp | |
| CBigFpMemRegOp | |
| CBranchEret64 | |
| CBranchEretA64 | |
| CBranchImm | |
| CBranchImm64 | |
| CBranchImmCond | |
| CBranchImmCond64 | |
| CBranchImmImmReg64 | |
| CBranchImmReg | |
| CBranchImmReg64 | |
| CBranchReg | |
| CBranchReg64 | |
| CBranchRegCond | |
| CBranchRegReg | |
| CBranchRegReg64 | |
| CBranchRet64 | |
| CBranchRetA64 | |
| CBrkPoint | |
| CCCRegClassOps | |
| CCrypto | |
| CDataAbort | |
| CDataImmOp | |
| CDataRegOp | |
| CDataRegRegOp | |
| CDataX1Reg2ImmOp | |
| CDataX1RegImmOp | |
| CDataX1RegOp | |
| CDataX2RegImmOp | |
| CDataX2RegOp | |
| CDataX3RegOp | |
| CDataXCondCompImmOp | |
| CDataXCondCompRegOp | |
| CDataXCondSelOp | |
| CDataXERegOp | |
| CDataXImmOnlyOp | |
| CDataXImmOp | |
| CDataXSRegOp | |
| CDecoder | |
| CDTLBIALL | Data TLB Invalidate All |
| CDTLBIASID | Data TLB Invalidate by ASID match |
| CDTLBIMVA | Data TLB Invalidate by VA |
| CDummyISADevice | Dummy device that prints a warning when it is accessed |
| CDumpStats | |
| CDumpStats64 | |
| ►CEmuFreebsd | |
| CBaseSyscallABI | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| ►CEmuLinux | |
| CBaseSyscallABI | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| CFastInterrupt | |
| CFpCondCompRegOp | |
| CFpCondSelOp | |
| CFpOp | |
| CFpRegImmOp | |
| CFpRegRegImmOp | |
| CFpRegRegOp | |
| CFpRegRegRegCondOp | |
| CFpRegRegRegImmOp | |
| CFpRegRegRegOp | |
| CFpRegRegRegRegOp | |
| CFsFreebsd | |
| CFsLinux | |
| CFsWorkload | |
| CHardwareBreakpoint | |
| CHTMCheckpoint | |
| CHypervisorCall | |
| CHypervisorTrap | |
| CIllegalInstSetStateFault | Illegal Instruction Set State fault (AArch64 only) |
| CInterrupt | |
| CInterrupts | |
| CIntRegClassOps | |
| CISA | |
| CITLBIALL | Instruction TLB Invalidate All |
| CITLBIASID | Instruction TLB Invalidate by ASID match |
| CITLBIMVA | Instruction TLB Invalidate by VA |
| CMacroMemOp | Base class for microcoded integer memory instructions |
| CMacroVFPMemOp | Base class for microcoded floating point memory instructions |
| CMemory | |
| CMemory64 | |
| CMemoryAtomicPair64 | |
| CMemoryDImm | |
| CMemoryDImm64 | |
| CMemoryDImmEx64 | |
| CMemoryDReg | |
| CMemoryEx64 | |
| CMemoryExDImm | |
| CMemoryExImm | |
| CMemoryImm | |
| CMemoryImm64 | |
| CMemoryLiteral64 | |
| CMemoryOffset | |
| CMemoryPostIndex | |
| CMemoryPostIndex64 | |
| CMemoryPreIndex | |
| CMemoryPreIndex64 | |
| CMemoryRaw64 | |
| CMemoryReg | |
| CMemoryReg64 | |
| CMicroIntImmOp | Microops of the form IntRegA = IntRegB op Imm |
| CMicroIntImmXOp | |
| CMicroIntMov | Microops of the form IntRegA = IntRegB |
| CMicroIntOp | Microops of the form IntRegA = IntRegB op IntRegC |
| CMicroIntRegOp | Microops of the form IntRegA = IntRegB op shifted IntRegC |
| CMicroIntRegXOp | |
| CMicroMemOp | Memory microops which use IntReg + Imm addressing |
| CMicroMemPairOp | |
| CMicroNeonMemOp | Microops for Neon loads/stores |
| CMicroNeonMixLaneOp | |
| CMicroNeonMixLaneOp64 | |
| CMicroNeonMixOp | Microops for Neon load/store (de)interleaving |
| CMicroNeonMixOp64 | Microops for AArch64 NEON load/store (de)interleaving |
| CMicroOp | Base class for Memory microops |
| CMicroOpX | |
| CMicroSetPCCPSR | Microops of the form PC = IntRegA CPSR = IntRegB |
| CMightBeMicro | |
| CMightBeMicro64 | |
| CMiscRegClassOps | |
| CMiscRegLUTEntry | MiscReg metadata |
| CMiscRegLUTEntryInitializer | Metadata table accessible via the value of the register |
| CMiscRegNum32 | |
| CMiscRegNum64 | |
| ►CMMU | |
| CCachedState | |
| CStats | |
| CMult3 | Base class for multipy instructions using three registers |
| CMult4 | Base class for multipy instructions using four registers |
| CPageTableOps | |
| CPairMemOp | Base class for pair load/store instructions |
| CPCAlignmentFault | PC alignment fault (AArch64 only) |
| ►CPMU | Model of an ARM PMU version 3 |
| CCounterState | State of a counter within the PMU |
| CPMUEvent | Event definition base class |
| ►CRegularEvent | |
| CRegularProbe | |
| CSWIncrementEvent | |
| CPredImmOp | Base class for predicated immediate operations |
| CPredIntOp | Base class for predicated integer operations |
| CPredMacroOp | Base class for predicated macro-operations |
| CPredMicroop | Base class for predicated micro-operations |
| CPredOp | Base class for predicated integer operations |
| CPrefetchAbort | |
| CPTE | |
| CRegABI32 | |
| CRegABI64 | |
| ►CRemoteGDB | |
| ►CAArch32GdbRegCache | |
| CGEM5_PACKED | |
| ►CAArch64GdbRegCache | |
| CGEM5_PACKED | |
| CReset | |
| CRfeOp | |
| CSecureMonitorCall | |
| CSecureMonitorTrap | |
| CSelfDebug | |
| CSEWorkload | |
| CSkipFunc | |
| CSkipFuncLinux32 | |
| CSkipFuncLinux64 | |
| CSmeAddOp | |
| CSmeAddVlOp | |
| CSmeLd1xSt1xOp | |
| CSmeLdrStrOp | |
| CSmeMovExtractOp | |
| CSmeMovInsertOp | |
| CSmeOPOp | |
| CSmeRdsvlOp | |
| CSmeZeroOp | |
| CSoftwareBreakpoint | Software Breakpoint (AArch64 only) |
| CSoftwareStep | |
| CSoftwareStepFault | |
| CSPAlignmentFault | Stack pointer alignment fault (AArch64 only) |
| CSrsOp | |
| CStackTrace | |
| CStage2LookUp | |
| CSupervisorCall | |
| CSupervisorTrap | |
| CSveAdrOp | ADR |
| CSveBinConstrPredOp | Binary, constructive, predicated SVE instruction |
| CSveBinDestrPredOp | Binary, destructive, predicated (merging) SVE instruction |
| CSveBinIdxUnpredOp | Binary, unpredicated SVE instruction |
| CSveBinImmIdxUnpredOp | Binary with immediate index, destructive, unpredicated SVE instruction |
| CSveBinImmPredOp | Binary with immediate, destructive, predicated (merging) SVE instruction |
| CSveBinImmUnpredConstrOp | Binary with immediate, destructive, unpredicated SVE instruction |
| CSveBinImmUnpredDestrOp | SVE vector - immediate binary operation |
| CSveBinUnpredOp | Binary, unpredicated SVE instruction with indexed operand |
| CSveBinWideImmUnpredOp | Binary with wide immediate, destructive, unpredicated SVE instruction |
| CSveClampOp | |
| CSveCmpImmOp | SVE compare-with-immediate instructions, predicated (zeroing) |
| CSveCmpOp | SVE compare instructions, predicated (zeroing) |
| CSveComplexIdxOp | SVE Complex Instructions (indexed) |
| CSveComplexOp | SVE Complex Instructions (vectors) |
| CSveCompTermOp | Compare and terminate loop SVE instruction |
| CSveContigMemSI | |
| CSveContigMemSS | |
| CSveDotProdIdxOp | SVE dot product instruction (indexed) |
| CSveDotProdOp | SVE dot product instruction (vectors) |
| CSveElemCountOp | Element count SVE instruction |
| CSveIndexedMemSV | |
| CSveIndexedMemVI | |
| CSveIndexIIOp | Index generation instruction, immediate operands |
| CSveIndexIROp | |
| CSveIndexRIOp | |
| CSveIndexRROp | |
| CSveIntCmpImmOp | Integer compare with immediate SVE instruction |
| CSveIntCmpOp | Integer compare SVE instruction |
| CSveLdStructSI | |
| CSveLdStructSS | |
| CSveMemPredFillSpill | |
| CSveMemVecFillSpill | |
| CSveOrdReducOp | SVE ordered reductions |
| CSvePartBrkOp | Partition break SVE instruction |
| CSvePartBrkPropOp | Partition break with propagation SVE instruction |
| CSvePredBinPermOp | Predicate binary permute instruction |
| CSvePredCountOp | |
| CSvePredCountPredOp | |
| CSvePredLogicalOp | Predicate logical instruction |
| CSvePredTestOp | SVE predicate test |
| CSvePredUnaryWImplicitDstOp | SVE unary predicate instructions with implicit destination operand |
| CSvePredUnaryWImplicitSrcOp | SVE unary predicate instructions with implicit source operand |
| CSvePredUnaryWImplicitSrcPredOp | SVE unary predicate instructions, predicated, with implicit source operand |
| CSvePselOp | Psel predicate selection SVE instruction |
| CSvePtrueOp | PTRUE, PTRUES |
| CSveReducOp | SVE reductions |
| CSveSelectOp | Scalar element select SVE instruction |
| CSveStStructSI | |
| CSveStStructSS | |
| CSveTblOp | SVE table lookup/permute using vector of element indices (TBL) |
| CSveTerImmUnpredOp | Ternary with immediate, destructive, unpredicated SVE instruction |
| CSveTerPredOp | Ternary, destructive, predicated (merging) SVE instruction |
| CSveTerUnpredOp | Ternary, destructive, unpredicated SVE instruction |
| CSveUnaryPredOp | Unary, constructive, predicated (merging) SVE instruction |
| CSveUnaryPredPredOp | SVE unary operation on predicate (predicated) |
| CSveUnarySca2VecUnpredOp | Unary unpredicated scalar to vector instruction |
| CSveUnaryUnpredOp | Unary, constructive, unpredicated SVE instruction |
| CSveUnaryWideImmPredOp | Unary with wide immediate, constructive, predicated SVE instruction |
| CSveUnaryWideImmUnpredOp | Unary with wide immediate, constructive, unpredicated SVE instruction |
| CSveUnpackOp | SVE unpack and widen predicate |
| CSveWhileOp | While predicate generation SVE instruction |
| CSveWImplicitSrcDstOp | SVE unary predicate instructions with implicit destination operand |
| CSyscallTable32 | |
| CSyscallTable64 | |
| CSysDC64 | |
| CSystemError | System error (AArch64 only) |
| ►CTableWalker | |
| CDescriptorBase | |
| CL1Descriptor | |
| CL2Descriptor | Level 2 page table descriptor |
| CLongDescriptor | Long-descriptor format (LPAE) |
| CPort | |
| CStage2Walk | This translation class is used to trigger the data fetch once a timing translation returns the translated physical address |
| CTableWalkerState | |
| CTableWalkerStats | Statistics |
| ►CWalkerState | |
| CLongDescData | Helper variables used to implement hierarchical access permissions when the long-desc |
| ►CTLB | |
| CTable | |
| CTlbStats | |
| CTlbEntry | |
| CTLBIALL | TLB Invalidate All |
| CTLBIALLEL | Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions |
| CTLBIALLN | TLB Invalidate All, Non-Secure |
| CTLBIASID | TLB Invalidate by ASID match |
| CTLBIIPA | TLB Invalidate by Intermediate Physical Address |
| CTLBIMVA | TLB Invalidate by VA |
| CTLBIMVAA | TLB Invalidate by VA, All ASID |
| CTLBIOp | |
| CTLBIRange | |
| CTLBIRIPA | TLB Range Invalidate by VA, All ASIDs |
| CTLBIRMVA | TLB Range Invalidate by VA |
| CTLBIRMVAA | TLB Range Invalidate by VA, All ASIDs |
| CTLBIVMALL | Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions |
| CTLBSetAssociative | |
| CTlbTestInterface | |
| ►CTLBTypes | |
| CKeyType | |
| CUndefinedInstruction | |
| CV7LPageTableOps | |
| CV8PageTableOps16k | |
| CV8PageTableOps4k | |
| CV8PageTableOps64k | |
| CVfpMacroOp | |
| CVirtualDataAbort | |
| CVirtualFastInterrupt | |
| CVirtualInterrupt | |
| CVldMultOp | Base classes for microcoded integer memory instructions |
| CVldMultOp64 | Base classes for microcoded AArch64 NEON memory instructions |
| CVldSingleOp | |
| CVldSingleOp64 | |
| CVReg | 128-bit NEON vector register |
| CVstMultOp | Base class for microcoded integer memory instructions |
| CVstMultOp64 | |
| CVstSingleOp | |
| CVstSingleOp64 | |
| CWatchPoint | |
| CWatchpoint | |
| ►NArmISAInst | |
| CMacroTmeOp | |
| CMicroTcommit64 | |
| CMicroTfence64 | |
| CMicroTmeBasic64 | |
| CMicroTmeOp | |
| CTcancel64 | |
| CTcommit64 | |
| CTmeImmOp64 | |
| CTmeRegNone64 | |
| CTstart64 | |
| CTtest64 | |
| ►Nauxv | |
| CAuxVector | |
| ►Nbackdoor_manager_test | |
| CBackdoorManagerTest | |
| ►Nbitfield_backend | |
| CBitfieldTypes | |
| CBitUnionBaseType | |
| CBitUnionBaseType< BitUnionType< T > > | |
| CBitUnionOperators | |
| CSigned | |
| CUnsigned | |
| ►Nbloom_filter | |
| CBase | |
| CBlock | Simple deletable (with false negatives) bloom filter that extracts bitfields of an address to use as indexes of the filter vector |
| CBulk | Implementation of the bloom filter, as described in "Bulk Disambiguation of
Speculative Threads in Multiprocessors", by Ceze, Luis, et al |
| CH3 | Implementation of the bloom filter as described in "Implementing Signatures
for Transactional Memory", by Sanchez, Daniel, et al |
| CMulti | This BloomFilter has multiple sub-filters, each with its own hashing functionality |
| CMultiBitSel | The MultiBitSel Bloom Filter associates an address to multiple entries through the use of multiple hash functions |
| CPerfect | A perfect bloom filter with no false positives nor false negatives |
| ►Nbranch_prediction | |
| ►CBiModeBP | Implements a bi-mode branch predictor |
| CBPHistory | |
| ►CBPredUnit | Basically a wrapper class to hold both the branch predictor and the BTB |
| CBPredUnitStats | Statistics |
| CPredictorHistory | |
| ►CBranchTargetBuffer | |
| CBranchTargetBufferStats | |
| CBTBEntry | |
| CIndirectPredictor | |
| CLocalBP | Implements a local predictor that uses the PC to index into a table of counters |
| ►CLoopPredictor | |
| CBranchInfo | |
| CLoopEntry | |
| CLoopPredictorStats | |
| ►CLTAGE | |
| CLTageBranchInfo | |
| CMPP_LoopPredictor | |
| CMPP_LoopPredictor_8KB | |
| ►CMPP_StatisticalCorrector | |
| CBranchInfo | |
| CMPP_SCThreadHistory | |
| CMPP_StatisticalCorrector_64KB | |
| CMPP_StatisticalCorrector_8KB | |
| ►CMPP_TAGE | |
| CBranchInfo | |
| CMPP_TAGE_8KB | |
| ►CMultiperspectivePerceptron | |
| CACYCLIC | |
| CBIAS | |
| CBLURRYPATH | |
| CFilterEntry | Entry of the branch filter |
| CGHIST | Available features |
| CGHISTMODPATH | |
| CGHISTPATH | |
| CHistorySpec | Base class to implement the predictor tables |
| CIMLI | |
| CLOCAL | |
| CLocalHistories | Local history entries, each enty contains the history of directions taken by a given branch |
| CMODHIST | |
| CMODPATH | |
| CMPPBranchInfo | Branch information data |
| CPATH | |
| CRECENCY | |
| CRECENCYPOS | |
| CSGHISTPATH | |
| CThreadData | History data is kept for each thread |
| CMultiperspectivePerceptron64KB | |
| CMultiperspectivePerceptron8KB | |
| ►CMultiperspectivePerceptronTAGE | |
| CMPPTAGEBranchInfo | Branch information data type |
| CMultiperspectivePerceptronTAGE64KB | |
| CMultiperspectivePerceptronTAGE8KB | |
| ►CReturnAddrStack | Return address stack class, implements a simple RAS |
| CAddrStack | Subclass that implements the actual address stack |
| CRASHistory | |
| CReturnAddrStackStats | |
| CSimpleBTB | |
| ►CSimpleIndirectPredictor | |
| CHistoryEntry | |
| CIndirectHistory | Indirect branch history information Used for prediction, update and recovery |
| CIndirectStats | |
| CIPredEntry | |
| CThreadInfo | Per thread path and global history registers |
| ►CStatisticalCorrector | |
| CBranchInfo | |
| CSCThreadHistory | |
| CStatisticalCorrectorStats | |
| ►CTAGE | |
| CTageBranchInfo | |
| ►CTAGE_SC_L | |
| CTageSCLBranchInfo | |
| CTAGE_SC_L_64KB | |
| ►CTAGE_SC_L_64KB_StatisticalCorrector | |
| CSC_64KB_ThreadHistory | |
| CTAGE_SC_L_8KB | |
| ►CTAGE_SC_L_8KB_StatisticalCorrector | |
| CSC_8KB_ThreadHistory | |
| CTAGE_SC_L_LoopPredictor | |
| ►CTAGE_SC_L_TAGE | |
| CBranchInfo | |
| CTAGE_SC_L_TAGE_64KB | |
| CTAGE_SC_L_TAGE_8KB | |
| ►CTAGEBase | |
| CBranchInfo | |
| CFoldedHistory | |
| CTAGEBaseStats | |
| CTageEntry | |
| CThreadHistory | |
| ►CTournamentBP | Implements a tournament branch predictor, hopefully identical to the one used in the 21264 |
| CBPHistory | The branch history information that is created upon predicting a branch |
| ►Ncompression | |
| ►Nencoder | |
| CBase | Base class for encoders |
| CCode | |
| ►CHuffman | This encoder builds a Huffman tree using the frequency of each value to be encoded |
| CNode | Node for the Huffman tree |
| CNodeComparator | Entries are not inserted directly into the tree |
| ►CBase | Base cache compressor interface |
| CBaseStats | |
| CCompressionData | |
| CBase16Delta8 | |
| CBase32Delta16 | |
| CBase32Delta8 | |
| CBase64Delta16 | |
| CBase64Delta32 | |
| CBase64Delta8 | |
| ►CBaseDelta | Base class for all base-delta-immediate compressors |
| CPatternM | |
| CPatternX | |
| ►CBaseDictionaryCompressor | |
| CDictionaryStats | |
| ►CCPack | |
| CPatternMMMM | |
| CPatternMMMX | |
| CPatternMMXX | |
| CPatternXXXX | |
| CPatternZZZX | |
| CPatternZZZZ | |
| ►CDictionaryCompressor | A template version of the dictionary compressor that allows to choose the dictionary size |
| CCompData | |
| CDeltaPattern | A pattern that checks whether the difference of the value and the dictionary entries' is below a certain threshold |
| CFactory | Create a factory to determine if input matches a pattern |
| CFactory< Head > | Specialization to end the recursion |
| CLocatedMaskedPattern | A pattern that narrows the MaskedPattern by allowing a only single possible dictionary entry to be matched against |
| CMaskedPattern | A pattern that compares masked values against dictionary entries |
| CMaskedValuePattern | A pattern that compares masked values to a masked portion of a fixed value |
| CPattern | The compressed data is composed of multiple pattern entries |
| CRepeatedValuePattern | A pattern that checks if dictionary entry sized values are solely composed of multiple copies of a single value |
| CSignExtendedPattern | A pattern that checks whether the value is an N bits sign-extended value, that is, all the MSB starting from the Nth are equal to the (N-1)th bit |
| CUncompressedPattern | A pattern containing the original uncompressed data |
| ►CFPC | |
| CFPCCompData | |
| CRepBytes | |
| CSignExtended1Byte | |
| CSignExtended4Bits | |
| CSignExtendedHalfword | |
| CSignExtendedTwoHalfwords | |
| CUncompressed | |
| CZeroPaddedHalfword | |
| CZeroRun | |
| ►CFPCD | |
| CPatternFFFF | |
| CPatternFFXX | |
| CPatternMMMMPenultimate | |
| CPatternMMMMPrevious | |
| CPatternMMMXPenultimate | |
| CPatternMMMXPrevious | |
| CPatternMMXXPenultimate | |
| CPatternMMXXPrevious | |
| CPatternRRRR | |
| CPatternXXXX | |
| CPatternXXZZ | |
| CPatternXZZZ | |
| CPatternZXZX | |
| CPatternZZXX | |
| CPatternZZZX | |
| CPatternZZZZ | |
| ►CFrequentValues | This compressor samples the cache for a while, trying to define the most frequently used values |
| ►CCompData | |
| CCompressedValue | A compressed value contains its encoding, and the compressed data itself |
| CFrequentValuesListener | |
| CVFTEntry | |
| ►CMulti | |
| CMultiCompData | |
| CMultiStats | |
| ►CPerfect | |
| CCompData | |
| ►CRepeatedQwords | |
| CPatternM | |
| CPatternX | |
| ►CZero | |
| CPatternX | |
| CPatternZ | |
| Ncontext_switch_task_id | Special TaskIds that are used for per-context-switch stats dumps and Cache Occupancy |
| ►Ncopy_engine_reg | |
| ►CChanRegs | |
| CCHANCMD | |
| CCHANCTRL | |
| CCHANERR | |
| CCHANSTS | |
| CDmaDesc | |
| CReg | |
| ►CRegs | |
| CINTRCTRL | |
| ►Ncp | |
| CFormat | |
| CPrint | |
| ►Ndebug | |
| CAllFlagsFlag | |
| CCompoundFlag | |
| CFlag | |
| CSimpleFlag | |
| ►Ndecode_cache | |
| ►CAddrMap | A sparse map from an Addr to a Value, stored in page chunks |
| CCacheChunk | |
| ►Nfastmodel | |
| CAmbaFromTlmBridge64 | |
| CAmbaToTlmBridge64 | |
| CCortexA76 | |
| CCortexA76Cluster | |
| CCortexA76TC | |
| CCortexR52 | |
| CCortexR52Cluster | |
| CCortexR52TC | |
| ►CFastmodelRemoteGDB | |
| CAArch64GdbRegCache | |
| CGIC | |
| CPL330 | |
| ►CResetControllerExample | |
| CCorePins | |
| CRegisters | |
| ►CSCGIC | |
| CTerminator | |
| CScxEvsCortexA76 | |
| CScxEvsCortexA76x1Types | |
| CScxEvsCortexA76x2Types | |
| CScxEvsCortexA76x3Types | |
| CScxEvsCortexA76x4Types | |
| ►CScxEvsCortexR52 | |
| CCorePins | |
| CScxEvsCortexR52x1Types | |
| CScxEvsCortexR52x2Types | |
| CScxEvsCortexR52x3Types | |
| CScxEvsCortexR52x4Types | |
| CSignalReceiver | |
| CSignalReceiverInt | |
| CSignalSender | |
| ►Nfree_bsd | |
| CSkipUDelay | A class to skip udelay() and related calls in the kernel |
| CThreadInfo | |
| NGem5Internal | |
| ►NGenericISA | |
| ►CBasicDecodeCache | |
| CAddrMapEntry | |
| CDelaySlotPCState | |
| CDelaySlotUPCState | |
| CM5DebugFault | |
| CM5DebugOnceFault | |
| CM5FatalFault | |
| CM5HackFaultBase | |
| CM5InformFaultBase | |
| CM5PanicFault | |
| CM5WarnFaultBase | |
| CPCStateWithNext | |
| CSimplePCState | |
| CUPCState | |
| ►Nguest_abi | |
| CAapcs32ArgumentBase | |
| CAapcs32ArrayType | |
| CAapcs32ArrayType< E[N]> | |
| CAapcs64ArrayType | |
| CAapcs64ArrayType< E[N]> | |
| CArgument | |
| CArgument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > > | |
| CArgument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CArgument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > sizeof(uint32_t)) > > | |
| CArgument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=sizeof(uint32_t)) > > | |
| CArgument< Aapcs32Vfp, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > &&!IsAapcs32HomogeneousAggregateV< Composite > > > | |
| CArgument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CArgument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > > | |
| CArgument< Aapcs32Vfp, Integer, typename std::enable_if_t< std::is_integral_v< Integer > > > | |
| CArgument< Aapcs32Vfp, VarArgs< Types... > > | |
| CArgument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > > | |
| CArgument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > > | |
| CArgument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> > | |
| CArgument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< ArmISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< GenericSyscallABI64, ABI > &&(std::is_integral_v< Arg >||std::is_same< Arg, pseudo_inst::GuestAddr >::value)> > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< RiscvISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&!ABI::template IsWideV< Arg > > > | |
| CArgument< Abi, ArmSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of_v< ArmSemihosting::AbiBase, Abi > > > | |
| CArgument< ABI, ConstProxyPtr< T, Proxy > > | |
| CArgument< ABI, ProxyPtr< T, Proxy > > | |
| CArgument< Abi, RiscvSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of_v< RiscvSemihosting::AbiBase, Abi > > > | |
| CArgument< ABI, VarArgs< Types... > > | |
| CArgument< ArmISA::RegABI32, pseudo_inst::GuestAddr > | |
| CArgument< ArmSemihosting::Abi32, Arg, typename std::enable_if_t<(std::is_integral_v< Arg >||std::is_same< Arg, pseudo_inst::GuestAddr >::value)> > | |
| CArgument< ArmSemihosting::Abi64, Arg, typename std::enable_if_t<(std::is_integral_v< Arg >||std::is_same< Arg, pseudo_inst::GuestAddr >::value)> > | |
| CArgument< RiscvISA::RegABI32, pseudo_inst::GuestAddr > | |
| CArgument< RiscvSemihosting::Abi32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > > | |
| CArgument< RiscvSemihosting::Abi64, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > > | |
| CArgument< SemiPseudoAbi32, T > | |
| CArgument< SemiPseudoAbi64, T > | |
| CArgument< SparcISA::SEWorkload::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&SparcISA::SEWorkload::SyscallABI32::IsWideV< Arg > > > | |
| CArgument< SparcPseudoInstABI, pseudo_inst::GuestAddr > | |
| CArgument< SparcPseudoInstABI, uint64_t > | |
| CArgument< TestABI, Addr > | |
| CArgument< TestABI_1D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > > | |
| CArgument< TestABI_1D, int > | |
| CArgument< TestABI_2D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > > | |
| CArgument< TestABI_2D, int > | |
| CArgument< TestABI_Prepare, int > | |
| CArgument< TestABI_TcInit, int > | |
| CArgument< X86ISA::EmuLinux::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&X86ISA::EmuLinux::SyscallABI32::IsWideV< Arg > > > | |
| CArgument< X86PseudoInstABI, pseudo_inst::GuestAddr > | |
| CArgument< X86PseudoInstABI, uint64_t > | |
| CIsAapcs32Composite | |
| CIsAapcs32Composite< T, typename std::enable_if_t<(std::is_array_v< T >||std::is_class_v< T >||std::is_union_v< T >) &&!IsVarArgsV< T > > > | |
| CIsAapcs32HomogeneousAggregate | |
| CIsAapcs32HomogeneousAggregate< E[N]> | |
| CIsAapcs64Composite | |
| CIsAapcs64Composite< T, typename std::enable_if_t<(std::is_array_v< T >||std::is_class_v< T >||std::is_union_v< T >) &&!IsVarArgsV< T > &&!IsAapcs64ShortVectorV< T > > > | |
| CIsAapcs64Hfa | |
| CIsAapcs64ShortVector | |
| CIsAapcs64ShortVector< E[N], typename std::enable_if_t<(std::is_integral_v< E >||std::is_floating_point_v< E >) &&(sizeof(E) *N==8||sizeof(E) *N==16)> > | |
| CIsVarArgs | |
| CIsVarArgs< VarArgs< Types... > > | |
| CPreparer | |
| CPreparer< ABI, Role, Type, decltype((void)&Role< ABI, Type >::prepare)> | |
| CResult | |
| CResult< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > > | |
| CResult< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CResult< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> > | |
| CResult< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> > | |
| CResult< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> > | |
| CResult< Aapcs32Vfp, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > &&!IsAapcs32HomogeneousAggregateV< Composite > > > | |
| CResult< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CResult< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > > | |
| CResult< Aapcs32Vfp, Integer, typename std::enable_if_t< std::is_integral_v< Integer > > > | |
| CResult< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > > | |
| CResult< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > > | |
| CResult< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> > | |
| CResult< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> > | |
| CResult< Abi, RiscvSemihosting::RetErrno > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< X86Linux::SyscallABI, ABI > > > | |
| CResult< ABI, void > | |
| CResult< ArmSemihosting::Abi32, ArmSemihosting::RetErrno > | |
| CResult< ArmSemihosting::Abi64, ArmSemihosting::RetErrno > | |
| CResult< MipsISA::SEWorkload::SyscallABI, SyscallReturn > | |
| CResult< PowerISA::SEWorkload::SyscallABI, SyscallReturn > | |
| CResult< RiscvISA::SEWorkload::SyscallABI32, SyscallReturn > | |
| CResult< RiscvISA::SEWorkload::SyscallABI64, SyscallReturn > | |
| CResult< SparcPseudoInstABI, T > | |
| CResult< TestABI_1D, int > | |
| CResult< TestABI_1D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > > | |
| CResult< TestABI_2D, int > | |
| CResult< TestABI_2D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > > | |
| CResult< TestABI_Prepare, Ret > | |
| CResult< X86PseudoInstABI, T > | |
| CResultStorer | |
| CResultStorer< ABI, Ret, typename std::enable_if_t< std::is_same_v< void(*)(ThreadContext *, const Ret &, typename ABI::State &), decltype(&Result< ABI, Ret >::store)> > > | |
| CStateInitializer | |
| CStateInitializer< ABI, typename std::enable_if_t< std::is_constructible_v< typename ABI::State, const ThreadContext * > > > | |
| CVarArgs | |
| CVarArgsBase | |
| CVarArgsBase< First, Types... > | |
| CVarArgsBase<> | |
| CVarArgsImpl | |
| CVarArgsImpl< ABI, Base > | |
| CVarArgsImpl< ABI, Base, First, Types... > | |
| ►Nigbreg | |
| Ntxd_op | |
| ►CRegs | |
| CCTRL | |
| CCTRL_EXT | |
| CEECD | |
| CEERD | |
| CFCRTH | |
| CFCRTL | |
| CFCTTV | |
| CFWSM | |
| CICR | |
| CITR | |
| CMANC | |
| CMDIC | |
| CPBA | |
| CRADV | |
| CRCTL | |
| CRDBA | |
| CRDH | |
| CRDLEN | |
| CRDT | |
| CRDTR | |
| CReg | |
| CRFCTL | |
| CRSRPD | |
| CRXCSUM | |
| CRXDCTL | |
| CSRRCTL | |
| CSTATUS | |
| CSWSM | |
| CTADV | |
| CTCTL | |
| CTDBA | |
| CTDH | |
| CTDLEN | |
| CTDT | |
| CTIDV | |
| CTXDCA_CTL | |
| CTXDCTL | |
| CRxDesc | |
| CTxDesc | |
| ►NIris | |
| CBaseCPU | |
| CBaseCpuEvs | |
| CCPU | |
| CInterrupts | |
| CISA | |
| CMMU | |
| ►CThreadContext | |
| CBpInfo | |
| CTLB | |
| ►Nlinux | |
| Npost5_10 | |
| Npre5_10 | |
| CDebugPrintk | |
| CPanicOrOopsEvent | Specify what to do on a Linux Kernel Panic or Oops |
| Cpcb_struct | |
| CSkipUDelay | A class to skip udelay() and related calls in the kernel |
| Cthread_info | |
| CThreadInfo | |
| ►Nloader | |
| CDtbFile | |
| CElfObject | |
| CElfObjectFormat | |
| CImageFile | |
| CImageFileData | |
| ►CMemoryImage | |
| CSegment | |
| CObjectFile | |
| CObjectFileFormat | |
| CRawImage | |
| CSymbol | |
| CSymbolTable | |
| ►Nmemory | |
| ►Nqos | |
| CFifoQueuePolicy | First In First Out Queue Policy |
| CFixedPriorityPolicy | Fixed Priority QoS Policy |
| CLifoQueuePolicy | Last In First Out Queue Policy |
| CLrgQueuePolicy | Least Recently Granted Queue Policy It selects packets from the queue with a round robin-like policy: using the requestor id as a switching parameter rather than switching over a time quantum |
| ►CMemCtrl | The qos::MemCtrl is a base class for Memory objects which support QoS - it provides access to a set of QoS scheduling policies |
| CMemCtrlStats | |
| ►CMemSinkCtrl | QoS Memory Sink |
| CMemoryPort | |
| CMemSinkCtrlStats | |
| CMemSinkInterface | |
| CPolicy | QoS Policy base class |
| CPropFairPolicy | Proportional Fair QoS Policy Providing a configurable fair scheduling policy based on utilization; utilization is directly proportional to a score which is inversely proportional to the QoS priority Users can tune the policy by adjusting the weight parameter (weight of the formula) |
| CQueuePolicy | QoS Queue Policy |
| CTurnaroundPolicy | Base class for QoS Bus Turnaround policies |
| CTurnaroundPolicyIdeal | Ideal QoS Bus Turnaround policy |
| ►CAbstractMemory | An abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information |
| CMemStats | |
| CBackingStoreEntry | A single entry for the backing store |
| CBurstHelper | A burst helper helps organize and manage a packet that is larger than the memory burst size |
| ►CCfiMemory | CfiMemory: This is modelling a flash memory adhering to the Common Flash Interface (CFI): |
| CBlockData | Metadata about the erase blocks in flash |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CMemoryPort | |
| CProgramBuffer | Word Buffer used by the BUFFERED PROGRAM command to write (program) chunks of words to flash |
| ►CDRAMInterface | Interface to DRAM devices with media specific parameters, statistics, and functions |
| CCommand | Simple structure to hold the values needed to keep track of commands for DRAMPower |
| CDRAMStats | |
| CRank | Rank class includes a vector of banks |
| CRankStats | |
| ►CDRAMSim2 | |
| CMemoryPort | The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself |
| CDRAMSim2Wrapper | Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world |
| ►CDRAMsim3 | |
| CMemoryPort | The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself |
| CDRAMsim3Wrapper | Wrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world |
| CDRAMSys | |
| CDRAMSysWrapper | |
| CHBMCtrl | HBM2 is divided into two pseudo channels which have independent data buses but share a command bus (separate row and column command bus) |
| CHeteroMemCtrl | |
| CLockedAddr | Locked address class that represents a physical address and a context id |
| ►CMemCtrl | The memory controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary controller |
| CCtrlStats | |
| CMemoryPort | |
| ►CMemInterface | General interface to memory device Includes functions and parameters shared across media types |
| CBank | A basic class to track the bank state, i.e |
| CMemPacket | A memory packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address |
| ►CNVMInterface | Interface to NVM devices with media specific parameters, statistics, and functions |
| CNVMStats | |
| CRank | NVM rank class simply includes a vector of banks |
| CPhysicalMemory | The physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect |
| ►CSharedMemoryServer | |
| CBaseShmPollEvent | |
| CClientSocketEvent | |
| CListenSocketEvent | |
| ►CSimpleMemory | The simple memory is a basic single-ported memory controller with a configurable throughput and latency |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CMemoryPort | |
| ►Nminor | |
| CBranchData | Forward data betwen Execute and Fetch1 carrying change-of-address/stream information |
| CBubbleIF | Interface class for data with 'bubble' values |
| CBubbleTraitsAdaptor | Pass on call to the element |
| CBubbleTraitsPtrAdaptor | Pass on call to the element where the element is a pointer |
| ►CDecode | |
| CDecodeThreadInfo | Data members after this line are cycle-to-cycle state |
| CExecContext | ExecContext bears the exec_context interface for Minor |
| ►CExecute | Execute stage |
| CExecuteThreadInfo | |
| ►CFetch1 | A stage responsible for fetching "lines" from memory and passing them to Fetch2 |
| CFetch1ThreadInfo | Stage cycle-by-cycle state |
| CFetchRequest | Memory access queuing |
| CIcachePort | Exposable fetch port |
| ►CFetch2 | This stage receives lines of data from Fetch1, separates them into instructions and passes them to Decode |
| CFetch2Stats | |
| CFetch2ThreadInfo | Data members after this line are cycle-to-cycle state |
| CForwardInstData | Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appropriate to the configured stage widths |
| CForwardLineData | Line fetch data in the forward direction |
| CFUPipeline | A functional unit configured from a MinorFU object |
| CInputBuffer | Like a Queue but with a restricted interface and a setTail function which, when the queue is empty, just takes a reference to the pushed item as the single element |
| CInstId | Id for lines and instructions |
| ►CLatch | Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see the right end of buffers between them |
| CInput | Encapsulate wires on either input or output of the latch |
| COutput | |
| ►CLSQ | |
| CBarrierDataRequest | Request for doing barrier accounting in the store buffer |
| CDcachePort | Exposable data port |
| CFailedDataRequest | FailedDataRequest represents requests from instructions that failed their predicates but need to ride the requests/transfers queues to maintain trace ordering |
| CLSQRequest | Derived SenderState to carry data access info |
| CSingleDataRequest | SingleDataRequest is used for requests that don't fragment |
| CSpecialDataRequest | Special request types that don't actually issue memory requests |
| CSplitDataRequest | |
| CStoreBuffer | Store buffer |
| CMinorActivityRecorder | ActivityRecorder with a Ticked interface |
| CMinorBuffer | TimeBuffer with MinorTrace and Named interfaces |
| CMinorDynInst | Dynamic instruction for Minor |
| CMinorStats | Currently unused stats class |
| CNoBubbleTraits | ... BubbleTraits are trait classes to add BubbleIF interface functionality to templates which process elements which don't necessarily implement BubbleIF themselves |
| CPipeline | The constructed pipeline |
| CQueue | Wrapper for a queue type to act as a pipeline stage input queue |
| CQueuedInst | Container class to box instructions in the FUs to make those queues have correct bubble behaviour when stepped |
| CReportIF | Interface class for data with reporting/tracing facilities |
| CReportTraitsAdaptor | ...ReportTraits are trait classes with the same functionality as ReportIF, but with elements explicitly passed into the report... functions |
| CReportTraitsPtrAdaptor | A similar adaptor but for elements held by pointer ElemType should implement ReportIF |
| CReservable | Base class for space reservation requestable objects |
| CScoreboard | A scoreboard of register dependencies including, for each register: The number of in-flight instructions which will generate a result for this register |
| CSelfStallingPipeline | A pipeline simulating class that will stall (not advance when advance() is called) if a non-bubble value lies at the far end of the pipeline |
| ►NMipsISA | |
| Nfloat_reg | |
| Nint_reg | |
| Nmisc_reg | |
| CAddressErrorFault | |
| CAddressFault | |
| CBreakpointFault | |
| CCoprocessorUnusableFault | |
| CCoreSpecific | |
| CDecoder | |
| CDspStateDisabledFault | |
| CEmuLinux | |
| CIntegerOverflowFault | |
| CInterruptFault | |
| CInterrupts | |
| CISA | |
| CMachineCheckFault | |
| CMipsFault | |
| ►CMipsFaultBase | |
| CFaultVals | |
| CMMU | |
| CNonMaskableInterrupt | |
| CPTE | |
| ►CRemoteGDB | |
| CMipsGdbRegCache | |
| CReservedInstructionFault | |
| CResetFault | |
| ►CSEWorkload | |
| CSyscallABI | |
| CSoftResetFault | |
| CStackTrace | |
| CSystemCallFault | |
| CThreadFault | |
| CTLB | |
| CTlbEntry | |
| CTlbFault | |
| CTlbInvalidFault | |
| CTlbModifiedFault | |
| CTlbRefillFault | |
| CTrapFault | |
| ►Nmpam | |
| CMSC | This class implements a simple MPAM Memory System Component (MSC) partitioning controller |
| ►Nnetworking | |
| CEthAddr | |
| CEthHdr | |
| CEthPtr | |
| Cip6_opt_dstopts | |
| Cip6_opt_fragment | |
| Cip6_opt_hdr | |
| Cip6_opt_routing_type2 | |
| CIp6Hdr | |
| CIp6Opt | |
| CIp6Ptr | |
| CIpAddress | |
| CIpHdr | |
| CIpNetmask | |
| CIpOpt | |
| CIpPtr | |
| CIpWithPort | |
| CTcpHdr | |
| CTcpOpt | |
| CTcpPtr | |
| CUdpHdr | |
| CUdpPtr | |
| NNullISA | |
| ►No3 | |
| CChecker | Specific non-templated derived class used for SimObject configuration |
| ►CCommit | Commit handles single threaded and SMT commit |
| CCommitStats | |
| ►CCPU | O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages |
| CCPUStats | |
| ►CDecode | Decode class handles both single threaded and SMT decode |
| CDecodeStats | |
| CStalls | Source of possible stalls |
| CDecodeStruct | Struct that defines the information passed from decode to rename |
| CDependencyEntry | Node in a linked list |
| CDependencyGraph | Array of linked list that maintains the dependencies between producing instructions and consuming instructions |
| ►CDynInst | |
| CArrays | |
| ►CElasticTrace | The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU |
| CElasticTraceStats | |
| CInstExecInfo | |
| CTraceInfo | |
| ►CFetch | Fetch class handles both single threaded and SMT fetch |
| CFetchStatGroup | |
| CFetchTranslation | |
| CFinishTranslationEvent | |
| CIcachePort | IcachePort class for instruction fetch |
| CStalls | Source of possible stalls |
| CFetchStruct | Struct that defines the information passed from fetch to decode |
| ►CFUPool | Pool of FU's, specific to the new CPU model |
| CFUIdxQueue | Class that implements a circular queue to hold FU indices |
| ►CIEW | IEW handles both single threaded and SMT IEW (issue/execute/writeback) |
| ►CIEWStats | |
| CExecutedInstStats | |
| CIEWStruct | Struct that defines the information passed from IEW to commit |
| ►CInstructionQueue | A standard instruction queue class |
| CFUCompletion | FU completion event class |
| CIQIOStats | |
| CIQStats | |
| CListOrderEntry | Entry for the list age ordering by op class |
| CPqCompare | Struct for comparing entries to be added to the priority queue |
| CIssueStruct | |
| ►CLSQ | |
| CDcachePort | DcachePort class for the load/store queue |
| CLSQRequest | Memory operation metadata |
| CSingleDataRequest | |
| CSplitDataRequest | |
| CUnsquashableDirectRequest | |
| ►CLSQUnit | Class that implements the actual LQ and SQ for each specific thread |
| CLSQEntry | |
| CLSQUnitStats | |
| CSQEntry | |
| CWritebackEvent | Writeback event, specifically for when stores forward data to loads |
| Cltseqnum | |
| ►CMemDepUnit | Memory dependency unit class |
| CMemDepEntry | Memory dependence entries that track memory operations, marking when the instruction is ready to execute and what instructions depend upon it |
| CMemDepUnitStats | |
| CPhysRegFile | Simple physical register file class |
| ►CRename | Rename handles both single threaded and SMT rename |
| CFreeEntries | Structures whose free entries impact the amount of instructions that can be renamed |
| CRenameHistory | Holds the information for each destination register rename |
| CRenameStats | |
| CStalls | Source of possible stalls |
| CRenameStruct | Struct that defines the information passed from rename to IEW |
| ►CROB | ROB class |
| CROBStats | |
| CScoreboard | Implements a simple scoreboard to track which registers are ready |
| CSimpleFreeList | Free list for a single class of registers (e.g., integer or floating point) |
| CSimpleRenameMap | Register rename map for a single class of registers (e.g., integer or floating point) |
| CSimpleTrace | |
| CStoreSet | Implements a store set predictor for determining if memory instructions are dependent upon each other |
| CThreadContext | Derived ThreadContext class for use with the O3CPU |
| CThreadState | Class that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc |
| ►CTimeStruct | Struct that defines all backwards communication |
| CCommitComm | |
| CDecodeComm | |
| CIewComm | |
| CRenameComm | |
| CUnifiedFreeList | FreeList class that simply holds the list of free integer and floating point registers |
| CUnifiedRenameMap | Unified register rename map for all classes of registers |
| ►Npartitioning_policy | |
| CBasePartitioningPolicy | A Partitioning Policy is a cache partitioning mechanism that limits the cache block allocations in a cache based on a PartitionID identifier |
| CMaxCapacityPartitioningPolicy | A MaxCapacityPartitioningPolicy filters the cache blocks available to a memory requestor (identified via PartitionID) based on count of already allocated blocks |
| CPartitionManager | |
| CWayPartitioningPolicy | A WayPartitioningPolicy filters the cache blocks available to a memory requestor (identified via PartitionID) based on the cache ways allocated to that requestor |
| CWayPolicyAllocation | A WayPolicyAllocation holds a single PartitionID->Ways allocation for Way Partitioning Policies |
| ►NPowerISA | |
| Nfloat_reg | |
| Nint_reg | |
| CAlignmentFault | |
| CBranchCondOp | Base class for conditional branches |
| CBranchDispCondOp | Base class for conditional, PC-relative or absolute address branches |
| CBranchOp | Base class for unconditional, PC-relative or absolute address branches |
| CBranchRegCondOp | Base class for conditional, register-based branches |
| CCondLogicOp | Class for condition register logical operations |
| CCondMoveOp | Class for condition register move operations |
| CDecoder | |
| CEmuLinux | |
| CFloatOp | Base class for floating point operations |
| CIntArithOp | Class for integer arithmetic operations |
| CIntCompOp | Class for integer compare operations |
| CIntConcatRotateOp | Class for integer rotate operations with a shift amount obtained from a register or by concatenating immediate fields and the first and last bits of a mask obtained by concatenating immediate fields |
| CIntConcatShiftOp | Class for integer shift operations with a shift value obtained from a register or by concatenating immediates |
| CIntDispArithOp | Class for integer arithmetic operations with displacement |
| CInterrupts | |
| CIntImmArithOp | Class for integer immediate arithmetic operations |
| CIntImmCompLogicOp | Class for integer immediate compare logical operations |
| CIntImmCompOp | Class for integer immediate compare operations |
| CIntImmLogicOp | Class for integer immediate logical operations |
| CIntImmOp | Class for integer immediate (signed and unsigned) operations |
| CIntImmTrapOp | Class for integer immediate trap operations |
| CIntLogicOp | Class for integer logical operations |
| CIntOp | We provide a base class for integer operations and then inherit for several other classes |
| CIntRotateOp | Class for integer rotate operations with a shift amount obtained from a register or an immediate and the first and last bits of a mask obtained from immediates |
| CIntShiftOp | Class for integer operations with a shift value obtained from a register or an instruction field |
| CIntTrapOp | Class for integer trap operations |
| CISA | |
| CMachineCheckFault | |
| CMemDispOp | Class for memory operations with displacement |
| CMemDispShiftOp | Class for memory operations with shifted displacement |
| CMemIndexOp | Class for memory operations with register indexed addressing |
| CMemOp | Base class for memory operations |
| CMiscOp | Class for misc operations |
| CMMU | |
| CPCDependentDisassembly | Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC) |
| CPCState | |
| CPowerFault | |
| CPowerStaticInst | |
| CPTE | |
| ►CRemoteGDB | |
| ►CPower64GdbRegCache | |
| CGEM5_PACKED | |
| ►CPowerGdbRegCache | |
| CGEM5_PACKED | |
| ►CSEWorkload | |
| CSyscallABI | |
| CStackTrace | |
| CTLB | |
| CTlbEntry | |
| CTrapFault | |
| CUnimplementedOpcodeFault | |
| ►Nprefetch | |
| ►CAccessMapPatternMatching | |
| CAccessMapEntry | AccessMapEntry data type |
| CAMPM | |
| ►CBase | |
| CPrefetchEvictListener | |
| CPrefetchInfo | Class containing the information needed by the prefetch to train and generate new prefetch requests |
| CPrefetchListener | |
| CStatGroup | |
| ►CBOP | |
| CDelayQueueEntry | In a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache |
| CDCPT | The prefetcher object using the DCPT |
| ►CDeltaCorrelatingPredictionTables | Delta Correlating Prediction Tables Prefetcher References: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching |
| CDCPTEntry | DCPT Table entry datatype |
| ►CIndirectMemory | |
| CIndirectPatternDetectorEntry | Indirect Pattern Detector entrt |
| CPrefetchTableEntry | Prefetch Table Entry |
| ►CIrregularStreamBuffer | |
| CAddressMapping | Address Mapping entry, holds an address and a confidence counter |
| CAddressMappingEntry | Maps a set of contiguous addresses to another set of (not necessarily contiguos) addresses, with their corresponding confidence counters |
| CTrainingUnitEntry | Training Unit Entry datatype, it holds the last accessed address and its secure flag |
| CMulti | |
| ►CPIF | |
| CCompactorEntry | The compactor tracks retired instructions addresses, leveraging the spatial and temporal locality among instructions for compaction |
| CIndexEntry | |
| CPrefetchListenerPC | Probe Listener to handle probe events from the CPU |
| ►CQueued | |
| CDeferredPacket | |
| CQueuedStats | |
| ►CSBOOE | |
| CSandbox | |
| CSandboxEntry | |
| ►CSignaturePath | |
| CPatternEntry | Pattern entry data type, a set of stride and counter entries |
| CPatternStrideEntry | A stride entry with its counter |
| CSignatureEntry | Signature entry data type |
| ►CSignaturePathV2 | |
| CGlobalHistoryEntry | Global History Register entry datatype |
| CSlimAMPM | |
| CSms | |
| ►CSTeMS | |
| ►CActiveGenerationTableEntry | Entry data type for the Active Generation Table (AGT) and the Pattern Sequence Table (PST) |
| CSequenceEntry | Sequence entry data type |
| CRegionMissOrderBufferEntry | Data type of the Region Miss Order Buffer entry |
| ►CStride | |
| CPCTableInfo | Information used to create a new PC table |
| CStrideEntry | Tagged by hashed PCs |
| CStridePrefetcherHashedSetAssociative | Override the default set associative to apply a specific hash function when extracting a set |
| CTagged | |
| ►Nprobing | Name space containing shared probe point declarations |
| CPacketInfo | A struct to hold on to the essential fields from a packet, so that the packet and underlying request can be safely passed on, and consequently modified or even deleted |
| ►Nps2 | |
| Nkeyboard | |
| Nmouse | |
| CDevice | |
| CPS2Keyboard | |
| CPS2Mouse | |
| CTouchKit | |
| ►Npseudo_inst | |
| CGuestAddr | This struct wrapper for Addr enables m5ops for systems with 32 bit pointer, since it allows to distinguish between address arguments and native C++ types |
| NQARMA | |
| ►Nqemu | |
| ►CFwCfg | |
| CDirectory | |
| CFwCfgIo | |
| CFwCfgItem | |
| CFwCfgItemBytes | |
| CFwCfgItemE820 | |
| CFwCfgItemFactory | |
| CFwCfgItemFactoryBase | |
| CFwCfgItemFile | |
| CFwCfgItemFixed | |
| CFwCfgItemString | |
| CFwCfgMmio | |
| ►Nreplacement_policy | |
| CBase | A common base class of cache replacement policy objects |
| CBIP | |
| ►CBRRIP | |
| CBRRIPReplData | BRRIP-specific implementation of replacement data |
| ►CDueling | This replacement policy duels two replacement policies to find out which one provides the best results |
| CDuelerReplData | Dueler-specific implementation of replacement data |
| CDuelingStats | |
| ►CFIFO | |
| CFIFOReplData | FIFO-specific implementation of replacement data |
| ►CLFU | |
| CLFUReplData | LFU-specific implementation of replacement data |
| ►CLRU | |
| CLRUReplData | LRU-specific implementation of replacement data |
| ►CMRU | |
| CMRUReplData | MRU-specific implementation of replacement data |
| ►CRandom | |
| CRandomReplData | Random-specific implementation of replacement data |
| CReplacementData | The replacement data needed by replacement policies |
| ►CSecondChance | |
| CSecondChanceReplData | Second-Chance-specific implementation of replacement data |
| ►CSHiP | |
| CSHiPReplData | SHiP-specific implementation of replacement data |
| CSHiPMem | SHiP that Uses memory addresses as signatures |
| CSHiPPC | SHiP that Uses PCs as signatures |
| ►CTreePLRU | |
| CTreePLRUReplData | Tree-PLRU-specific implementation of replacement data |
| ►CWeightedLRU | |
| CWeightedLRUReplData | Weighted LRU implementation of replacement data |
| ►NRiscvISA | |
| Nfloat_reg | |
| Nint_reg | |
| CAddressFault | |
| CAtomicGenericOp | A generic atomic op class |
| CAtomicMemOp | |
| CAtomicMemOpMicro | |
| CBareMetal | |
| CBasePMAChecker | Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the Physical Memory Attributes |
| CBootloaderKernelWorkload | |
| CBreakpointFault | |
| CBSOp | |
| CCmMacroInst | |
| CCompRegOp | Base class for compressed operations that work only on registers |
| CCSRMetadata | |
| CCSROp | Base class for CSR operations |
| CDecoder | |
| Cdouble_width | |
| Cdouble_width< float16_t > | |
| Cdouble_width< float32_t > | |
| Cdouble_width< float8_t > | |
| Cdouble_width< int16_t > | |
| Cdouble_width< int32_t > | |
| Cdouble_width< int64_t > | |
| Cdouble_width< int8_t > | |
| Cdouble_width< uint16_t > | |
| Cdouble_width< uint32_t > | |
| Cdouble_width< uint64_t > | |
| Cdouble_width< uint8_t > | |
| Cdouble_widthf | |
| Cdouble_widthf< int16_t > | |
| Cdouble_widthf< int32_t > | |
| Cdouble_widthf< int8_t > | |
| Cdouble_widthf< uint16_t > | |
| Cdouble_widthf< uint32_t > | |
| Cdouble_widthf< uint8_t > | |
| CEmuLinux | |
| CFsLinux | |
| CIllegalFrmFault | |
| CIllegalInstFault | |
| CImmOp | Base class for operations with immediates (I is the type of immediate) |
| CInstFault | |
| CInterruptFault | |
| CInterrupts | |
| CISA | |
| CLoad | |
| CLoadReserved | |
| CLoadReservedMicro | |
| CMemFenceMicro | |
| CMemInst | |
| CMmioVirtIO | |
| CMMU | |
| CNonMaskableInterruptFault | |
| CPCState | |
| CPMAChecker | This class provides an abstract PMAChecker for RISC-V to provide PMA checking functionality |
| ►CPMP | This class helps to implement RISCV's physical memory protection (pmp) primitive |
| CPmpEntry | Single pmp entry struct |
| CPseudoOp | |
| CRegABI32 | |
| CRegABI64 | |
| CRegOp | Base class for operations that work only on registers |
| ►CRemoteGDB | |
| ►CRiscv32GdbRegCache | |
| CGEM5_PACKED | RISC-V Register Cache Order and sizes of registers found in ext/gdb-xml/riscv.xml To add support for more CSRs: |
| ►CRiscv64GdbRegCache | |
| CGEM5_PACKED | RISC-V Register Cache Order and sizes of registers found in ext/gdb-xml/riscv.xml To add support for more CSRs: |
| CReset | |
| CRiscvFault | |
| CRiscvMacroInst | Base class for all RISC-V Macroops |
| CRiscvMicroInst | Base class for all RISC-V Microops |
| CRiscvStaticInst | Base class for all RISC-V static instructions |
| CSEWorkload | |
| CStackTrace | |
| CStore | |
| CStoreCond | |
| CStoreCondMicro | |
| CSyscallFault | |
| CSystemOp | Base class for system operations |
| ►CTLB | |
| CTlbStats | |
| CTlbEntry | |
| CUnimplementedFault | |
| CUnknown | Static instruction class for unknown (illegal) instructions |
| CUnknownInstFault | |
| CVConfOp | Base class for Vector Config operations |
| CVCpyVsMicroInst | |
| CVectorArithMacroInst | |
| CVectorArithMicroInst | |
| CVectorMacroInst | |
| CVectorMemMacroInst | |
| CVectorMemMicroInst | |
| CVectorMicroInst | |
| CVectorNonSplitInst | |
| CVectorNopMicroInst | |
| CVectorSlideMacroInst | |
| CVectorSlideMicroInst | |
| CVectorVMUNARY0MacroInst | |
| CVectorVMUNARY0MicroInst | |
| CVleMacroInst | |
| CVleMicroInst | |
| CVlFFTrimVlMicroOp | |
| CVlIndexMacroInst | |
| CVlIndexMicroInst | |
| CVlSegDeIntrlvMicroInst | |
| CVlSegMacroInst | |
| CVlSegMicroInst | |
| CVlStrideMacroInst | |
| CVlStrideMicroInst | |
| CVlWholeMacroInst | |
| CVlWholeMicroInst | |
| CVMaskMergeMicroInst | |
| CVMvWholeMacroInst | |
| CVMvWholeMicroInst | |
| CVPinVdMicroInst | |
| CVseMacroInst | |
| CVseMicroInst | |
| CVsIndexMacroInst | |
| CVsIndexMicroInst | |
| CVsSegIntrlvMicroInst | |
| CVsSegMacroInst | |
| CVsSegMicroInst | |
| CVsStrideMacroInst | |
| CVsStrideMicroInst | |
| CVsWholeMacroInst | |
| CVsWholeMicroInst | |
| CVxsatMicroInst | |
| ►CWalker | |
| CPagewalkerStats | |
| CWalkerPort | |
| CWalkerSenderState | |
| CWalkerState | |
| ►Nruby | |
| ►NCHI | |
| ►CMN_TBEStorage | |
| CMN_TBEStorageStats | |
| CMN_TBETable | |
| ►Ngarnet | |
| CCredit | |
| CCreditLink | |
| CCrossbarSwitch | |
| Cflit | |
| CflitBuffer | |
| CGarnetExtLink | |
| CGarnetIntLink | |
| CGarnetNetwork | |
| CInputUnit | |
| CNetworkBridge | |
| ►CNetworkInterface | |
| CInputPort | |
| COutputPort | |
| CNetworkLink | |
| COutputUnit | |
| COutVcState | |
| CRouteInfo | |
| CRouter | |
| CRoutingUnit | |
| CSwitchAllocator | |
| CVirtualChannel | |
| CAbstractCacheEntry | |
| ►CAbstractController | |
| CControllerStats | |
| CMemoryPort | Port that forwards requests and receives responses from the memory controller |
| CSenderState | |
| CTransMapPair | |
| CAccessTraceForAddress | |
| CAddressProfiler | |
| ►CALUFreeListArray | |
| CAccessRecord | |
| ►CBankedArray | |
| CAccessRecord | |
| ►CBaseRoutingUnit | |
| CRouteInfo | |
| CBasicExtLink | |
| CBasicIntLink | |
| CBasicLink | |
| CBasicRouter | |
| ►CCacheMemory | |
| CCacheMemoryStats | |
| CCacheRecorder | |
| CCHIGenericController | |
| CCoalescedRequest | |
| CConsumer | |
| CDataBlock | |
| CDirectoryMemory | |
| CDMARequest | |
| CDMASequencer | |
| ►CExpectedMap | |
| ►CExpectedState | |
| CEnumClassHash | |
| ►CFaultModel | |
| Csystem_conf | |
| ►CGPUCoalescer | |
| CGMTokenPort | |
| CHistogram | |
| CHTMSequencer | |
| CLinkEntry | |
| CMachineID | |
| CMessage | |
| CMessageBuffer | |
| CNetDest | |
| ►CNetwork | |
| CAddrMapNode | |
| CPendingWriteInst | |
| CPerfectCacheLineState | |
| CPerfectCacheMemory | |
| ►CPerfectSwitch | |
| COutputPort | |
| CPersistentTable | |
| CPersistentTableEntry | |
| CPrefetchEntry | |
| ►CProfiler | |
| ►CProfilerStats | |
| CPerMachineTypeStats | |
| CPerRequestTypeMachineTypeStats | |
| CPerRequestTypeStats | |
| CProtocolInfo | |
| CRejectException | |
| CRubyDummyPort | |
| ►CRubyPort | |
| CMemRequestPort | |
| CMemResponsePort | |
| CPioRequestPort | |
| CPioResponsePort | |
| CSenderState | |
| CRubyPortProxy | |
| ►CRubyPrefetcher | |
| CNonUnitFilterEntry | |
| CRubyPrefetcherStats | |
| CUnitFilterEntry | |
| CRubyPrefetcherProxy | This is a proxy for prefetcher class in classic memory |
| CRubyRequest | |
| CRubySystem | |
| CSequencer | |
| CSequencerRequest | |
| CSet | |
| CSimpleExtLink | |
| CSimpleIntLink | |
| ►CSimpleNetwork | |
| CNetworkStats | |
| CStoreTrace | |
| CSubBlock | |
| ►CSwitch | |
| CSwitchStats | |
| ►CTBEStorage | |
| CTBEStorageStats | |
| CTBETable | |
| ►CThrottle | |
| CThrottleStats | |
| CTimerTable | |
| CTopology | |
| CTraceRecord | Class for recording cache contents |
| ►CTriggerQueue | |
| CValType | |
| CUncoalescedTable | |
| CVIPERCoalescer | |
| CVIPERSequencer | |
| ►CWeightBased | |
| CLinkInfo | |
| CWireBuffer | |
| CWriteMask | |
| ►Nscmi | |
| CAgentChannel | This is a Agent to Platform channel (The agent is the initiator) |
| CBaseProtocol | This protocol describes the properties of the implementation and provides generic error management |
| CCommunication | The SCMI Communication class models a bidirectional communication between the SCMI platform and the agent |
| CMessage | |
| CPlatform | |
| CPlatformChannel | This is a Platform to Agent channel (The platform is the initiator) |
| CProtocol | |
| CVirtualChannel | Generic communication channel between the Agent and the Platform |
| ►Nsim_clock | These are variables that are set based on the simulator frequency |
| Nas_float | |
| Nas_int | These variables equal the number of ticks in the unit of time they're named after in a 64 bit integer |
| ►Nsinic | |
| ►Nregisters | |
| CInfo | |
| CBase | |
| ►CDevice | |
| CDeviceStats | Statistics |
| CVirtualReg | |
| CInterface | |
| ►NSparcISA | |
| Nfloat_reg | |
| Nint_reg | |
| CBlockMem | |
| CBlockMemImm | |
| CBlockMemImmMicro | |
| CBlockMemMicro | |
| CBranch | Base class for branch operations |
| CBranchDisp | Base class for branch operations with an immediate displacement |
| CBranchImm13 | Base class for branches that use an immediate and a register to compute their displacements |
| CBranchNBits | Base class for branches with n bit displacements |
| CBranchSplit | Base class for 16bit split displacements |
| CCleanWindow | |
| CCpuMondo | |
| CDataAccessError | |
| CDataAccessException | |
| CDataAccessProtection | |
| CDataInvalidTSBEntry | |
| CDataRealTranslationMiss | |
| CDecoder | |
| CDevMondo | |
| CDivisionByZero | |
| CEmuLinux | |
| CEnumeratedFault | |
| CExternallyInitiatedReset | |
| CFailUnimplemented | Static instruction class for unimplemented instructions that cause simulator termination |
| CFastDataAccessMMUMiss | |
| CFastDataAccessProtection | |
| CFastInstructionAccessMMUMiss | |
| CFillNNormal | |
| CFillNOther | |
| CFpDisabled | |
| CFpExceptionIEEE754 | |
| CFpExceptionOther | |
| CFpUnimpl | |
| CFsWorkload | |
| CHstickMatch | |
| CIllegalInstruction | |
| CInstructionAccessError | |
| CInstructionAccessException | |
| CInstructionBreakpoint | |
| CInstructionInvalidTSBEntry | |
| CInstructionRealTranslationMiss | |
| CInternalProcessorError | |
| CInterruptLevelN | |
| CInterrupts | |
| CInterruptVector | |
| CIntOp | Base class for integer operations |
| CIntOpImm | Base class for immediate integer operations |
| CIntOpImm10 | Base class for 10 bit immediate integer operations |
| CIntOpImm11 | Base class for 11 bit immediate integer operations |
| CIntOpImm13 | Base class for 13 bit immediate integer operations |
| CIntRegClassOps | |
| CISA | |
| CLDDFMemAddressNotAligned | |
| CLDQFMemAddressNotAligned | |
| CMem | Base class for memory operations |
| CMemAddressNotAligned | |
| CMemImm | Class for memory operations which use an immediate offset |
| CMMU | |
| CNop | Nop class |
| CPageTableEntry | |
| CPAWatchpoint | |
| CPowerOnReset | |
| CPriv | Base class for privelege mode operations |
| CPrivilegedAction | |
| CPrivilegedOpcode | |
| CPrivImm | Base class for privelege mode operations with immediates |
| CPrivReg | |
| CRdPriv | |
| CREDStateException | |
| ►CRemoteGDB | |
| CSPARC64GdbRegCache | |
| CSPARCGdbRegCache | |
| CResumableError | |
| CSetHi | Base class for sethi |
| ►CSEWorkload | |
| CBaseSyscallABI | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| CSoftwareInitiatedReset | |
| CSparcDelayedMicroInst | |
| CSparcFault | |
| ►CSparcFaultBase | |
| CFaultVals | |
| CSparcMacroInst | |
| CSparcMicroInst | |
| CSparcStaticInst | Base class for all SPARC static instructions |
| CSpillNNormal | |
| CSpillNOther | |
| CStackTrace | |
| CSTDFMemAddressNotAligned | |
| CStoreError | |
| CSTQFMemAddressNotAligned | |
| CTagOverflow | |
| CTLB | |
| CTlbEntry | |
| CTlbMap | |
| CTlbRange | |
| CTrap | Base class for trap instructions, or instructions that always fault |
| CTrapInstruction | |
| CTrapLevelZero | |
| CTteTag | |
| CUnknown | Class for Unknown/Illegal instructions |
| CVAWatchpoint | |
| CVecDisabled | |
| CWarnUnimplemented | Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation) |
| CWatchDogReset | |
| CWrPriv | |
| CWrPrivImm | |
| ►Nstatistics | |
| ►Nunits | Units for Stats |
| CBase | Parent class of all unit classes |
| CBit | |
| CByte | |
| CCount | |
| CCycle | |
| CDegreeCelsius | |
| CJoule | |
| CRate | |
| CRatio | |
| CSecond | |
| CTick | |
| CUnspecified | |
| CVolt | |
| CWatt | |
| CAverage | A stat that calculates the per tick average of a value |
| CAverageDeviation | Calculates the per tick mean and variance of the samples |
| CAverageVector | A vector of Average stats |
| ►CAvgSampleStor | Templatized storage for distribution that calculates per tick mean and variance |
| CParams | |
| ►CAvgStor | Templatized storage and interface to a per-tick average stat |
| CParams | |
| CBasePrint | |
| CBinaryNode | |
| CConstNode | |
| CConstVectorNode | |
| CDataWrap | |
| CDataWrapVec | |
| CDataWrapVec2d | |
| CDistBase | Implementation of a distribution stat |
| CDistData | General container for distribution data |
| CDistInfo | |
| CDistInfoProxy | |
| CDistParams | The parameters for a distribution stat |
| CDistPrint | |
| CDistProxy | |
| CDistribution | A simple distribution stat |
| ►CDistStor | Templatized storage and interface for a distribution stat |
| CParams | The parameters for a distribution stat |
| CFormula | A formula for statistics that is calculated when printed |
| CFormulaInfo | |
| CFormulaInfoProxy | |
| CFormulaNode | |
| CFunctorProxy | |
| CFunctorProxy< T, typename std::enable_if_t< std::is_constructible_v< std::function< Result()>, const T & > > > | Template specialization for type std::function<Result()> which holds a copy of its target instead of a pointer to it |
| CGroup | Statistics container |
| CHdf5 | |
| CHistogram | A simple histogram stat |
| ►CHistStor | Templatized storage and interface for a histogram stat |
| CParams | The parameters for a distribution stat |
| CInfo | |
| CInfoAccess | |
| CInfoProxy | |
| CMethodProxy | A proxy similar to the FunctorProxy, but allows calling a method of a bound object, instead of a global free-standing function |
| CNode | Base class for formula statistic node |
| COpString | |
| COpString< std::divides< Result > > | |
| COpString< std::minus< Result > > | |
| COpString< std::modulus< Result > > | |
| COpString< std::multiplies< Result > > | |
| COpString< std::negate< Result > > | |
| COpString< std::plus< Result > > | |
| COutput | |
| CProxyInfo | |
| ►CSampleStor | Templatized storage and interface for a distribution that calculates mean and variance |
| CParams | |
| CScalar | This is a simple scalar statistic, like a counter |
| CScalarBase | Implementation of a scalar stat |
| CScalarInfo | |
| CScalarInfoProxy | |
| CScalarPrint | |
| CScalarProxy | A proxy class to access the stat at a given index in a VectorBase stat |
| CScalarProxyNode | |
| CScalarStatNode | |
| CSparseHistBase | Implementation of a sparse histogram stat |
| CSparseHistData | Data structure of sparse histogram |
| CSparseHistInfo | |
| CSparseHistInfoProxy | |
| CSparseHistogram | |
| CSparseHistPrint | |
| ►CSparseHistStor | Templatized storage and interface for a sparse histogram stat |
| CParams | The parameters for a sparse histogram stat |
| CStandardDeviation | Calculates the mean and variance of all the samples |
| CStatEvent | Event to dump and/or reset the statistics |
| ►CStatStor | Templatized storage and interface for a simple scalar stat |
| CParams | |
| CStorageParams | |
| CSumNode | |
| CTemp | Helper class to construct formula node trees |
| CText | |
| CUnaryNode | |
| CValue | |
| CValueBase | |
| CValueProxy | |
| CVector | A vector of scalar stats |
| CVector2d | A 2-Dimensional vecto of scalar stats |
| CVector2dBase | |
| CVector2dInfo | |
| CVector2dInfoProxy | |
| CVectorAverageDeviation | This is a vector of AverageDeviation stats |
| CVectorBase | Implementation of a vector of stats |
| CVectorDistBase | |
| CVectorDistInfo | |
| CVectorDistInfoProxy | |
| CVectorDistribution | A vector of distributions |
| CVectorInfo | |
| CVectorInfoProxy | |
| CVectorPrint | |
| CVectorProxy | |
| CVectorStandardDeviation | This is a vector of StandardDeviation stats |
| CVectorStatNode | |
| ►Nstl_helpers | |
| ►Nhash_impl | |
| Chash | |
| Chash< std::pair< T, U > > | |
| Chash< std::tuple< T... > > | |
| Chash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > > | |
| Chash< T, std::enable_if_t< is_std_hash_enabled_v< T > > > | |
| NopExtract_impl | |
| CPrinter | |
| Cunordered_map | |
| Cunordered_set | |
| ►Ntlm | |
| ►Nchi | |
| Nruby_to_tlm | |
| Ntlm_to_ruby | |
| ►CCacheController | The tlm::chi::CacheController is a ruby CacheController which acts as a bridge between the AMBA TLM 2.0 implementation of CHI 1 with the gem5 (ruby) one |
| CDatalessTransaction | |
| CReadTransaction | |
| CTransaction | |
| CWriteTransaction | |
| ►CTlmGenerator | TlmGenerator: this class is basically a CHI-tlm traffic generator |
| ►CTransaction | Transaction object It stores ARM::CHI::Payload and ARM::CHI::Phase objects, and a list of action callables which will be executed in the order they have been registered once a transaction response arrives |
| CAction | Action: Does something without condition checking |
| CAssertion | Assertion: Will check for a specific condition and will fail if the condition is not met |
| CExpectation | Expectation: Will check for a specific condition and will warn if the condition is not met |
| ►CTransactionEvent | |
| CCompare | |
| ►Ntrace | |
| CArmCapstoneDisassembler | |
| ►CArmNativeTrace | |
| CThreadState | |
| CCapstoneDisassembler | Capstone Disassembler: The disassembler relies on the capstone library to convert the StaticInst encoding into the disassembled string |
| CExeTracer | |
| CExeTracerRecord | |
| CInstDisassembler | The base InstDisassembler class provides a one-API interface to disassemble the instruction passed as a first argument |
| CInstPBTrace | |
| CInstPBTraceRecord | This in an instruction tracer that records the flow of instructions through multiple cpus and systems to a protobuf file specified by proto/inst.proto for further analysis |
| ►CInstRecord | |
| CData | |
| CInstTracer | |
| CIntelTrace | |
| CIntelTraceRecord | |
| CLogger | Debug logging base class |
| CNativeTrace | |
| CNativeTraceRecord | |
| COstreamLogger | Logging wrapper for ostreams with the format: <when>: <name>: <message-body> |
| CSparcNativeTrace | |
| ►CTarmacBaseRecord | |
| CInstEntry | TARMAC instruction trace record |
| CMemEntry | TARMAC memory access trace record (stores only) |
| CRegEntry | TARMAC register trace record |
| CTarmacContext | This object type is encapsulating the informations needed by a Tarmac record to generate it's own entries |
| CTarmacParser | Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation status, comparing results and reporting architectural mismatches if any |
| ►CTarmacParserRecord | |
| CParserInstEntry | |
| CParserMemEntry | |
| CParserRegEntry | |
| CTarmacParserRecordEvent | Event triggered to check the value of the destination registers |
| CTarmacTracer | Tarmac Tracer: this tracer generates a new Tarmac Record for every instruction being executed in gem5 |
| ►CTarmacTracerRecord | TarmacTracer Record: Record generated by the TarmacTracer for every executed instruction |
| CTraceInstEntry | Instruction Entry |
| CTraceMemEntry | Memory Entry |
| CTraceRegEntry | Register Entry |
| ►CTarmacTracerRecordV8 | TarmacTracer record for ARMv8 CPUs: The record is adding some data to the base TarmacTracer record |
| CTraceEntryV8 | General data shared by all v8 entries |
| CTraceInstEntryV8 | Instruction entry for v8 records |
| CTraceMemEntryV8 | Memory Entry for V8 |
| CTraceRegEntryV8 | Register entry for v8 records |
| ►CX86NativeTrace | |
| CThreadState | |
| ►NVegaISA | Classes that represnt vector/scalar operands in VEGA ISA |
| CBufferRsrcDescriptor | |
| CDecoder | |
| CGPUISA | |
| ►CGpuTLB | |
| CCpuSidePort | |
| CMemSidePort | MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected |
| CTLBEvent | |
| CTranslation | |
| CVegaTLBStats | |
| CInFmt_DS | |
| CInFmt_DS_1 | |
| CInFmt_EXP | |
| CInFmt_EXP_1 | |
| CInFmt_FLAT | |
| CInFmt_FLAT_1 | |
| CInFmt_INST | |
| CInFmt_MIMG | |
| CInFmt_MIMG_1 | |
| CInFmt_MTBUF | |
| CInFmt_MTBUF_1 | |
| CInFmt_MUBUF | |
| CInFmt_MUBUF_1 | |
| CInFmt_SMEM | |
| CInFmt_SMEM_1 | |
| CInFmt_SOP1 | |
| CInFmt_SOP2 | |
| CInFmt_SOPC | |
| CInFmt_SOPK | |
| CInFmt_SOPP | |
| CInFmt_VINTRP | |
| CInFmt_VOP1 | |
| CInFmt_VOP2 | |
| CInFmt_VOP3_1 | |
| CInFmt_VOP3A | |
| CInFmt_VOP3B | |
| CInFmt_VOP3P | |
| CInFmt_VOP3P_1 | |
| CInFmt_VOP3P_MAI | |
| CInFmt_VOP3P_MAI_1 | |
| CInFmt_VOP_DPP | |
| CInFmt_VOP_SDWA | |
| CInFmt_VOP_SDWAB | |
| CInFmt_VOPC | |
| CInst_DS | |
| CInst_DS__DS_ADD_F32 | |
| CInst_DS__DS_ADD_RTN_F32 | |
| CInst_DS__DS_ADD_RTN_U32 | |
| CInst_DS__DS_ADD_RTN_U64 | |
| CInst_DS__DS_ADD_SRC2_F32 | |
| CInst_DS__DS_ADD_SRC2_U32 | |
| CInst_DS__DS_ADD_SRC2_U64 | |
| CInst_DS__DS_ADD_U32 | |
| CInst_DS__DS_ADD_U64 | |
| CInst_DS__DS_AND_B32 | |
| CInst_DS__DS_AND_B64 | |
| CInst_DS__DS_AND_RTN_B32 | |
| CInst_DS__DS_AND_RTN_B64 | |
| CInst_DS__DS_AND_SRC2_B32 | |
| CInst_DS__DS_AND_SRC2_B64 | |
| CInst_DS__DS_APPEND | |
| CInst_DS__DS_BPERMUTE_B32 | |
| CInst_DS__DS_CMPST_B32 | |
| CInst_DS__DS_CMPST_B64 | |
| CInst_DS__DS_CMPST_F32 | |
| CInst_DS__DS_CMPST_F64 | |
| CInst_DS__DS_CMPST_RTN_B32 | |
| CInst_DS__DS_CMPST_RTN_B64 | |
| CInst_DS__DS_CMPST_RTN_F32 | |
| CInst_DS__DS_CMPST_RTN_F64 | |
| CInst_DS__DS_CONDXCHG32_RTN_B64 | |
| CInst_DS__DS_CONSUME | |
| CInst_DS__DS_DEC_RTN_U32 | |
| CInst_DS__DS_DEC_RTN_U64 | |
| CInst_DS__DS_DEC_SRC2_U32 | |
| CInst_DS__DS_DEC_SRC2_U64 | |
| CInst_DS__DS_DEC_U32 | |
| CInst_DS__DS_DEC_U64 | |
| CInst_DS__DS_GWS_BARRIER | |
| CInst_DS__DS_GWS_INIT | |
| CInst_DS__DS_GWS_SEMA_BR | |
| CInst_DS__DS_GWS_SEMA_P | |
| CInst_DS__DS_GWS_SEMA_RELEASE_ALL | |
| CInst_DS__DS_GWS_SEMA_V | |
| CInst_DS__DS_INC_RTN_U32 | |
| CInst_DS__DS_INC_RTN_U64 | |
| CInst_DS__DS_INC_SRC2_U32 | |
| CInst_DS__DS_INC_SRC2_U64 | |
| CInst_DS__DS_INC_U32 | |
| CInst_DS__DS_INC_U64 | |
| CInst_DS__DS_MAX_F32 | |
| CInst_DS__DS_MAX_F64 | |
| CInst_DS__DS_MAX_I32 | |
| CInst_DS__DS_MAX_I64 | |
| CInst_DS__DS_MAX_RTN_F32 | |
| CInst_DS__DS_MAX_RTN_F64 | |
| CInst_DS__DS_MAX_RTN_I32 | |
| CInst_DS__DS_MAX_RTN_I64 | |
| CInst_DS__DS_MAX_RTN_U32 | |
| CInst_DS__DS_MAX_RTN_U64 | |
| CInst_DS__DS_MAX_SRC2_F32 | |
| CInst_DS__DS_MAX_SRC2_F64 | |
| CInst_DS__DS_MAX_SRC2_I32 | |
| CInst_DS__DS_MAX_SRC2_I64 | |
| CInst_DS__DS_MAX_SRC2_U32 | |
| CInst_DS__DS_MAX_SRC2_U64 | |
| CInst_DS__DS_MAX_U32 | |
| CInst_DS__DS_MAX_U64 | |
| CInst_DS__DS_MIN_F32 | |
| CInst_DS__DS_MIN_F64 | |
| CInst_DS__DS_MIN_I32 | |
| CInst_DS__DS_MIN_I64 | |
| CInst_DS__DS_MIN_RTN_F32 | |
| CInst_DS__DS_MIN_RTN_F64 | |
| CInst_DS__DS_MIN_RTN_I32 | |
| CInst_DS__DS_MIN_RTN_I64 | |
| CInst_DS__DS_MIN_RTN_U32 | |
| CInst_DS__DS_MIN_RTN_U64 | |
| CInst_DS__DS_MIN_SRC2_F32 | |
| CInst_DS__DS_MIN_SRC2_F64 | |
| CInst_DS__DS_MIN_SRC2_I32 | |
| CInst_DS__DS_MIN_SRC2_I64 | |
| CInst_DS__DS_MIN_SRC2_U32 | |
| CInst_DS__DS_MIN_SRC2_U64 | |
| CInst_DS__DS_MIN_U32 | |
| CInst_DS__DS_MIN_U64 | |
| CInst_DS__DS_MSKOR_B32 | |
| CInst_DS__DS_MSKOR_B64 | |
| CInst_DS__DS_MSKOR_RTN_B32 | |
| CInst_DS__DS_MSKOR_RTN_B64 | |
| CInst_DS__DS_NOP | |
| CInst_DS__DS_OR_B32 | |
| CInst_DS__DS_OR_B64 | |
| CInst_DS__DS_OR_RTN_B32 | |
| CInst_DS__DS_OR_RTN_B64 | |
| CInst_DS__DS_OR_SRC2_B32 | |
| CInst_DS__DS_OR_SRC2_B64 | |
| CInst_DS__DS_ORDERED_COUNT | |
| CInst_DS__DS_PERMUTE_B32 | |
| CInst_DS__DS_READ2_B32 | |
| CInst_DS__DS_READ2_B64 | |
| CInst_DS__DS_READ2ST64_B32 | |
| CInst_DS__DS_READ2ST64_B64 | |
| CInst_DS__DS_READ_B128 | |
| CInst_DS__DS_READ_B32 | |
| CInst_DS__DS_READ_B64 | |
| CInst_DS__DS_READ_B96 | |
| CInst_DS__DS_READ_I16 | |
| CInst_DS__DS_READ_I8 | |
| CInst_DS__DS_READ_U16 | |
| CInst_DS__DS_READ_U16_D16 | |
| CInst_DS__DS_READ_U16_D16_HI | |
| CInst_DS__DS_READ_U8 | |
| CInst_DS__DS_RSUB_RTN_U32 | |
| CInst_DS__DS_RSUB_RTN_U64 | |
| CInst_DS__DS_RSUB_SRC2_U32 | |
| CInst_DS__DS_RSUB_SRC2_U64 | |
| CInst_DS__DS_RSUB_U32 | |
| CInst_DS__DS_RSUB_U64 | |
| CInst_DS__DS_SUB_RTN_U32 | |
| CInst_DS__DS_SUB_RTN_U64 | |
| CInst_DS__DS_SUB_SRC2_U32 | |
| CInst_DS__DS_SUB_SRC2_U64 | |
| CInst_DS__DS_SUB_U32 | |
| CInst_DS__DS_SUB_U64 | |
| CInst_DS__DS_SWIZZLE_B32 | |
| CInst_DS__DS_WRAP_RTN_B32 | |
| CInst_DS__DS_WRITE2_B32 | |
| CInst_DS__DS_WRITE2_B64 | |
| CInst_DS__DS_WRITE2ST64_B32 | |
| CInst_DS__DS_WRITE2ST64_B64 | |
| CInst_DS__DS_WRITE_B128 | |
| CInst_DS__DS_WRITE_B16 | |
| CInst_DS__DS_WRITE_B32 | |
| CInst_DS__DS_WRITE_B64 | |
| CInst_DS__DS_WRITE_B8 | |
| CInst_DS__DS_WRITE_B8_D16_HI | |
| CInst_DS__DS_WRITE_B96 | |
| CInst_DS__DS_WRITE_SRC2_B32 | |
| CInst_DS__DS_WRITE_SRC2_B64 | |
| CInst_DS__DS_WRXCHG2_RTN_B32 | |
| CInst_DS__DS_WRXCHG2_RTN_B64 | |
| CInst_DS__DS_WRXCHG2ST64_RTN_B32 | |
| CInst_DS__DS_WRXCHG2ST64_RTN_B64 | |
| CInst_DS__DS_WRXCHG_RTN_B32 | |
| CInst_DS__DS_WRXCHG_RTN_B64 | |
| CInst_DS__DS_XOR_B32 | |
| CInst_DS__DS_XOR_B64 | |
| CInst_DS__DS_XOR_RTN_B32 | |
| CInst_DS__DS_XOR_RTN_B64 | |
| CInst_DS__DS_XOR_SRC2_B32 | |
| CInst_DS__DS_XOR_SRC2_B64 | |
| CInst_EXP | |
| CInst_EXP__EXP | |
| CInst_FLAT | |
| CInst_FLAT__FLAT_ATOMIC_ADD | |
| CInst_FLAT__FLAT_ATOMIC_ADD_F32 | |
| CInst_FLAT__FLAT_ATOMIC_ADD_F64 | |
| CInst_FLAT__FLAT_ATOMIC_ADD_X2 | |
| CInst_FLAT__FLAT_ATOMIC_AND | |
| CInst_FLAT__FLAT_ATOMIC_AND_X2 | |
| CInst_FLAT__FLAT_ATOMIC_CMPSWAP | |
| CInst_FLAT__FLAT_ATOMIC_CMPSWAP_X2 | |
| CInst_FLAT__FLAT_ATOMIC_DEC | |
| CInst_FLAT__FLAT_ATOMIC_DEC_X2 | |
| CInst_FLAT__FLAT_ATOMIC_INC | |
| CInst_FLAT__FLAT_ATOMIC_INC_X2 | |
| CInst_FLAT__FLAT_ATOMIC_MAX_F64 | |
| CInst_FLAT__FLAT_ATOMIC_MIN_F64 | |
| CInst_FLAT__FLAT_ATOMIC_OR | |
| CInst_FLAT__FLAT_ATOMIC_OR_X2 | |
| CInst_FLAT__FLAT_ATOMIC_PK_ADD_F16 | |
| CInst_FLAT__FLAT_ATOMIC_SMAX | |
| CInst_FLAT__FLAT_ATOMIC_SMAX_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SMIN | |
| CInst_FLAT__FLAT_ATOMIC_SMIN_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SUB | |
| CInst_FLAT__FLAT_ATOMIC_SUB_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SWAP | |
| CInst_FLAT__FLAT_ATOMIC_SWAP_X2 | |
| CInst_FLAT__FLAT_ATOMIC_UMAX | |
| CInst_FLAT__FLAT_ATOMIC_UMAX_X2 | |
| CInst_FLAT__FLAT_ATOMIC_UMIN | |
| CInst_FLAT__FLAT_ATOMIC_UMIN_X2 | |
| CInst_FLAT__FLAT_ATOMIC_XOR | |
| CInst_FLAT__FLAT_ATOMIC_XOR_X2 | |
| CInst_FLAT__FLAT_LOAD_DWORD | |
| CInst_FLAT__FLAT_LOAD_DWORDX2 | |
| CInst_FLAT__FLAT_LOAD_DWORDX3 | |
| CInst_FLAT__FLAT_LOAD_DWORDX4 | |
| CInst_FLAT__FLAT_LOAD_SBYTE | |
| CInst_FLAT__FLAT_LOAD_SSHORT | |
| CInst_FLAT__FLAT_LOAD_UBYTE | |
| CInst_FLAT__FLAT_LOAD_USHORT | |
| CInst_FLAT__FLAT_STORE_BYTE | |
| CInst_FLAT__FLAT_STORE_DWORD | |
| CInst_FLAT__FLAT_STORE_DWORDX2 | |
| CInst_FLAT__FLAT_STORE_DWORDX3 | |
| CInst_FLAT__FLAT_STORE_DWORDX4 | |
| CInst_FLAT__FLAT_STORE_SHORT | |
| CInst_FLAT__FLAT_STORE_SHORT_D16_HI | |
| CInst_MIMG | |
| CInst_MIMG__IMAGE_ATOMIC_ADD | |
| CInst_MIMG__IMAGE_ATOMIC_AND | |
| CInst_MIMG__IMAGE_ATOMIC_CMPSWAP | |
| CInst_MIMG__IMAGE_ATOMIC_DEC | |
| CInst_MIMG__IMAGE_ATOMIC_INC | |
| CInst_MIMG__IMAGE_ATOMIC_OR | |
| CInst_MIMG__IMAGE_ATOMIC_SMAX | |
| CInst_MIMG__IMAGE_ATOMIC_SMIN | |
| CInst_MIMG__IMAGE_ATOMIC_SUB | |
| CInst_MIMG__IMAGE_ATOMIC_SWAP | |
| CInst_MIMG__IMAGE_ATOMIC_UMAX | |
| CInst_MIMG__IMAGE_ATOMIC_UMIN | |
| CInst_MIMG__IMAGE_ATOMIC_XOR | |
| CInst_MIMG__IMAGE_GATHER4 | |
| CInst_MIMG__IMAGE_GATHER4_B | |
| CInst_MIMG__IMAGE_GATHER4_B_CL | |
| CInst_MIMG__IMAGE_GATHER4_B_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_B_O | |
| CInst_MIMG__IMAGE_GATHER4_C | |
| CInst_MIMG__IMAGE_GATHER4_C_B | |
| CInst_MIMG__IMAGE_GATHER4_C_B_CL | |
| CInst_MIMG__IMAGE_GATHER4_C_B_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_C_B_O | |
| CInst_MIMG__IMAGE_GATHER4_C_CL | |
| CInst_MIMG__IMAGE_GATHER4_C_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_C_L | |
| CInst_MIMG__IMAGE_GATHER4_C_L_O | |
| CInst_MIMG__IMAGE_GATHER4_C_LZ | |
| CInst_MIMG__IMAGE_GATHER4_C_LZ_O | |
| CInst_MIMG__IMAGE_GATHER4_C_O | |
| CInst_MIMG__IMAGE_GATHER4_CL | |
| CInst_MIMG__IMAGE_GATHER4_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_L | |
| CInst_MIMG__IMAGE_GATHER4_L_O | |
| CInst_MIMG__IMAGE_GATHER4_LZ | |
| CInst_MIMG__IMAGE_GATHER4_LZ_O | |
| CInst_MIMG__IMAGE_GATHER4_O | |
| CInst_MIMG__IMAGE_GET_LOD | |
| CInst_MIMG__IMAGE_GET_RESINFO | |
| CInst_MIMG__IMAGE_LOAD | |
| CInst_MIMG__IMAGE_LOAD_MIP | |
| CInst_MIMG__IMAGE_LOAD_MIP_PCK | |
| CInst_MIMG__IMAGE_LOAD_MIP_PCK_SGN | |
| CInst_MIMG__IMAGE_LOAD_PCK | |
| CInst_MIMG__IMAGE_LOAD_PCK_SGN | |
| CInst_MIMG__IMAGE_SAMPLE | |
| CInst_MIMG__IMAGE_SAMPLE_B | |
| CInst_MIMG__IMAGE_SAMPLE_B_CL | |
| CInst_MIMG__IMAGE_SAMPLE_B_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_B_O | |
| CInst_MIMG__IMAGE_SAMPLE_C | |
| CInst_MIMG__IMAGE_SAMPLE_C_B | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_D | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_L | |
| CInst_MIMG__IMAGE_SAMPLE_C_L_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_LZ | |
| CInst_MIMG__IMAGE_SAMPLE_C_LZ_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_O | |
| CInst_MIMG__IMAGE_SAMPLE_CD | |
| CInst_MIMG__IMAGE_SAMPLE_CD_CL | |
| CInst_MIMG__IMAGE_SAMPLE_CD_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_CD_O | |
| CInst_MIMG__IMAGE_SAMPLE_CL | |
| CInst_MIMG__IMAGE_SAMPLE_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_D | |
| CInst_MIMG__IMAGE_SAMPLE_D_CL | |
| CInst_MIMG__IMAGE_SAMPLE_D_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_D_O | |
| CInst_MIMG__IMAGE_SAMPLE_L | |
| CInst_MIMG__IMAGE_SAMPLE_L_O | |
| CInst_MIMG__IMAGE_SAMPLE_LZ | |
| CInst_MIMG__IMAGE_SAMPLE_LZ_O | |
| CInst_MIMG__IMAGE_SAMPLE_O | |
| CInst_MIMG__IMAGE_STORE | |
| CInst_MIMG__IMAGE_STORE_MIP | |
| CInst_MIMG__IMAGE_STORE_MIP_PCK | |
| CInst_MIMG__IMAGE_STORE_PCK | |
| CInst_MTBUF | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_X | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XY | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_X | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_X | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XY | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XYZ | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XYZW | |
| CInst_MUBUF | |
| CInst_MUBUF__BUFFER_ATOMIC_ADD | |
| CInst_MUBUF__BUFFER_ATOMIC_ADD_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_AND | |
| CInst_MUBUF__BUFFER_ATOMIC_AND_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_CMPSWAP | |
| CInst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_DEC | |
| CInst_MUBUF__BUFFER_ATOMIC_DEC_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_INC | |
| CInst_MUBUF__BUFFER_ATOMIC_INC_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_OR | |
| CInst_MUBUF__BUFFER_ATOMIC_OR_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SMAX | |
| CInst_MUBUF__BUFFER_ATOMIC_SMAX_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SMIN | |
| CInst_MUBUF__BUFFER_ATOMIC_SMIN_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SUB | |
| CInst_MUBUF__BUFFER_ATOMIC_SUB_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SWAP | |
| CInst_MUBUF__BUFFER_ATOMIC_SWAP_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_UMAX | |
| CInst_MUBUF__BUFFER_ATOMIC_UMAX_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_UMIN | |
| CInst_MUBUF__BUFFER_ATOMIC_UMIN_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_XOR | |
| CInst_MUBUF__BUFFER_ATOMIC_XOR_X2 | |
| CInst_MUBUF__BUFFER_LOAD_DWORD | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX2 | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX3 | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX4 | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_X | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_X | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XY | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XYZ | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XYZW | |
| CInst_MUBUF__BUFFER_LOAD_SBYTE | |
| CInst_MUBUF__BUFFER_LOAD_SHORT_D16 | |
| CInst_MUBUF__BUFFER_LOAD_SHORT_D16_HI | |
| CInst_MUBUF__BUFFER_LOAD_SSHORT | |
| CInst_MUBUF__BUFFER_LOAD_UBYTE | |
| CInst_MUBUF__BUFFER_LOAD_USHORT | |
| CInst_MUBUF__BUFFER_STORE_BYTE | |
| CInst_MUBUF__BUFFER_STORE_DWORD | |
| CInst_MUBUF__BUFFER_STORE_DWORDX2 | |
| CInst_MUBUF__BUFFER_STORE_DWORDX3 | |
| CInst_MUBUF__BUFFER_STORE_DWORDX4 | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_X | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XY | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_X | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XY | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XYZ | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XYZW | |
| CInst_MUBUF__BUFFER_STORE_LDS_DWORD | |
| CInst_MUBUF__BUFFER_STORE_SHORT | |
| CInst_MUBUF__BUFFER_WBINVL1 | |
| CInst_MUBUF__BUFFER_WBINVL1_VOL | |
| CInst_SMEM | |
| CInst_SMEM__S_ATC_PROBE | |
| CInst_SMEM__S_ATC_PROBE_BUFFER | |
| CInst_SMEM__S_BUFFER_LOAD_DWORD | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX16 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX2 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX4 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX8 | |
| CInst_SMEM__S_BUFFER_STORE_DWORD | |
| CInst_SMEM__S_BUFFER_STORE_DWORDX2 | |
| CInst_SMEM__S_BUFFER_STORE_DWORDX4 | |
| CInst_SMEM__S_DCACHE_INV | |
| CInst_SMEM__S_DCACHE_INV_VOL | |
| CInst_SMEM__S_DCACHE_WB | |
| CInst_SMEM__S_DCACHE_WB_VOL | |
| CInst_SMEM__S_LOAD_DWORD | |
| CInst_SMEM__S_LOAD_DWORDX16 | |
| CInst_SMEM__S_LOAD_DWORDX2 | |
| CInst_SMEM__S_LOAD_DWORDX4 | |
| CInst_SMEM__S_LOAD_DWORDX8 | |
| CInst_SMEM__S_MEMREALTIME | |
| CInst_SMEM__S_MEMTIME | |
| CInst_SMEM__S_STORE_DWORD | |
| CInst_SMEM__S_STORE_DWORDX2 | |
| CInst_SMEM__S_STORE_DWORDX4 | |
| CInst_SOP1 | |
| CInst_SOP1__S_ABS_I32 | |
| CInst_SOP1__S_AND_SAVEEXEC_B64 | |
| CInst_SOP1__S_ANDN2_SAVEEXEC_B64 | |
| CInst_SOP1__S_BCNT0_I32_B32 | |
| CInst_SOP1__S_BCNT0_I32_B64 | |
| CInst_SOP1__S_BCNT1_I32_B32 | |
| CInst_SOP1__S_BCNT1_I32_B64 | |
| CInst_SOP1__S_BITSET0_B32 | |
| CInst_SOP1__S_BITSET0_B64 | |
| CInst_SOP1__S_BITSET1_B32 | |
| CInst_SOP1__S_BITSET1_B64 | |
| CInst_SOP1__S_BREV_B32 | |
| CInst_SOP1__S_BREV_B64 | |
| CInst_SOP1__S_CBRANCH_JOIN | |
| CInst_SOP1__S_CMOV_B32 | |
| CInst_SOP1__S_CMOV_B64 | |
| CInst_SOP1__S_FF0_I32_B32 | |
| CInst_SOP1__S_FF0_I32_B64 | |
| CInst_SOP1__S_FF1_I32_B32 | |
| CInst_SOP1__S_FF1_I32_B64 | |
| CInst_SOP1__S_FLBIT_I32 | |
| CInst_SOP1__S_FLBIT_I32_B32 | |
| CInst_SOP1__S_FLBIT_I32_B64 | |
| CInst_SOP1__S_FLBIT_I32_I64 | |
| CInst_SOP1__S_GETPC_B64 | |
| CInst_SOP1__S_MOV_B32 | |
| CInst_SOP1__S_MOV_B64 | |
| CInst_SOP1__S_MOV_FED_B32 | |
| CInst_SOP1__S_MOVRELD_B32 | |
| CInst_SOP1__S_MOVRELD_B64 | |
| CInst_SOP1__S_MOVRELS_B32 | |
| CInst_SOP1__S_MOVRELS_B64 | |
| CInst_SOP1__S_NAND_SAVEEXEC_B64 | |
| CInst_SOP1__S_NOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_NOT_B32 | |
| CInst_SOP1__S_NOT_B64 | |
| CInst_SOP1__S_OR_SAVEEXEC_B64 | |
| CInst_SOP1__S_ORN2_SAVEEXEC_B64 | |
| CInst_SOP1__S_QUADMASK_B32 | |
| CInst_SOP1__S_QUADMASK_B64 | |
| CInst_SOP1__S_RFE_B64 | |
| CInst_SOP1__S_SET_GPR_IDX_IDX | |
| CInst_SOP1__S_SETPC_B64 | |
| CInst_SOP1__S_SEXT_I32_I16 | |
| CInst_SOP1__S_SEXT_I32_I8 | |
| CInst_SOP1__S_SWAPPC_B64 | |
| CInst_SOP1__S_WQM_B32 | |
| CInst_SOP1__S_WQM_B64 | |
| CInst_SOP1__S_XNOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_XOR_SAVEEXEC_B64 | |
| CInst_SOP2 | |
| CInst_SOP2__S_ABSDIFF_I32 | |
| CInst_SOP2__S_ADD_I32 | |
| CInst_SOP2__S_ADD_U32 | |
| CInst_SOP2__S_ADDC_U32 | |
| CInst_SOP2__S_AND_B32 | |
| CInst_SOP2__S_AND_B64 | |
| CInst_SOP2__S_ANDN2_B32 | |
| CInst_SOP2__S_ANDN2_B64 | |
| CInst_SOP2__S_ASHR_I32 | |
| CInst_SOP2__S_ASHR_I64 | |
| CInst_SOP2__S_BFE_I32 | |
| CInst_SOP2__S_BFE_I64 | |
| CInst_SOP2__S_BFE_U32 | |
| CInst_SOP2__S_BFE_U64 | |
| CInst_SOP2__S_BFM_B32 | |
| CInst_SOP2__S_BFM_B64 | |
| CInst_SOP2__S_CBRANCH_G_FORK | |
| CInst_SOP2__S_CSELECT_B32 | |
| CInst_SOP2__S_CSELECT_B64 | |
| CInst_SOP2__S_LSHL_B32 | |
| CInst_SOP2__S_LSHL_B64 | |
| CInst_SOP2__S_LSHR_B32 | |
| CInst_SOP2__S_LSHR_B64 | |
| CInst_SOP2__S_MAX_I32 | |
| CInst_SOP2__S_MAX_U32 | |
| CInst_SOP2__S_MIN_I32 | |
| CInst_SOP2__S_MIN_U32 | |
| CInst_SOP2__S_MUL_HI_I32 | |
| CInst_SOP2__S_MUL_HI_U32 | |
| CInst_SOP2__S_MUL_I32 | |
| CInst_SOP2__S_NAND_B32 | |
| CInst_SOP2__S_NAND_B64 | |
| CInst_SOP2__S_NOR_B32 | |
| CInst_SOP2__S_NOR_B64 | |
| CInst_SOP2__S_OR_B32 | |
| CInst_SOP2__S_OR_B64 | |
| CInst_SOP2__S_ORN2_B32 | |
| CInst_SOP2__S_ORN2_B64 | |
| CInst_SOP2__S_RFE_RESTORE_B64 | |
| CInst_SOP2__S_SUB_I32 | |
| CInst_SOP2__S_SUB_U32 | |
| CInst_SOP2__S_SUBB_U32 | |
| CInst_SOP2__S_XNOR_B32 | |
| CInst_SOP2__S_XNOR_B64 | |
| CInst_SOP2__S_XOR_B32 | |
| CInst_SOP2__S_XOR_B64 | |
| CInst_SOPC | |
| CInst_SOPC__S_BITCMP0_B32 | |
| CInst_SOPC__S_BITCMP0_B64 | |
| CInst_SOPC__S_BITCMP1_B32 | |
| CInst_SOPC__S_BITCMP1_B64 | |
| CInst_SOPC__S_CMP_EQ_I32 | |
| CInst_SOPC__S_CMP_EQ_U32 | |
| CInst_SOPC__S_CMP_EQ_U64 | |
| CInst_SOPC__S_CMP_GE_I32 | |
| CInst_SOPC__S_CMP_GE_U32 | |
| CInst_SOPC__S_CMP_GT_I32 | |
| CInst_SOPC__S_CMP_GT_U32 | |
| CInst_SOPC__S_CMP_LE_I32 | |
| CInst_SOPC__S_CMP_LE_U32 | |
| CInst_SOPC__S_CMP_LG_I32 | |
| CInst_SOPC__S_CMP_LG_U32 | |
| CInst_SOPC__S_CMP_LG_U64 | |
| CInst_SOPC__S_CMP_LT_I32 | |
| CInst_SOPC__S_CMP_LT_U32 | |
| CInst_SOPC__S_SET_GPR_IDX_ON | |
| CInst_SOPC__S_SETVSKIP | |
| CInst_SOPK | |
| CInst_SOPK__S_ADDK_I32 | |
| CInst_SOPK__S_CBRANCH_I_FORK | |
| CInst_SOPK__S_CMOVK_I32 | |
| CInst_SOPK__S_CMPK_EQ_I32 | |
| CInst_SOPK__S_CMPK_EQ_U32 | |
| CInst_SOPK__S_CMPK_GE_I32 | |
| CInst_SOPK__S_CMPK_GE_U32 | |
| CInst_SOPK__S_CMPK_GT_I32 | |
| CInst_SOPK__S_CMPK_GT_U32 | |
| CInst_SOPK__S_CMPK_LE_I32 | |
| CInst_SOPK__S_CMPK_LE_U32 | |
| CInst_SOPK__S_CMPK_LG_I32 | |
| CInst_SOPK__S_CMPK_LG_U32 | |
| CInst_SOPK__S_CMPK_LT_I32 | |
| CInst_SOPK__S_CMPK_LT_U32 | |
| CInst_SOPK__S_GETREG_B32 | |
| CInst_SOPK__S_MOVK_I32 | |
| CInst_SOPK__S_MULK_I32 | |
| CInst_SOPK__S_SETREG_B32 | |
| CInst_SOPK__S_SETREG_IMM32_B32 | |
| CInst_SOPP | |
| CInst_SOPP__S_BARRIER | |
| CInst_SOPP__S_BRANCH | |
| CInst_SOPP__S_CBRANCH_CDBGSYS | |
| CInst_SOPP__S_CBRANCH_CDBGSYS_AND_USER | |
| CInst_SOPP__S_CBRANCH_CDBGSYS_OR_USER | |
| CInst_SOPP__S_CBRANCH_CDBGUSER | |
| CInst_SOPP__S_CBRANCH_EXECNZ | |
| CInst_SOPP__S_CBRANCH_EXECZ | |
| CInst_SOPP__S_CBRANCH_SCC0 | |
| CInst_SOPP__S_CBRANCH_SCC1 | |
| CInst_SOPP__S_CBRANCH_VCCNZ | |
| CInst_SOPP__S_CBRANCH_VCCZ | |
| CInst_SOPP__S_DECPERFLEVEL | |
| CInst_SOPP__S_ENDPGM | |
| CInst_SOPP__S_ENDPGM_SAVED | |
| CInst_SOPP__S_ICACHE_INV | |
| CInst_SOPP__S_INCPERFLEVEL | |
| CInst_SOPP__S_NOP | |
| CInst_SOPP__S_SENDMSG | |
| CInst_SOPP__S_SENDMSGHALT | |
| CInst_SOPP__S_SET_GPR_IDX_MODE | |
| CInst_SOPP__S_SET_GPR_IDX_OFF | |
| CInst_SOPP__S_SETHALT | |
| CInst_SOPP__S_SETKILL | |
| CInst_SOPP__S_SETPRIO | |
| CInst_SOPP__S_SLEEP | |
| CInst_SOPP__S_TRAP | |
| CInst_SOPP__S_TTRACEDATA | |
| CInst_SOPP__S_WAITCNT | |
| CInst_SOPP__S_WAKEUP | |
| CInst_VINTRP | |
| CInst_VINTRP__V_INTERP_MOV_F32 | |
| CInst_VINTRP__V_INTERP_P1_F32 | |
| CInst_VINTRP__V_INTERP_P2_F32 | |
| CInst_VOP1 | |
| CInst_VOP1__V_ACCVGPR_MOV_B32 | |
| CInst_VOP1__V_BFREV_B32 | |
| CInst_VOP1__V_CEIL_F16 | |
| CInst_VOP1__V_CEIL_F32 | |
| CInst_VOP1__V_CEIL_F64 | |
| CInst_VOP1__V_CLREXCP | |
| CInst_VOP1__V_COS_F16 | |
| CInst_VOP1__V_COS_F32 | |
| CInst_VOP1__V_CVT_F16_F32 | |
| CInst_VOP1__V_CVT_F16_I16 | |
| CInst_VOP1__V_CVT_F16_U16 | |
| CInst_VOP1__V_CVT_F32_F16 | |
| CInst_VOP1__V_CVT_F32_F64 | |
| CInst_VOP1__V_CVT_F32_I32 | |
| CInst_VOP1__V_CVT_F32_U32 | |
| CInst_VOP1__V_CVT_F32_UBYTE0 | |
| CInst_VOP1__V_CVT_F32_UBYTE1 | |
| CInst_VOP1__V_CVT_F32_UBYTE2 | |
| CInst_VOP1__V_CVT_F32_UBYTE3 | |
| CInst_VOP1__V_CVT_F64_F32 | |
| CInst_VOP1__V_CVT_F64_I32 | |
| CInst_VOP1__V_CVT_F64_U32 | |
| CInst_VOP1__V_CVT_FLR_I32_F32 | |
| CInst_VOP1__V_CVT_I16_F16 | |
| CInst_VOP1__V_CVT_I32_F32 | |
| CInst_VOP1__V_CVT_I32_F64 | |
| CInst_VOP1__V_CVT_OFF_F32_I4 | |
| CInst_VOP1__V_CVT_RPI_I32_F32 | |
| CInst_VOP1__V_CVT_U16_F16 | |
| CInst_VOP1__V_CVT_U32_F32 | |
| CInst_VOP1__V_CVT_U32_F64 | |
| CInst_VOP1__V_EXP_F16 | |
| CInst_VOP1__V_EXP_F32 | |
| CInst_VOP1__V_EXP_LEGACY_F32 | |
| CInst_VOP1__V_FFBH_I32 | |
| CInst_VOP1__V_FFBH_U32 | |
| CInst_VOP1__V_FFBL_B32 | |
| CInst_VOP1__V_FLOOR_F16 | |
| CInst_VOP1__V_FLOOR_F32 | |
| CInst_VOP1__V_FLOOR_F64 | |
| CInst_VOP1__V_FRACT_F16 | |
| CInst_VOP1__V_FRACT_F32 | |
| CInst_VOP1__V_FRACT_F64 | |
| CInst_VOP1__V_FREXP_EXP_I16_F16 | |
| CInst_VOP1__V_FREXP_EXP_I32_F32 | |
| CInst_VOP1__V_FREXP_EXP_I32_F64 | |
| CInst_VOP1__V_FREXP_MANT_F16 | |
| CInst_VOP1__V_FREXP_MANT_F32 | |
| CInst_VOP1__V_FREXP_MANT_F64 | |
| CInst_VOP1__V_LOG_F16 | |
| CInst_VOP1__V_LOG_F32 | |
| CInst_VOP1__V_LOG_LEGACY_F32 | |
| CInst_VOP1__V_MOV_B32 | |
| CInst_VOP1__V_MOV_B64 | |
| CInst_VOP1__V_MOV_FED_B32 | |
| CInst_VOP1__V_NOP | |
| CInst_VOP1__V_NOT_B32 | |
| CInst_VOP1__V_RCP_F16 | |
| CInst_VOP1__V_RCP_F32 | |
| CInst_VOP1__V_RCP_F64 | |
| CInst_VOP1__V_RCP_IFLAG_F32 | |
| CInst_VOP1__V_READFIRSTLANE_B32 | |
| CInst_VOP1__V_RNDNE_F16 | |
| CInst_VOP1__V_RNDNE_F32 | |
| CInst_VOP1__V_RNDNE_F64 | |
| CInst_VOP1__V_RSQ_F16 | |
| CInst_VOP1__V_RSQ_F32 | |
| CInst_VOP1__V_RSQ_F64 | |
| CInst_VOP1__V_SIN_F16 | |
| CInst_VOP1__V_SIN_F32 | |
| CInst_VOP1__V_SQRT_F16 | |
| CInst_VOP1__V_SQRT_F32 | |
| CInst_VOP1__V_SQRT_F64 | |
| CInst_VOP1__V_TRUNC_F16 | |
| CInst_VOP1__V_TRUNC_F32 | |
| CInst_VOP1__V_TRUNC_F64 | |
| CInst_VOP2 | |
| CInst_VOP2__V_ADD_CO_U32 | |
| CInst_VOP2__V_ADD_F16 | |
| CInst_VOP2__V_ADD_F32 | |
| CInst_VOP2__V_ADD_U16 | |
| CInst_VOP2__V_ADD_U32 | |
| CInst_VOP2__V_ADDC_CO_U32 | |
| CInst_VOP2__V_AND_B32 | |
| CInst_VOP2__V_ASHRREV_I16 | |
| CInst_VOP2__V_ASHRREV_I32 | |
| CInst_VOP2__V_CNDMASK_B32 | |
| CInst_VOP2__V_FMAC_F32 | |
| CInst_VOP2__V_LDEXP_F16 | |
| CInst_VOP2__V_LSHLREV_B16 | |
| CInst_VOP2__V_LSHLREV_B32 | |
| CInst_VOP2__V_LSHRREV_B16 | |
| CInst_VOP2__V_LSHRREV_B32 | |
| CInst_VOP2__V_MAC_F16 | |
| CInst_VOP2__V_MAC_F32 | |
| CInst_VOP2__V_MADAK_F16 | |
| CInst_VOP2__V_MADAK_F32 | |
| CInst_VOP2__V_MADMK_F16 | |
| CInst_VOP2__V_MADMK_F32 | |
| CInst_VOP2__V_MAX_F16 | |
| CInst_VOP2__V_MAX_F32 | |
| CInst_VOP2__V_MAX_I16 | |
| CInst_VOP2__V_MAX_I32 | |
| CInst_VOP2__V_MAX_U16 | |
| CInst_VOP2__V_MAX_U32 | |
| CInst_VOP2__V_MIN_F16 | |
| CInst_VOP2__V_MIN_F32 | |
| CInst_VOP2__V_MIN_I16 | |
| CInst_VOP2__V_MIN_I32 | |
| CInst_VOP2__V_MIN_U16 | |
| CInst_VOP2__V_MIN_U32 | |
| CInst_VOP2__V_MUL_F16 | |
| CInst_VOP2__V_MUL_F32 | |
| CInst_VOP2__V_MUL_HI_I32_I24 | |
| CInst_VOP2__V_MUL_HI_U32_U24 | |
| CInst_VOP2__V_MUL_I32_I24 | |
| CInst_VOP2__V_MUL_LEGACY_F32 | |
| CInst_VOP2__V_MUL_LO_U16 | |
| CInst_VOP2__V_MUL_U32_U24 | |
| CInst_VOP2__V_OR_B32 | |
| CInst_VOP2__V_SUB_CO_U32 | |
| CInst_VOP2__V_SUB_F16 | |
| CInst_VOP2__V_SUB_F32 | |
| CInst_VOP2__V_SUB_U16 | |
| CInst_VOP2__V_SUB_U32 | |
| CInst_VOP2__V_SUBB_CO_U32 | |
| CInst_VOP2__V_SUBBREV_CO_U32 | |
| CInst_VOP2__V_SUBREV_CO_U32 | |
| CInst_VOP2__V_SUBREV_F16 | |
| CInst_VOP2__V_SUBREV_F32 | |
| CInst_VOP2__V_SUBREV_U16 | |
| CInst_VOP2__V_SUBREV_U32 | |
| CInst_VOP2__V_XNOR_B32 | |
| CInst_VOP2__V_XOR_B32 | |
| CInst_VOP3__V_ADD3_U32 | |
| CInst_VOP3__V_ADD_CO_U32 | |
| CInst_VOP3__V_ADD_F16 | |
| CInst_VOP3__V_ADD_F32 | |
| CInst_VOP3__V_ADD_F64 | |
| CInst_VOP3__V_ADD_LSHL_U32 | |
| CInst_VOP3__V_ADD_U16 | |
| CInst_VOP3__V_ADD_U32 | |
| CInst_VOP3__V_ADDC_CO_U32 | |
| CInst_VOP3__V_ALIGNBIT_B32 | |
| CInst_VOP3__V_ALIGNBYTE_B32 | |
| CInst_VOP3__V_AND_B32 | |
| CInst_VOP3__V_AND_OR_B32 | |
| CInst_VOP3__V_ASHRREV_I16 | |
| CInst_VOP3__V_ASHRREV_I32 | |
| CInst_VOP3__V_ASHRREV_I64 | |
| CInst_VOP3__V_BCNT_U32_B32 | |
| CInst_VOP3__V_BFE_I32 | |
| CInst_VOP3__V_BFE_U32 | |
| CInst_VOP3__V_BFI_B32 | |
| CInst_VOP3__V_BFM_B32 | |
| CInst_VOP3__V_BFREV_B32 | |
| CInst_VOP3__V_CEIL_F16 | |
| CInst_VOP3__V_CEIL_F32 | |
| CInst_VOP3__V_CEIL_F64 | |
| CInst_VOP3__V_CLREXCP | |
| CInst_VOP3__V_CMP_CLASS_F16 | |
| CInst_VOP3__V_CMP_CLASS_F32 | |
| CInst_VOP3__V_CMP_CLASS_F64 | |
| CInst_VOP3__V_CMP_EQ_F16 | |
| CInst_VOP3__V_CMP_EQ_F32 | |
| CInst_VOP3__V_CMP_EQ_F64 | |
| CInst_VOP3__V_CMP_EQ_I16 | |
| CInst_VOP3__V_CMP_EQ_I32 | |
| CInst_VOP3__V_CMP_EQ_I64 | |
| CInst_VOP3__V_CMP_EQ_U16 | |
| CInst_VOP3__V_CMP_EQ_U32 | |
| CInst_VOP3__V_CMP_EQ_U64 | |
| CInst_VOP3__V_CMP_F_F16 | |
| CInst_VOP3__V_CMP_F_F32 | |
| CInst_VOP3__V_CMP_F_F64 | |
| CInst_VOP3__V_CMP_F_I16 | |
| CInst_VOP3__V_CMP_F_I32 | |
| CInst_VOP3__V_CMP_F_I64 | |
| CInst_VOP3__V_CMP_F_U16 | |
| CInst_VOP3__V_CMP_F_U32 | |
| CInst_VOP3__V_CMP_F_U64 | |
| CInst_VOP3__V_CMP_GE_F16 | |
| CInst_VOP3__V_CMP_GE_F32 | |
| CInst_VOP3__V_CMP_GE_F64 | |
| CInst_VOP3__V_CMP_GE_I16 | |
| CInst_VOP3__V_CMP_GE_I32 | |
| CInst_VOP3__V_CMP_GE_I64 | |
| CInst_VOP3__V_CMP_GE_U16 | |
| CInst_VOP3__V_CMP_GE_U32 | |
| CInst_VOP3__V_CMP_GE_U64 | |
| CInst_VOP3__V_CMP_GT_F16 | |
| CInst_VOP3__V_CMP_GT_F32 | |
| CInst_VOP3__V_CMP_GT_F64 | |
| CInst_VOP3__V_CMP_GT_I16 | |
| CInst_VOP3__V_CMP_GT_I32 | |
| CInst_VOP3__V_CMP_GT_I64 | |
| CInst_VOP3__V_CMP_GT_U16 | |
| CInst_VOP3__V_CMP_GT_U32 | |
| CInst_VOP3__V_CMP_GT_U64 | |
| CInst_VOP3__V_CMP_LE_F16 | |
| CInst_VOP3__V_CMP_LE_F32 | |
| CInst_VOP3__V_CMP_LE_F64 | |
| CInst_VOP3__V_CMP_LE_I16 | |
| CInst_VOP3__V_CMP_LE_I32 | |
| CInst_VOP3__V_CMP_LE_I64 | |
| CInst_VOP3__V_CMP_LE_U16 | |
| CInst_VOP3__V_CMP_LE_U32 | |
| CInst_VOP3__V_CMP_LE_U64 | |
| CInst_VOP3__V_CMP_LG_F16 | |
| CInst_VOP3__V_CMP_LG_F32 | |
| CInst_VOP3__V_CMP_LG_F64 | |
| CInst_VOP3__V_CMP_LT_F16 | |
| CInst_VOP3__V_CMP_LT_F32 | |
| CInst_VOP3__V_CMP_LT_F64 | |
| CInst_VOP3__V_CMP_LT_I16 | |
| CInst_VOP3__V_CMP_LT_I32 | |
| CInst_VOP3__V_CMP_LT_I64 | |
| CInst_VOP3__V_CMP_LT_U16 | |
| CInst_VOP3__V_CMP_LT_U32 | |
| CInst_VOP3__V_CMP_LT_U64 | |
| CInst_VOP3__V_CMP_NE_I16 | |
| CInst_VOP3__V_CMP_NE_I32 | |
| CInst_VOP3__V_CMP_NE_I64 | |
| CInst_VOP3__V_CMP_NE_U16 | |
| CInst_VOP3__V_CMP_NE_U32 | |
| CInst_VOP3__V_CMP_NE_U64 | |
| CInst_VOP3__V_CMP_NEQ_F16 | |
| CInst_VOP3__V_CMP_NEQ_F32 | |
| CInst_VOP3__V_CMP_NEQ_F64 | |
| CInst_VOP3__V_CMP_NGE_F16 | |
| CInst_VOP3__V_CMP_NGE_F32 | |
| CInst_VOP3__V_CMP_NGE_F64 | |
| CInst_VOP3__V_CMP_NGT_F16 | |
| CInst_VOP3__V_CMP_NGT_F32 | |
| CInst_VOP3__V_CMP_NGT_F64 | |
| CInst_VOP3__V_CMP_NLE_F16 | |
| CInst_VOP3__V_CMP_NLE_F32 | |
| CInst_VOP3__V_CMP_NLE_F64 | |
| CInst_VOP3__V_CMP_NLG_F16 | |
| CInst_VOP3__V_CMP_NLG_F32 | |
| CInst_VOP3__V_CMP_NLG_F64 | |
| CInst_VOP3__V_CMP_NLT_F16 | |
| CInst_VOP3__V_CMP_NLT_F32 | |
| CInst_VOP3__V_CMP_NLT_F64 | |
| CInst_VOP3__V_CMP_O_F16 | |
| CInst_VOP3__V_CMP_O_F32 | |
| CInst_VOP3__V_CMP_O_F64 | |
| CInst_VOP3__V_CMP_T_I16 | |
| CInst_VOP3__V_CMP_T_I32 | |
| CInst_VOP3__V_CMP_T_I64 | |
| CInst_VOP3__V_CMP_T_U16 | |
| CInst_VOP3__V_CMP_T_U32 | |
| CInst_VOP3__V_CMP_T_U64 | |
| CInst_VOP3__V_CMP_TRU_F16 | |
| CInst_VOP3__V_CMP_TRU_F32 | |
| CInst_VOP3__V_CMP_TRU_F64 | |
| CInst_VOP3__V_CMP_U_F16 | |
| CInst_VOP3__V_CMP_U_F32 | |
| CInst_VOP3__V_CMP_U_F64 | |
| CInst_VOP3__V_CMPX_CLASS_F16 | |
| CInst_VOP3__V_CMPX_CLASS_F32 | |
| CInst_VOP3__V_CMPX_CLASS_F64 | |
| CInst_VOP3__V_CMPX_EQ_F16 | |
| CInst_VOP3__V_CMPX_EQ_F32 | |
| CInst_VOP3__V_CMPX_EQ_F64 | |
| CInst_VOP3__V_CMPX_EQ_I16 | |
| CInst_VOP3__V_CMPX_EQ_I32 | |
| CInst_VOP3__V_CMPX_EQ_I64 | |
| CInst_VOP3__V_CMPX_EQ_U16 | |
| CInst_VOP3__V_CMPX_EQ_U32 | |
| CInst_VOP3__V_CMPX_EQ_U64 | |
| CInst_VOP3__V_CMPX_F_F16 | |
| CInst_VOP3__V_CMPX_F_F32 | |
| CInst_VOP3__V_CMPX_F_F64 | |
| CInst_VOP3__V_CMPX_F_I16 | |
| CInst_VOP3__V_CMPX_F_I32 | |
| CInst_VOP3__V_CMPX_F_I64 | |
| CInst_VOP3__V_CMPX_F_U16 | |
| CInst_VOP3__V_CMPX_F_U32 | |
| CInst_VOP3__V_CMPX_F_U64 | |
| CInst_VOP3__V_CMPX_GE_F16 | |
| CInst_VOP3__V_CMPX_GE_F32 | |
| CInst_VOP3__V_CMPX_GE_F64 | |
| CInst_VOP3__V_CMPX_GE_I16 | |
| CInst_VOP3__V_CMPX_GE_I32 | |
| CInst_VOP3__V_CMPX_GE_I64 | |
| CInst_VOP3__V_CMPX_GE_U16 | |
| CInst_VOP3__V_CMPX_GE_U32 | |
| CInst_VOP3__V_CMPX_GE_U64 | |
| CInst_VOP3__V_CMPX_GT_F16 | |
| CInst_VOP3__V_CMPX_GT_F32 | |
| CInst_VOP3__V_CMPX_GT_F64 | |
| CInst_VOP3__V_CMPX_GT_I16 | |
| CInst_VOP3__V_CMPX_GT_I32 | |
| CInst_VOP3__V_CMPX_GT_I64 | |
| CInst_VOP3__V_CMPX_GT_U16 | |
| CInst_VOP3__V_CMPX_GT_U32 | |
| CInst_VOP3__V_CMPX_GT_U64 | |
| CInst_VOP3__V_CMPX_LE_F16 | |
| CInst_VOP3__V_CMPX_LE_F32 | |
| CInst_VOP3__V_CMPX_LE_F64 | |
| CInst_VOP3__V_CMPX_LE_I16 | |
| CInst_VOP3__V_CMPX_LE_I32 | |
| CInst_VOP3__V_CMPX_LE_I64 | |
| CInst_VOP3__V_CMPX_LE_U16 | |
| CInst_VOP3__V_CMPX_LE_U32 | |
| CInst_VOP3__V_CMPX_LE_U64 | |
| CInst_VOP3__V_CMPX_LG_F16 | |
| CInst_VOP3__V_CMPX_LG_F32 | |
| CInst_VOP3__V_CMPX_LG_F64 | |
| CInst_VOP3__V_CMPX_LT_F16 | |
| CInst_VOP3__V_CMPX_LT_F32 | |
| CInst_VOP3__V_CMPX_LT_F64 | |
| CInst_VOP3__V_CMPX_LT_I16 | |
| CInst_VOP3__V_CMPX_LT_I32 | |
| CInst_VOP3__V_CMPX_LT_I64 | |
| CInst_VOP3__V_CMPX_LT_U16 | |
| CInst_VOP3__V_CMPX_LT_U32 | |
| CInst_VOP3__V_CMPX_LT_U64 | |
| CInst_VOP3__V_CMPX_NE_I16 | |
| CInst_VOP3__V_CMPX_NE_I32 | |
| CInst_VOP3__V_CMPX_NE_I64 | |
| CInst_VOP3__V_CMPX_NE_U16 | |
| CInst_VOP3__V_CMPX_NE_U32 | |
| CInst_VOP3__V_CMPX_NE_U64 | |
| CInst_VOP3__V_CMPX_NEQ_F16 | |
| CInst_VOP3__V_CMPX_NEQ_F32 | |
| CInst_VOP3__V_CMPX_NEQ_F64 | |
| CInst_VOP3__V_CMPX_NGE_F16 | |
| CInst_VOP3__V_CMPX_NGE_F32 | |
| CInst_VOP3__V_CMPX_NGE_F64 | |
| CInst_VOP3__V_CMPX_NGT_F16 | |
| CInst_VOP3__V_CMPX_NGT_F32 | |
| CInst_VOP3__V_CMPX_NGT_F64 | |
| CInst_VOP3__V_CMPX_NLE_F16 | |
| CInst_VOP3__V_CMPX_NLE_F32 | |
| CInst_VOP3__V_CMPX_NLE_F64 | |
| CInst_VOP3__V_CMPX_NLG_F16 | |
| CInst_VOP3__V_CMPX_NLG_F32 | |
| CInst_VOP3__V_CMPX_NLG_F64 | |
| CInst_VOP3__V_CMPX_NLT_F16 | |
| CInst_VOP3__V_CMPX_NLT_F32 | |
| CInst_VOP3__V_CMPX_NLT_F64 | |
| CInst_VOP3__V_CMPX_O_F16 | |
| CInst_VOP3__V_CMPX_O_F32 | |
| CInst_VOP3__V_CMPX_O_F64 | |
| CInst_VOP3__V_CMPX_T_I16 | |
| CInst_VOP3__V_CMPX_T_I32 | |
| CInst_VOP3__V_CMPX_T_I64 | |
| CInst_VOP3__V_CMPX_T_U16 | |
| CInst_VOP3__V_CMPX_T_U32 | |
| CInst_VOP3__V_CMPX_T_U64 | |
| CInst_VOP3__V_CMPX_TRU_F16 | |
| CInst_VOP3__V_CMPX_TRU_F32 | |
| CInst_VOP3__V_CMPX_TRU_F64 | |
| CInst_VOP3__V_CMPX_U_F16 | |
| CInst_VOP3__V_CMPX_U_F32 | |
| CInst_VOP3__V_CMPX_U_F64 | |
| CInst_VOP3__V_CNDMASK_B32 | |
| CInst_VOP3__V_COS_F16 | |
| CInst_VOP3__V_COS_F32 | |
| CInst_VOP3__V_CUBEID_F32 | |
| CInst_VOP3__V_CUBEMA_F32 | |
| CInst_VOP3__V_CUBESC_F32 | |
| CInst_VOP3__V_CUBETC_F32 | |
| CInst_VOP3__V_CVT_F16_F32 | |
| CInst_VOP3__V_CVT_F16_I16 | |
| CInst_VOP3__V_CVT_F16_U16 | |
| CInst_VOP3__V_CVT_F32_F16 | |
| CInst_VOP3__V_CVT_F32_F64 | |
| CInst_VOP3__V_CVT_F32_I32 | |
| CInst_VOP3__V_CVT_F32_U32 | |
| CInst_VOP3__V_CVT_F32_UBYTE0 | |
| CInst_VOP3__V_CVT_F32_UBYTE1 | |
| CInst_VOP3__V_CVT_F32_UBYTE2 | |
| CInst_VOP3__V_CVT_F32_UBYTE3 | |
| CInst_VOP3__V_CVT_F64_F32 | |
| CInst_VOP3__V_CVT_F64_I32 | |
| CInst_VOP3__V_CVT_F64_U32 | |
| CInst_VOP3__V_CVT_FLR_I32_F32 | |
| CInst_VOP3__V_CVT_I16_F16 | |
| CInst_VOP3__V_CVT_I32_F32 | |
| CInst_VOP3__V_CVT_I32_F64 | |
| CInst_VOP3__V_CVT_OFF_F32_I4 | |
| CInst_VOP3__V_CVT_PK_FP8_F32 | |
| CInst_VOP3__V_CVT_PK_I16_I32 | |
| CInst_VOP3__V_CVT_PK_U16_U32 | |
| CInst_VOP3__V_CVT_PK_U8_F32 | |
| CInst_VOP3__V_CVT_PKACCUM_U8_F32 | |
| CInst_VOP3__V_CVT_PKNORM_I16_F32 | |
| CInst_VOP3__V_CVT_PKNORM_U16_F32 | |
| CInst_VOP3__V_CVT_PKRTZ_F16_F32 | |
| CInst_VOP3__V_CVT_RPI_I32_F32 | |
| CInst_VOP3__V_CVT_U16_F16 | |
| CInst_VOP3__V_CVT_U32_F32 | |
| CInst_VOP3__V_CVT_U32_F64 | |
| CInst_VOP3__V_DIV_FIXUP_F16 | |
| CInst_VOP3__V_DIV_FIXUP_F32 | |
| CInst_VOP3__V_DIV_FIXUP_F64 | |
| CInst_VOP3__V_DIV_FMAS_F32 | |
| CInst_VOP3__V_DIV_FMAS_F64 | |
| CInst_VOP3__V_DIV_SCALE_F32 | |
| CInst_VOP3__V_DIV_SCALE_F64 | |
| CInst_VOP3__V_EXP_F16 | |
| CInst_VOP3__V_EXP_F32 | |
| CInst_VOP3__V_EXP_LEGACY_F32 | |
| CInst_VOP3__V_FFBH_I32 | |
| CInst_VOP3__V_FFBH_U32 | |
| CInst_VOP3__V_FFBL_B32 | |
| CInst_VOP3__V_FLOOR_F16 | |
| CInst_VOP3__V_FLOOR_F32 | |
| CInst_VOP3__V_FLOOR_F64 | |
| CInst_VOP3__V_FMA_F16 | |
| CInst_VOP3__V_FMA_F32 | |
| CInst_VOP3__V_FMA_F64 | |
| CInst_VOP3__V_FMAC_F32 | |
| CInst_VOP3__V_FRACT_F16 | |
| CInst_VOP3__V_FRACT_F32 | |
| CInst_VOP3__V_FRACT_F64 | |
| CInst_VOP3__V_FREXP_EXP_I16_F16 | |
| CInst_VOP3__V_FREXP_EXP_I32_F32 | |
| CInst_VOP3__V_FREXP_EXP_I32_F64 | |
| CInst_VOP3__V_FREXP_MANT_F16 | |
| CInst_VOP3__V_FREXP_MANT_F32 | |
| CInst_VOP3__V_FREXP_MANT_F64 | |
| CInst_VOP3__V_INTERP_MOV_F32 | |
| CInst_VOP3__V_INTERP_P1_F32 | |
| CInst_VOP3__V_INTERP_P1LL_F16 | |
| CInst_VOP3__V_INTERP_P1LV_F16 | |
| CInst_VOP3__V_INTERP_P2_F16 | |
| CInst_VOP3__V_INTERP_P2_F32 | |
| CInst_VOP3__V_LDEXP_F16 | |
| CInst_VOP3__V_LDEXP_F32 | |
| CInst_VOP3__V_LDEXP_F64 | |
| CInst_VOP3__V_LERP_U8 | |
| CInst_VOP3__V_LOG_F16 | |
| CInst_VOP3__V_LOG_F32 | |
| CInst_VOP3__V_LOG_LEGACY_F32 | |
| CInst_VOP3__V_LSHL_ADD_U32 | |
| CInst_VOP3__V_LSHL_ADD_U64 | |
| CInst_VOP3__V_LSHL_OR_B32 | |
| CInst_VOP3__V_LSHLREV_B16 | |
| CInst_VOP3__V_LSHLREV_B32 | |
| CInst_VOP3__V_LSHLREV_B64 | |
| CInst_VOP3__V_LSHRREV_B16 | |
| CInst_VOP3__V_LSHRREV_B32 | |
| CInst_VOP3__V_LSHRREV_B64 | |
| CInst_VOP3__V_MAC_F16 | |
| CInst_VOP3__V_MAC_F32 | |
| CInst_VOP3__V_MAD_F16 | |
| CInst_VOP3__V_MAD_F32 | |
| CInst_VOP3__V_MAD_I16 | |
| CInst_VOP3__V_MAD_I32_I24 | |
| CInst_VOP3__V_MAD_I64_I32 | |
| CInst_VOP3__V_MAD_LEGACY_F32 | |
| CInst_VOP3__V_MAD_U16 | |
| CInst_VOP3__V_MAD_U32_U24 | |
| CInst_VOP3__V_MAD_U64_U32 | |
| CInst_VOP3__V_MAX3_F32 | |
| CInst_VOP3__V_MAX3_I32 | |
| CInst_VOP3__V_MAX3_U32 | |
| CInst_VOP3__V_MAX_F16 | |
| CInst_VOP3__V_MAX_F32 | |
| CInst_VOP3__V_MAX_F64 | |
| CInst_VOP3__V_MAX_I16 | |
| CInst_VOP3__V_MAX_I32 | |
| CInst_VOP3__V_MAX_U16 | |
| CInst_VOP3__V_MAX_U32 | |
| CInst_VOP3__V_MBCNT_HI_U32_B32 | |
| CInst_VOP3__V_MBCNT_LO_U32_B32 | |
| CInst_VOP3__V_MED3_F32 | |
| CInst_VOP3__V_MED3_I32 | |
| CInst_VOP3__V_MED3_U32 | |
| CInst_VOP3__V_MIN3_F32 | |
| CInst_VOP3__V_MIN3_I32 | |
| CInst_VOP3__V_MIN3_U32 | |
| CInst_VOP3__V_MIN_F16 | |
| CInst_VOP3__V_MIN_F32 | |
| CInst_VOP3__V_MIN_F64 | |
| CInst_VOP3__V_MIN_I16 | |
| CInst_VOP3__V_MIN_I32 | |
| CInst_VOP3__V_MIN_U16 | |
| CInst_VOP3__V_MIN_U32 | |
| CInst_VOP3__V_MOV_B32 | |
| CInst_VOP3__V_MOV_FED_B32 | |
| CInst_VOP3__V_MQSAD_PK_U16_U8 | |
| CInst_VOP3__V_MQSAD_U32_U8 | |
| CInst_VOP3__V_MSAD_U8 | |
| CInst_VOP3__V_MUL_F16 | |
| CInst_VOP3__V_MUL_F32 | |
| CInst_VOP3__V_MUL_F64 | |
| CInst_VOP3__V_MUL_HI_I32 | |
| CInst_VOP3__V_MUL_HI_I32_I24 | |
| CInst_VOP3__V_MUL_HI_U32 | |
| CInst_VOP3__V_MUL_HI_U32_U24 | |
| CInst_VOP3__V_MUL_I32_I24 | |
| CInst_VOP3__V_MUL_LEGACY_F32 | |
| CInst_VOP3__V_MUL_LO_U16 | |
| CInst_VOP3__V_MUL_LO_U32 | |
| CInst_VOP3__V_MUL_U32_U24 | |
| CInst_VOP3__V_NOP | |
| CInst_VOP3__V_NOT_B32 | |
| CInst_VOP3__V_OR3_B32 | |
| CInst_VOP3__V_OR_B32 | |
| CInst_VOP3__V_PERM_B32 | |
| CInst_VOP3__V_QSAD_PK_U16_U8 | |
| CInst_VOP3__V_RCP_F16 | |
| CInst_VOP3__V_RCP_F32 | |
| CInst_VOP3__V_RCP_F64 | |
| CInst_VOP3__V_RCP_IFLAG_F32 | |
| CInst_VOP3__V_READLANE_B32 | |
| CInst_VOP3__V_RNDNE_F16 | |
| CInst_VOP3__V_RNDNE_F32 | |
| CInst_VOP3__V_RNDNE_F64 | |
| CInst_VOP3__V_RSQ_F16 | |
| CInst_VOP3__V_RSQ_F32 | |
| CInst_VOP3__V_RSQ_F64 | |
| CInst_VOP3__V_SAD_HI_U8 | |
| CInst_VOP3__V_SAD_U16 | |
| CInst_VOP3__V_SAD_U32 | |
| CInst_VOP3__V_SAD_U8 | |
| CInst_VOP3__V_SIN_F16 | |
| CInst_VOP3__V_SIN_F32 | |
| CInst_VOP3__V_SQRT_F16 | |
| CInst_VOP3__V_SQRT_F32 | |
| CInst_VOP3__V_SQRT_F64 | |
| CInst_VOP3__V_SUB_CO_U32 | |
| CInst_VOP3__V_SUB_F16 | |
| CInst_VOP3__V_SUB_F32 | |
| CInst_VOP3__V_SUB_U16 | |
| CInst_VOP3__V_SUB_U32 | |
| CInst_VOP3__V_SUBB_CO_U32 | |
| CInst_VOP3__V_SUBBREV_CO_U32 | |
| CInst_VOP3__V_SUBREV_CO_U32 | |
| CInst_VOP3__V_SUBREV_F16 | |
| CInst_VOP3__V_SUBREV_F32 | |
| CInst_VOP3__V_SUBREV_U16 | |
| CInst_VOP3__V_SUBREV_U32 | |
| CInst_VOP3__V_TRIG_PREOP_F64 | |
| CInst_VOP3__V_TRUNC_F16 | |
| CInst_VOP3__V_TRUNC_F32 | |
| CInst_VOP3__V_TRUNC_F64 | |
| CInst_VOP3__V_WRITELANE_B32 | |
| CInst_VOP3__V_XAD_U32 | |
| CInst_VOP3__V_XOR_B32 | |
| CInst_VOP3A | |
| CInst_VOP3B | |
| CInst_VOP3P | |
| CInst_VOP3P__1OP | |
| CInst_VOP3P__2OP_X16 | |
| CInst_VOP3P__3OP_X16 | |
| CInst_VOP3P__V_ACCVGPR_READ | |
| CInst_VOP3P__V_ACCVGPR_WRITE | |
| CInst_VOP3P__V_DOT2_F32_F16 | |
| CInst_VOP3P__V_DOT2_I32_I16 | |
| CInst_VOP3P__V_DOT2_U32_U16 | |
| CInst_VOP3P__V_DOT4_I32_I8 | |
| CInst_VOP3P__V_DOT4_U32_U8 | |
| CInst_VOP3P__V_DOT8_I32_I4 | |
| CInst_VOP3P__V_DOT8_U32_U4 | |
| CInst_VOP3P__V_PK_ADD_F16 | |
| CInst_VOP3P__V_PK_ADD_F32 | |
| CInst_VOP3P__V_PK_ADD_I16 | |
| CInst_VOP3P__V_PK_ADD_U16 | |
| CInst_VOP3P__V_PK_ASHRREV_B16 | |
| CInst_VOP3P__V_PK_FMA_F16 | |
| CInst_VOP3P__V_PK_FMA_F32 | |
| CInst_VOP3P__V_PK_LSHLREV_B16 | |
| CInst_VOP3P__V_PK_LSHRREV_B16 | |
| CInst_VOP3P__V_PK_MAD_I16 | |
| CInst_VOP3P__V_PK_MAD_U16 | |
| CInst_VOP3P__V_PK_MAX_F16 | |
| CInst_VOP3P__V_PK_MAX_I16 | |
| CInst_VOP3P__V_PK_MAX_U16 | |
| CInst_VOP3P__V_PK_MIN_F16 | |
| CInst_VOP3P__V_PK_MIN_I16 | |
| CInst_VOP3P__V_PK_MIN_U16 | |
| CInst_VOP3P__V_PK_MOV_B32 | |
| CInst_VOP3P__V_PK_MUL_F16 | |
| CInst_VOP3P__V_PK_MUL_F32 | |
| CInst_VOP3P__V_PK_MUL_LO_U16 | |
| CInst_VOP3P__V_PK_SUB_I16 | |
| CInst_VOP3P__V_PK_SUB_U16 | |
| CInst_VOP3P_MAI | |
| CInst_VOP3P_MAI__V_MFMA | |
| CInst_VOP3P_MAI__V_MFMA_I8 | |
| CInst_VOP3P_MAI__V_MFMA_MXFP | |
| CInst_VOPC | |
| CInst_VOPC__V_CMP_CLASS_F16 | |
| CInst_VOPC__V_CMP_CLASS_F32 | |
| CInst_VOPC__V_CMP_CLASS_F64 | |
| CInst_VOPC__V_CMP_EQ_F16 | |
| CInst_VOPC__V_CMP_EQ_F32 | |
| CInst_VOPC__V_CMP_EQ_F64 | |
| CInst_VOPC__V_CMP_EQ_I16 | |
| CInst_VOPC__V_CMP_EQ_I32 | |
| CInst_VOPC__V_CMP_EQ_I64 | |
| CInst_VOPC__V_CMP_EQ_U16 | |
| CInst_VOPC__V_CMP_EQ_U32 | |
| CInst_VOPC__V_CMP_EQ_U64 | |
| CInst_VOPC__V_CMP_F_F16 | |
| CInst_VOPC__V_CMP_F_F32 | |
| CInst_VOPC__V_CMP_F_F64 | |
| CInst_VOPC__V_CMP_F_I16 | |
| CInst_VOPC__V_CMP_F_I32 | |
| CInst_VOPC__V_CMP_F_I64 | |
| CInst_VOPC__V_CMP_F_U16 | |
| CInst_VOPC__V_CMP_F_U32 | |
| CInst_VOPC__V_CMP_F_U64 | |
| CInst_VOPC__V_CMP_GE_F16 | |
| CInst_VOPC__V_CMP_GE_F32 | |
| CInst_VOPC__V_CMP_GE_F64 | |
| CInst_VOPC__V_CMP_GE_I16 | |
| CInst_VOPC__V_CMP_GE_I32 | |
| CInst_VOPC__V_CMP_GE_I64 | |
| CInst_VOPC__V_CMP_GE_U16 | |
| CInst_VOPC__V_CMP_GE_U32 | |
| CInst_VOPC__V_CMP_GE_U64 | |
| CInst_VOPC__V_CMP_GT_F16 | |
| CInst_VOPC__V_CMP_GT_F32 | |
| CInst_VOPC__V_CMP_GT_F64 | |
| CInst_VOPC__V_CMP_GT_I16 | |
| CInst_VOPC__V_CMP_GT_I32 | |
| CInst_VOPC__V_CMP_GT_I64 | |
| CInst_VOPC__V_CMP_GT_U16 | |
| CInst_VOPC__V_CMP_GT_U32 | |
| CInst_VOPC__V_CMP_GT_U64 | |
| CInst_VOPC__V_CMP_LE_F16 | |
| CInst_VOPC__V_CMP_LE_F32 | |
| CInst_VOPC__V_CMP_LE_F64 | |
| CInst_VOPC__V_CMP_LE_I16 | |
| CInst_VOPC__V_CMP_LE_I32 | |
| CInst_VOPC__V_CMP_LE_I64 | |
| CInst_VOPC__V_CMP_LE_U16 | |
| CInst_VOPC__V_CMP_LE_U32 | |
| CInst_VOPC__V_CMP_LE_U64 | |
| CInst_VOPC__V_CMP_LG_F16 | |
| CInst_VOPC__V_CMP_LG_F32 | |
| CInst_VOPC__V_CMP_LG_F64 | |
| CInst_VOPC__V_CMP_LT_F16 | |
| CInst_VOPC__V_CMP_LT_F32 | |
| CInst_VOPC__V_CMP_LT_F64 | |
| CInst_VOPC__V_CMP_LT_I16 | |
| CInst_VOPC__V_CMP_LT_I32 | |
| CInst_VOPC__V_CMP_LT_I64 | |
| CInst_VOPC__V_CMP_LT_U16 | |
| CInst_VOPC__V_CMP_LT_U32 | |
| CInst_VOPC__V_CMP_LT_U64 | |
| CInst_VOPC__V_CMP_NE_I16 | |
| CInst_VOPC__V_CMP_NE_I32 | |
| CInst_VOPC__V_CMP_NE_I64 | |
| CInst_VOPC__V_CMP_NE_U16 | |
| CInst_VOPC__V_CMP_NE_U32 | |
| CInst_VOPC__V_CMP_NE_U64 | |
| CInst_VOPC__V_CMP_NEQ_F16 | |
| CInst_VOPC__V_CMP_NEQ_F32 | |
| CInst_VOPC__V_CMP_NEQ_F64 | |
| CInst_VOPC__V_CMP_NGE_F16 | |
| CInst_VOPC__V_CMP_NGE_F32 | |
| CInst_VOPC__V_CMP_NGE_F64 | |
| CInst_VOPC__V_CMP_NGT_F16 | |
| CInst_VOPC__V_CMP_NGT_F32 | |
| CInst_VOPC__V_CMP_NGT_F64 | |
| CInst_VOPC__V_CMP_NLE_F16 | |
| CInst_VOPC__V_CMP_NLE_F32 | |
| CInst_VOPC__V_CMP_NLE_F64 | |
| CInst_VOPC__V_CMP_NLG_F16 | |
| CInst_VOPC__V_CMP_NLG_F32 | |
| CInst_VOPC__V_CMP_NLG_F64 | |
| CInst_VOPC__V_CMP_NLT_F16 | |
| CInst_VOPC__V_CMP_NLT_F32 | |
| CInst_VOPC__V_CMP_NLT_F64 | |
| CInst_VOPC__V_CMP_O_F16 | |
| CInst_VOPC__V_CMP_O_F32 | |
| CInst_VOPC__V_CMP_O_F64 | |
| CInst_VOPC__V_CMP_T_I16 | |
| CInst_VOPC__V_CMP_T_I32 | |
| CInst_VOPC__V_CMP_T_I64 | |
| CInst_VOPC__V_CMP_T_U16 | |
| CInst_VOPC__V_CMP_T_U32 | |
| CInst_VOPC__V_CMP_T_U64 | |
| CInst_VOPC__V_CMP_TRU_F16 | |
| CInst_VOPC__V_CMP_TRU_F32 | |
| CInst_VOPC__V_CMP_TRU_F64 | |
| CInst_VOPC__V_CMP_U_F16 | |
| CInst_VOPC__V_CMP_U_F32 | |
| CInst_VOPC__V_CMP_U_F64 | |
| CInst_VOPC__V_CMPX_CLASS_F16 | |
| CInst_VOPC__V_CMPX_CLASS_F32 | |
| CInst_VOPC__V_CMPX_CLASS_F64 | |
| CInst_VOPC__V_CMPX_EQ_F16 | |
| CInst_VOPC__V_CMPX_EQ_F32 | |
| CInst_VOPC__V_CMPX_EQ_F64 | |
| CInst_VOPC__V_CMPX_EQ_I16 | |
| CInst_VOPC__V_CMPX_EQ_I32 | |
| CInst_VOPC__V_CMPX_EQ_I64 | |
| CInst_VOPC__V_CMPX_EQ_U16 | |
| CInst_VOPC__V_CMPX_EQ_U32 | |
| CInst_VOPC__V_CMPX_EQ_U64 | |
| CInst_VOPC__V_CMPX_F_F16 | |
| CInst_VOPC__V_CMPX_F_F32 | |
| CInst_VOPC__V_CMPX_F_F64 | |
| CInst_VOPC__V_CMPX_F_I16 | |
| CInst_VOPC__V_CMPX_F_I32 | |
| CInst_VOPC__V_CMPX_F_I64 | |
| CInst_VOPC__V_CMPX_F_U16 | |
| CInst_VOPC__V_CMPX_F_U32 | |
| CInst_VOPC__V_CMPX_F_U64 | |
| CInst_VOPC__V_CMPX_GE_F16 | |
| CInst_VOPC__V_CMPX_GE_F32 | |
| CInst_VOPC__V_CMPX_GE_F64 | |
| CInst_VOPC__V_CMPX_GE_I16 | |
| CInst_VOPC__V_CMPX_GE_I32 | |
| CInst_VOPC__V_CMPX_GE_I64 | |
| CInst_VOPC__V_CMPX_GE_U16 | |
| CInst_VOPC__V_CMPX_GE_U32 | |
| CInst_VOPC__V_CMPX_GE_U64 | |
| CInst_VOPC__V_CMPX_GT_F16 | |
| CInst_VOPC__V_CMPX_GT_F32 | |
| CInst_VOPC__V_CMPX_GT_F64 | |
| CInst_VOPC__V_CMPX_GT_I16 | |
| CInst_VOPC__V_CMPX_GT_I32 | |
| CInst_VOPC__V_CMPX_GT_I64 | |
| CInst_VOPC__V_CMPX_GT_U16 | |
| CInst_VOPC__V_CMPX_GT_U32 | |
| CInst_VOPC__V_CMPX_GT_U64 | |
| CInst_VOPC__V_CMPX_LE_F16 | |
| CInst_VOPC__V_CMPX_LE_F32 | |
| CInst_VOPC__V_CMPX_LE_F64 | |
| CInst_VOPC__V_CMPX_LE_I16 | |
| CInst_VOPC__V_CMPX_LE_I32 | |
| CInst_VOPC__V_CMPX_LE_I64 | |
| CInst_VOPC__V_CMPX_LE_U16 | |
| CInst_VOPC__V_CMPX_LE_U32 | |
| CInst_VOPC__V_CMPX_LE_U64 | |
| CInst_VOPC__V_CMPX_LG_F16 | |
| CInst_VOPC__V_CMPX_LG_F32 | |
| CInst_VOPC__V_CMPX_LG_F64 | |
| CInst_VOPC__V_CMPX_LT_F16 | |
| CInst_VOPC__V_CMPX_LT_F32 | |
| CInst_VOPC__V_CMPX_LT_F64 | |
| CInst_VOPC__V_CMPX_LT_I16 | |
| CInst_VOPC__V_CMPX_LT_I32 | |
| CInst_VOPC__V_CMPX_LT_I64 | |
| CInst_VOPC__V_CMPX_LT_U16 | |
| CInst_VOPC__V_CMPX_LT_U32 | |
| CInst_VOPC__V_CMPX_LT_U64 | |
| CInst_VOPC__V_CMPX_NE_I16 | |
| CInst_VOPC__V_CMPX_NE_I32 | |
| CInst_VOPC__V_CMPX_NE_I64 | |
| CInst_VOPC__V_CMPX_NE_U16 | |
| CInst_VOPC__V_CMPX_NE_U32 | |
| CInst_VOPC__V_CMPX_NE_U64 | |
| CInst_VOPC__V_CMPX_NEQ_F16 | |
| CInst_VOPC__V_CMPX_NEQ_F32 | |
| CInst_VOPC__V_CMPX_NEQ_F64 | |
| CInst_VOPC__V_CMPX_NGE_F16 | |
| CInst_VOPC__V_CMPX_NGE_F32 | |
| CInst_VOPC__V_CMPX_NGE_F64 | |
| CInst_VOPC__V_CMPX_NGT_F16 | |
| CInst_VOPC__V_CMPX_NGT_F32 | |
| CInst_VOPC__V_CMPX_NGT_F64 | |
| CInst_VOPC__V_CMPX_NLE_F16 | |
| CInst_VOPC__V_CMPX_NLE_F32 | |
| CInst_VOPC__V_CMPX_NLE_F64 | |
| CInst_VOPC__V_CMPX_NLG_F16 | |
| CInst_VOPC__V_CMPX_NLG_F32 | |
| CInst_VOPC__V_CMPX_NLG_F64 | |
| CInst_VOPC__V_CMPX_NLT_F16 | |
| CInst_VOPC__V_CMPX_NLT_F32 | |
| CInst_VOPC__V_CMPX_NLT_F64 | |
| CInst_VOPC__V_CMPX_O_F16 | |
| CInst_VOPC__V_CMPX_O_F32 | |
| CInst_VOPC__V_CMPX_O_F64 | |
| CInst_VOPC__V_CMPX_T_I16 | |
| CInst_VOPC__V_CMPX_T_I32 | |
| CInst_VOPC__V_CMPX_T_I64 | |
| CInst_VOPC__V_CMPX_T_U16 | |
| CInst_VOPC__V_CMPX_T_U32 | |
| CInst_VOPC__V_CMPX_T_U64 | |
| CInst_VOPC__V_CMPX_TRU_F16 | |
| CInst_VOPC__V_CMPX_TRU_F32 | |
| CInst_VOPC__V_CMPX_TRU_F64 | |
| CInst_VOPC__V_CMPX_U_F16 | |
| CInst_VOPC__V_CMPX_U_F32 | |
| CInst_VOPC__V_CMPX_U_F64 | |
| CInstFormat | |
| COperand | |
| COpTraits | Convenience traits so we can automatically infer the correct FP type without looking at the number of dwords (i.e., to determine if we need a float or a double when creating FP constants) |
| COpTraits< ScalarRegF64 > | |
| COpTraits< ScalarRegU64 > | |
| CPackedReg | |
| CPageFault | |
| CScalarOperand | |
| CStatusReg | |
| CVecOperand | |
| CVegaFault | |
| CVEGAGPUStaticInst | |
| ►CWalker | |
| CWalkerPort | |
| CWalkerSenderState | |
| CWalkerState | |
| ►NX86ISA | This is exposed globally, independent of the ISA |
| ►NACPI | |
| ►NMADT | |
| ►CIntSourceOverride | |
| CMem | |
| ►CIOAPIC | |
| CMem | |
| ►CLAPIC | |
| CMem | |
| ►CLAPICOverride | |
| CMem | |
| ►CMADT | |
| CMem | |
| ►CNMI | |
| CMem | |
| ►CRecord | |
| CMem | |
| CAllocator | |
| CLinearAllocator | |
| ►CRSDP | |
| CMem | |
| CMemR0 | |
| CRSDT | |
| CRXSDT | |
| ►CSysDescTable | |
| CMem | |
| CXSDT | |
| Nauxv | |
| Ncc_reg | |
| Ncondition_tests | |
| Nfloat_reg | |
| Nint_reg | |
| ►Nintelmp | |
| CAddrSpaceMapping | |
| CBaseConfigEntry | |
| CBus | |
| CBusHierarchy | |
| CCompatAddrSpaceMod | |
| CConfigTable | |
| CExtConfigEntry | |
| CFloatingPointer | |
| CIntAssignment | |
| CIOAPIC | |
| CIOIntAssignment | |
| CLocalIntAssignment | |
| CProcessor | |
| Nmisc_reg | |
| Nsegment_idx | |
| ►Nsmbios | |
| CBiosInformation | |
| CSMBiosStructure | |
| ►CSMBiosTable | |
| ►CSMBiosHeader | |
| CIntermediateHeader | |
| ►CAddrOp | |
| CArgType | |
| CAlignmentCheck | |
| CBareMetalWorkload | |
| CBoundRange | |
| CBreakpoint | |
| ►CCmos | |
| CX86RTC | |
| CCpuidResult | |
| CCrOp | |
| CCrRegIndex | |
| CCtrlRegIndex | |
| CDataHiOp | |
| CDataLowOp | |
| CDataOp | |
| CDbgOp | |
| CDbgRegIndex | |
| CDebugException | |
| CDecodeFaultInst | |
| ►CDecoder | |
| CInstBytes | |
| CDestOp | |
| CDeviceNotAvailable | |
| CDivideError | |
| CDoubleFault | |
| CE820Entry | |
| CE820Table | |
| CEmulEnv | |
| ►CEmuLinux | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| CExternalInterrupt | |
| CExtMachInst | |
| CFaultOp | |
| CFlatFloatRegClassOps | |
| CFlatIntRegClassOps | |
| CFloatOp | |
| CFloatRegClassOps | |
| CFoldedOp | |
| CFpOp | |
| CFpRegIndex | |
| CFsLinux | |
| CFsWorkload | |
| CGeneralProtection | |
| CGpRegIndex | Classes for register indices passed to instruction constructors |
| ►CGpuTLB | |
| CAccessInfo | This hash map will use the virtual page address as a key and will keep track of total number of accesses per page |
| CCpuSidePort | |
| CGpuTLBStats | |
| CMemSidePort | MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected |
| CTLBEvent | |
| CTranslation | |
| CHasDataSize | |
| CHasDataSize< T, decltype((void)&T::dataSize)> | |
| ►CI386Process | |
| CVSyscallPage | |
| CI8042 | |
| CI82094AA | |
| ►CI8237 | |
| ►CChannel | |
| CChannelAddrReg | |
| CChannelRemainingReg | |
| CWriteOnlyReg | |
| ►CI8254 | |
| CX86Intel8254Timer | |
| CI8259 | |
| CImm64Op | |
| CImm8Op | |
| CInitInterrupt | |
| CInstOperands | |
| CInterrupts | |
| CIntOp | |
| CIntRegClassOps | |
| ►CIntRequestPort | |
| COnCompletion | |
| CIntResponsePort | |
| CInvalidOpcode | |
| CInvalidTSS | |
| CISA | |
| CLdStFpOp | Base class for load ops using one FP register |
| CLdStOp | Base class for load ops using one integer register |
| CLdStSplitOp | Base class for load and store ops using two registers, we will call them split ops for this reason |
| CLongModePTE | |
| CMachineCheck | |
| CMacroopBase | |
| CMediaOpBase | |
| CMemNoDataOp | Base class for the tia microop which has no destination register |
| CMemOp | Base class for memory ops |
| CMicroCondBase | |
| CMicroDebug | |
| CMicroHalt | |
| CMiscOp | |
| CMMU | |
| CNonMaskableInterrupt | |
| COverflowTrap | |
| CPageFault | |
| CPCState | |
| CRegOpBase | |
| ►CRemoteGDB | |
| ►CAMD64GdbRegCache | |
| CGEM5_PACKED | |
| CX86GdbRegCache | |
| CSecurityException | |
| CSegDescriptorLimit | |
| CSegmentNotPresent | |
| CSegOp | |
| CSegRegIndex | |
| CSIMDFloatingPointFault | |
| CSpeaker | |
| CSrc1Op | |
| CSrc2Op | |
| CSrc3Op | |
| CStackFault | |
| CStackTrace | |
| CStartupInterrupt | |
| CSystemManagementInterrupt | |
| ►CTLB | |
| CTlbStats | |
| CTlbEntry | |
| CUnimpInstFault | |
| CUpcOp | |
| ►CWalker | |
| CWalkerPort | |
| CWalkerSenderState | |
| CWalkerState | |
| ►CX86_64Process | |
| CVSyscallPage | |
| CX86Abort | |
| CX86CPUID | |
| CX86Fault | |
| CX86FaultBase | |
| CX86Interrupt | |
| CX86MicroopBase | |
| CX86Process | |
| CX86StaticInst | Base class for all X86 static instructions |
| CX86Trap | |
| CX87FpExceptionPending | |
| ►NX86ISAInst | |
| CMicrocodeRom | |
| C__SchedulingPolicy | Intermediate class that derives from the i-face class, and implements its API |
| C_amd_queue_t | |
| C_hsa_agent_dispatch_packet_t | |
| C_hsa_barrier_and_packet_t | |
| C_hsa_barrier_or_packet_t | |
| C_hsa_dispatch_packet_t | |
| C_hsa_generic_vendor_pkt | |
| C_hsa_queue_t | |
| C_hsa_signal_t | |
| CA9SCU | |
| ►CAapcs32 | |
| CState | |
| ►CAapcs32Vfp | |
| CState | |
| ►CAapcs64 | |
| CState | |
| CAbstractNVM | This is an interface between the disk interface (which will handle the disk data transactions) and the timing model |
| CActivityRecorder | ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not |
| ►CAddressManager | |
| CAtomicStruct | |
| CLastWriter | |
| CAddressMonitor | |
| ►CAddrMapper | An address mapper changes the packet addresses in going from the response port side of the mapper to the request port side |
| CAddrMapperSenderState | |
| CMapperRequestPort | |
| CMapperResponsePort | |
| ►CAddrRange | Encapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc |
| CDummy | |
| CAddrRangeMap | The AddrRangeMap uses an STL map to implement an interval tree for address decoding |
| CAddrTypes | |
| CAmbaDevice | |
| CAmbaDmaDevice | |
| CAmbaFake | |
| CAmbaIntDevice | |
| CAmbaPioDevice | |
| Camd_event_t | |
| Camd_signal_s | |
| ►CAMDGPUDevice | Device model for an AMD GPU |
| CAddrRangeHasher | |
| CAMDGPUGfx | |
| CAMDGPUIHRegs | Struct to contain all interrupt handler related registers |
| CAMDGPUInterruptCookie | |
| ►CAMDGPUInterruptHandler | |
| CDmaEvent | |
| CSenderState | |
| ►CAMDGPUMemoryManager | |
| ►CGPUMemPort | |
| CSenderState | |
| CRequestStatus | |
| CAMDGPUNbio | |
| ►CAMDGPUSystemHub | This class handles reads from the system/host memory space from the shader |
| CAtomicResponseEvent | |
| CResponseEvent | |
| ►CAMDGPUVM | |
| CAGPTranslationGen | Translation range generators |
| CAMDGPUSysVMContext | |
| CGARTTranslationGen | |
| CGEM5_PACKED | |
| CMMHUBTranslationGen | |
| CUserTranslationGen | |
| ►CAMDMMIOReader | Helper class to read Linux kernel MMIO trace from amdgpu modprobes |
| CMmioTrace | |
| CAp2ScpDoorbell | |
| CApertureRegister | |
| CAQLRingBuffer | Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer |
| CArchTimer | Per-CPU architected timer |
| CArchTimerKvm | |
| ►CARMArchTLB | |
| CEntry | |
| CArmFreebsd | |
| ►CArmFreebsd32 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| ►CArmFreebsd64 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| CArmInterruptPin | Generic representation of an Arm interrupt pin |
| CArmInterruptPinGen | This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator |
| ►CArmKvmCPU | ARM implementation of a KVM-based hardware virtualized CPU |
| CKvmCoreMiscRegInfo | |
| CKvmIntRegInfo | |
| CArmLinux | |
| ►CArmLinux32 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| Ctimespec | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| ►CArmLinux64 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| Ctimespec | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| CArmLinuxProcess32 | A process with emulated Arm/Linux syscalls |
| CArmLinuxProcess64 | A process with emulated Arm/Linux syscalls |
| CArmPPI | |
| CArmPPIGen | Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of generating more than one interrupt (one per ContextID) |
| CArmProcess | |
| CArmProcess32 | |
| CArmProcess64 | |
| CArmRelease | |
| ►CArmSemihosting | Semihosting for AArch32 and AArch64 |
| ►CAbi32 | |
| CState | |
| ►CAbi64 | |
| CState | |
| CArmSigInterruptPin | |
| CArmSigInterruptPinGen | |
| CArmSPI | |
| CArmSPIGen | Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a pointer to it and returns it every time it is asked for it (via the get metod) |
| CArmSystem | |
| ►CArmV8KvmCPU | This is an implementation of a KVM-based ARMv8-compatible CPU |
| CIntRegInfo | Mapping between integer registers in gem5 and KVM |
| CMiscRegInfo | Mapping between misc registers in gem5 and registers in KVM |
| CAssociativeCache | |
| CAtagCmdline | |
| CAtagCore | |
| CAtagHeader | |
| CAtagMem | |
| CAtagNone | |
| CAtagRev | |
| CAtagSerial | |
| CAtomicGeneric2Op | |
| CAtomicGeneric3Op | |
| CAtomicGenericPair3Op | |
| CAtomicOpAdd | |
| CAtomicOpAnd | |
| CAtomicOpCAS | |
| CAtomicOpDec | |
| CAtomicOpExch | |
| CAtomicOpFunctor | |
| CAtomicOpInc | |
| CAtomicOpMax | |
| CAtomicOpMin | |
| CAtomicOpOr | |
| CAtomicOpSub | |
| CAtomicOpXor | |
| CAtomicRequestProtocol | |
| CAtomicResponseProtocol | |
| ►CAtomicSimpleCPU | |
| CAtomicCPUDPort | |
| CAtomicCPUPort | An AtomicCPUPort overrides the default behaviour of the recvAtomicSnoop and ignores the packet instead of panicking |
| CAtOp64 | |
| CBackdoorManager | This class manages the backdoors for RangeAddrMapper |
| CBadDevice | BadDevice This device just panics when accessed |
| CBarrier | |
| CBaseArmKvmCPU | |
| CBaseBufferArg | Base class for BufferArg and TypedBufferArg, Not intended to be used directly |
| ►CBaseCache | A basic cache interface |
| CCacheAccessorImpl | |
| CCacheCmdStats | |
| CCacheReqPacketQueue | Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also send requests based on the current MSHR status |
| CCacheRequestPort | A cache request port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks) |
| CCacheResponsePort | A cache response port is used for the CPU-side port of the cache, and it is basically a simple timing port that uses a transmit list for responses to the CPU (or connected requestor) |
| CCacheStats | |
| CCpuSidePort | The CPU-side port extends the base cache response port with access functions for functional, atomic and timing requests |
| CMemSidePort | The memory-side port extends the base cache request port with access functions for functional, atomic and timing snoops |
| ►CBaseCPU | |
| CBaseCPUStats | |
| CCommitCPUStats | |
| CExecuteCPUStats | |
| CFetchCPUStats | |
| CGlobalStats | Global CPU statistics that are merged into the Root object |
| CBaseGdbRegCache | Concrete subclasses of this abstract class represent how the register values are transmitted on the wire |
| CBaseGen | Base class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator |
| CBaseGic | |
| ►CBaseGlobalEvent | Common base class for GlobalEvent and GlobalSyncEvent |
| CBarrierEvent | The base class for the local events that will synchronize threads to perform the global event |
| CBaseGlobalEventTemplate | Funky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes |
| CBaseHTMCheckpoint | Transactional Memory checkpoint |
| CBaseInterrupts | |
| CBaseISA | |
| ►CBaseKvmCPU | Base class for KVM based CPU models |
| CKVMCpuPort | KVM memory port |
| CStatGroup | |
| CBaseKvmTimer | Timer functions to interrupt VM execution after a number of simulation ticks |
| ►CBaseMemProbe | Base class for memory system probes accepting Packet instances |
| CPacketListener | |
| ►CBaseMMU | |
| CMMUTranslationGen | |
| CTranslation | |
| ►CBasePixelPump | Timing generator for a pixel-based display |
| CPixelEvent | Callback helper class with suspend support |
| ►CBaseRemoteGDB | |
| ►CGdbCommand | |
| CContext | |
| ►CGdbMultiLetterCommand | |
| CContext | |
| ►CQuerySetCommand | |
| CContext | |
| CSocketEvent | |
| CTrapEvent | |
| ►CBaseSemihosting | Semihosting for AArch32, AArch64, RISCV-32 and RISCV-64: https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst |
| ►CAbiBase | |
| CStateBase | |
| CFile | |
| CFileBase | Internal state for open files |
| CFileFeatures | Implementation of the ':semihosting-features' magic file |
| CInPlaceArg | |
| CSemiCallBase | Semihosting call information structure |
| CBaseSetAssoc | A basic cache tag store |
| CBaseSimpleCPU | |
| CBaseStackTrace | |
| ►CBaseTags | A common base class of Cache tagstore objects |
| CBaseTagStats | TODO: It would be good if these stats were acquired after warmup |
| CBaseTLB | |
| ►CBaseTrafficGen | The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces |
| CStatGroup | |
| CTrafficGenPort | Request port specialisation for the traffic generator |
| ►CBaseXBar | The base crossbar contains the common elements of the non-coherent and coherent crossbar |
| CLayer | A layer is an internal crossbar arbitration point with its own flow control |
| CReqLayer | |
| CRespLayer | |
| CSnoopRespLayer | |
| CBasicPioDevice | |
| CBasicSignal | |
| CBitfieldROType | |
| CBitfieldType | |
| ►CBitfieldTypeImpl | |
| ►CTypeDeducer | |
| CT | |
| CT< void(C::*)(Type1 &, Type2)> | |
| CWrapper | |
| CBitfieldWOType | |
| ►CBmpWriter | |
| CBmpPixel32 | |
| CCompleteV1Header | |
| CFileHeader | |
| CInfoHeaderV1 | |
| CBreakPCEvent | |
| ►CBridge | A bridge is used to interface two different crossbars (or in general a memory-mapped requestor and responder), with buffering for requests and responses |
| CBridgeRequestPort | Port on the side that forwards requests and receives responses |
| CBridgeResponsePort | The port on the side that receives requests and sends responses |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CBTBSetAssociative | |
| ►CBTBTagType | |
| CKeyType | |
| CBufferArg | BufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call |
| CCache | A coherent cache that can be arranged in flexible topologies |
| CCacheAccessor | Provides generic cache lookup functions |
| CCacheAccessProbeArg | Information provided to probes on a cache event |
| ►CCacheBlk | A Basic Cache block |
| CLock | Represents that the indicated thread context has a "lock" on the block, in the LL/SC sense |
| CCacheBlkPrintWrapper | Simple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block |
| CCacheDataUpdateProbeArg | A data contents update is composed of the updated block's address, the old contents, and the new contents |
| CCacheEntry | A CacheEntry is an entry containing a tag |
| CCallbackQueue | |
| CChannelAddr | Class holding a guest address in a contiguous channel-local address space |
| CChannelAddrRange | The ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space |
| CCheck | |
| CChecker | Templated Checker class |
| CCheckerCPU | CheckerCPU class |
| CCheckerThreadContext | Derived ThreadContext class for use with the Checker |
| CCheckpointIn | |
| CCheckTable | |
| CChunkGenerator | This class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g |
| CCircleBuf | Circular buffer backed by a vector |
| ►CCircularQueue | Circular queue |
| Citerator | Iterator to the circular queue |
| ►CClint | NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf |
| CClintRegisters | MMIO Registers 0x0000 - 0x3FFF: msip (write-through to misc reg file) ...: reserved[0] 0x4000 - 0xBFF7: mtimecmp ...: reserved[1] 0xBFF8: mtime (read-only) |
| ►CClockDomain | The ClockDomain provides clock to group of clocked objects bundled under the same clock domain |
| CClockDomainStats | |
| CClocked | Helper class for objects that need to be clocked |
| CClockedObject | Extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object |
| CClockRateControlBwIf | |
| CClockRateControlDummyProtocolType | |
| CClockRateControlFwIf | |
| CClockRateControlInitiatorSocket | |
| CClockRateControlSlaveBase | |
| CClockRateControlTargetSocket | |
| ►CCoherentXBar | A coherent crossbar connects a number of (potentially) snooping requestors and responders, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses |
| CCoherentXBarRequestPort | Declaration of the coherent crossbar memory-side port type, one will be instantiated for each of the CPU-side-port interfaces connecting to the crossbar |
| CCoherentXBarResponsePort | Declaration of the coherent crossbar CPU-side port type, one will be instantiated for each of the mem_side_ports connecting to the crossbar |
| CSnoopRespPort | Internal class to bridge between an incoming snoop response from a CPU-side port and forwarding it through an outgoing CPU-side port |
| CCommandReg_t | |
| ►CCommMonitor | The communication monitor is a SimObject which can monitor statistics of the communication happening between two ports in the memory system |
| CCommMonitorSenderState | Sender state class for the monitor so that we can annotate packets with a transmit time and receive time |
| CMonitorRequestPort | This is the request port of the communication monitor |
| CMonitorResponsePort | This is the CPU-side port of the communication monitor |
| CMonitorStats | Stats declarations, all in a struct for convenience |
| CCompressedTags | A CompressedTags cache tag store |
| CCompressionBlk | A superblock is composed of sub-blocks, and each sub-block has information regarding its superblock and a pointer to its superblock tag |
| ►CComputeUnit | |
| CComputeUnitStats | |
| ►CDataPort | Data access Port |
| CSenderState | |
| CSystemHubEvent | |
| ►CDTLBPort | Data TLB port |
| CSenderState | SenderState is information carried along with the packet throughout the TLB hierarchy |
| CGMTokenPort | |
| ►CITLBPort | |
| CSenderState | SenderState is information carried along with the packet throughout the TLB hierarchy |
| ►CLDSPort | Port intended to communicate between the CU and its LDS |
| CSenderState | SenderState is information carried along with the packet, esp |
| ►CScalarDataPort | |
| CMemReqEvent | |
| CSenderState | |
| CSystemHubEvent | |
| ►CScalarDTLBPort | |
| CSenderState | |
| ►CSQCPort | |
| CMemReqEvent | |
| CSenderState | |
| ►CConfigCache | |
| CEntry | |
| CConstProxyPtr | |
| CContextDescriptor | |
| ►CCopyEngine | |
| CCopyEngineChannel | |
| CCopyEngineStats | |
| ►CCoroutine | This template defines a Coroutine wrapper type with a Boost-like interface |
| CCallerType | CallerType: A reference to an object of this class will be passed to the coroutine task |
| CEmpty | |
| CCountedExitEvent | |
| ►CCowDiskImage | Specialization for accessing a copy-on-write disk image layer |
| CSector | |
| CCpuCluster | |
| ►CCpuLocalTimer | |
| CTimer | |
| CCPUProgressEvent | |
| CCpuThread | |
| CCustomNoMaliGpu | |
| ►CCxxConfigDirectoryEntry | Config details entry for a SimObject |
| CParamDesc | |
| CPortDesc | Similar to ParamDesc to describe ports |
| CCxxConfigFileBase | Config file wrapper providing a common interface to CxxConfigManager |
| ►CCxxConfigManager | This class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++ |
| CException | Exception for instantiate/post-instantiate errors |
| CRenaming | Name substitution when instantiating any object whose name starts with fromPrefix |
| CSimObjectResolver | Class for resolving SimObject names to SimObjects usable by the checkpoint restore mechanism |
| ►CCxxConfigParams | Base for peer classes of SimObjectParams derived classes with parameter modifying member functions |
| CAddToConfigDir | |
| CCxxIniFile | CxxConfigManager interface for using .ini files |
| CCycles | Cycles is a wrapper class for representing cycle counts, i.e |
| CDataTranslation | This class represents part of a data address translation |
| CDebugBreakEvent | |
| CDebugStep | |
| CDecoderFaultInst | |
| CDerivedClockDomain | The derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain |
| CDescheduleDeleter | |
| CDeviceFDEntry | Holds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls) |
| CDirectedGenerator | |
| CDiskImage | Basic interface for accessing a disk image |
| CDisplay | |
| CDisplayTimings | |
| ►CDistEtherLink | Model for a fixed bandwidth full duplex ethernet link |
| CLink | Model base class for a single uni-directional link |
| CLocalIface | Interface to the local simulated system |
| CRxLink | Model for a receive link |
| CTxLink | Model for a send link |
| ►CDistHeaderPkt | |
| CHeader | |
| ►CDistIface | The interface class to talk to peer gem5 processes |
| ►CRecvScheduler | Class to encapsulate information about data packets received |
| CDesc | Received packet descriptor |
| CSync | This class implements global sync operations among gem5 peer processes |
| CSyncEvent | The global event to schedule periodic dist sync |
| CSyncNode | |
| CSyncSwitch | |
| CDmaCallback | DMA callback class |
| CDmaDevice | |
| ►CDmaPort | |
| CDmaReqState | |
| ►CDmaReadFifo | Buffered DMA engine helper class |
| CDmaDoneEvent | |
| CDmaThread | |
| ►CDmaVirtDevice | |
| CDmaVirtCallback | Wraps a std::function object in a DmaCallback |
| CDoorbell | Generic doorbell interface |
| CDoorbellInfo | |
| Cdp_regs | Ethernet device registers |
| Cdp_rom | |
| CDrainable | Interface for objects that might require draining before checkpointing |
| CDrainManager | |
| CDramGen | DRAM specific generator is for issuing request with variable page hit length and bank utilization |
| CDRAMPower | DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system |
| CDramRotGen | |
| CDueler | A dueler is an entry that may or may not be accounted for sampling |
| CDuelingMonitor | Duel between two sampled options to determine which is the winner |
| CDumbTOD | DumbTOD simply returns some idea of time when read |
| CDummyChecker | Specific non-templated derived class used for SimObject configuration |
| CDummyMatRegContainer | Dummy type aliases and constants for architectures that do not implement matrix registers |
| CDummyVecPredRegContainer | Dummy type aliases and constants for architectures that do not implement vector predicate registers |
| CDummyVecRegContainer | Dummy type aliases and constants for architectures that do not implement vector registers |
| ►CDVFSHandler | DVFS Handler class, maintains a list of all the domains it can handle |
| CUpdateEvent | Update performance level event, encapsulates all the required information for a future call to change a domain's performance level |
| CDynPoolManager | |
| CEmbeddedPyBind | |
| CEmbeddedPython | |
| CEmulatedDriver | EmulatedDriver is an abstract base class for fake SE-mode device drivers |
| ►CEmulationPageTable | |
| CEntry | |
| CPageTableTranslationGen | |
| CEnergyCtrl | |
| ►CEpisode | |
| CAction | |
| CEtherBus | |
| CEtherDevBase | Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy |
| ►CEtherDevice | |
| CEtherDeviceStats | |
| CEtherDump | |
| CEtherInt | |
| ►CEtherLink | |
| CInterface | |
| CLink | |
| ►CEtherSwitch | |
| ►CInterface | Model for an Ethernet switch port |
| ►CPortFifo | |
| CEntryOrder | |
| CPortFifoEntry | |
| CSwitchTableEntry | |
| CEtherTapBase | |
| CEtherTapInt | |
| CEtherTapStub | |
| CEthPacketData | |
| CEvent | |
| CEventBase | Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions |
| CEventFunctionWrapper | |
| CEventManager | |
| ►CEventQueue | Queue of events sorted in time order |
| CScopedMigration | |
| CScopedRelease | |
| CExecContext | The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model |
| ►CExecStage | |
| CExecStageStats | |
| CExitGen | The exit generator exits from the simulation once entered |
| CExtensible | |
| CExtension | This is the extension for carrying additional information |
| CExtensionBase | This is base of every extension |
| ►CExternalMaster | |
| CExternalPort | Derive from this class to create an external port interface |
| CHandler | |
| ►CExternalSlave | |
| CExternalPort | Derive from this class to create an external port interface |
| CHandler | |
| CFailUnimplemented | Static instruction class for unimplemented instructions that cause simulator termination |
| ►CFALRU | A fully associative LRU cache |
| CCacheTracking | Mechanism that allows us to simultaneously collect miss statistics for multiple caches |
| CPairHash | Hash table type mapping addresses to cache block pointers |
| CFALRUBlk | A fully associative cache block |
| CFaultBase | |
| CFDArray | |
| CFDEntry | Holds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode |
| ►CFetchStage | |
| CFetchStageStats | |
| ►CFetchUnit | |
| CFetchBufDesc | Fetch buffer descriptor |
| CSystemHubEvent | |
| CFiber | This class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution |
| CFifo | Simple FIFO implementation backed by a circular buffer |
| CFileFDEntry | Holds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk) |
| CFixedStreamGen | |
| CFlags | Wrapper that groups a few flag bits under the same undelying container |
| ►CFlashDevice | Flash Device model The Flash Device model is a timing model for a NAND flash device |
| CCallBackEntry | |
| CFlashDeviceStats | |
| CPageMapEntry | Every logical address maps to a physical block and a physical page |
| CFloat16 | |
| CFrameBuffer | Internal gem5 representation of a frame buffer |
| CFreeBSD | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface |
| CFUDesc | |
| CFunctionalRequestProtocol | |
| CFunctionalResponseProtocol | |
| CFunctionProfile | |
| CFuncUnit | |
| CFutexKey | FutexKey class defines an unique identifier for a particular futex in the system |
| CFutexMap | FutexMap class holds a map of all futexes used in the system |
| ►CFVPBasePwrCtrl | |
| CRegisters | |
| CFXSave | |
| ►CGarnetSyntheticTraffic | |
| CCpuPort | |
| CGarnetSyntheticTrafficSenderState | |
| CGEM5_PACKED | PM4 packets |
| CGenericAlignmentFault | |
| CGenericArmPciHost | |
| CGenericHtmFailureFault | |
| CGenericPageTableFault | |
| CGenericPciHost | Configurable generic PCI host interface |
| CGenericRiscvPciHost | |
| CGenericSatCounter | Implements an n bit saturating counter and provides methods to increment, decrement, and read it |
| CGenericSyscallABI | |
| ►CGenericSyscallABI32 | |
| CIsWide | |
| CIsWide< T, std::enable_if_t<(sizeof(T) > sizeof(UintPtr))> > | |
| CGenericSyscallABI64 | |
| ►CGenericTimer | |
| ►CCoreTimers | |
| CEventStream | |
| CGenericTimerFrame | |
| CGenericTimerISA | |
| CGenericTimerMem | |
| ►CGenericWatchdog | |
| CListener | System Counter Listener: This object is being notified any time there is a change in the SystemCounter |
| ►CGicV2 | |
| CBankedRegs | Registers "banked for each connected processor" per ARM IHI0048B |
| CGicv2m | |
| CGicv2mFrame | Ultimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m |
| CGicV2Registers | |
| CGicV2Types | |
| CGicv3 | |
| ►CGicv3CPUInterface | |
| Chppi_t | |
| CGicv3Distributor | |
| ►CGicv3Its | GICv3 ITS module |
| CDataPort | |
| CGicv3Redistributor | |
| CGicv3Registers | |
| CGicV3Types | |
| ►CGlobalEvent | The main global event class |
| CBarrierEvent | |
| CGlobalInstTracker | |
| ►CGlobalMemPipeline | |
| CGlobalMemPipelineStats | |
| CGlobals | Container for serializing global variables (not associated with any serialized object) |
| CGlobalSimLoopExitEvent | |
| ►CGlobalSyncEvent | A special global event that synchronizes all threads and forces them to process asynchronously enqueued events |
| CBarrierEvent | |
| CGoodbyeObject | |
| ►CGPUCommandProcessor | |
| CKernelDispatchData | |
| ►CGPUComputeDriver | |
| CDriverWakeupEvent | |
| CEventList | |
| CEventTableEntry | |
| ►CGPUDispatcher | |
| CGPUDispatcherStats | |
| CGPUDynInst | |
| CGPUExecContext | |
| CGPURenderDriver | |
| CGPUStaticInst | |
| CGpuTranslationState | GPU TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back |
| CGpuWavefront | |
| CGTestException | |
| ►CGTestLogOutput | |
| CEventHook | |
| CGTestTickHandler | |
| ►CGUPSGen | |
| CGenPort | Definition of the GenPort class which is of the type RequestPort |
| CGUPSGenStat | |
| CHardBreakpoint | |
| CHBFDEntry | Extends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags |
| ►CHDLcd | |
| CDmaEngine | |
| CHDLcdStats | |
| CPixelPump | |
| CHelloObject | |
| CHiFiveBase | |
| CHMCController | HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol |
| CHorizontalSlice | Provides a view of a horizontal slice of either a MatStore or a Tile |
| Chsa_packet_header_bitfield_t | |
| ►CHSAPacketProcessor | |
| Cdma_series_ctx | Calls getCurrentEntry once the queueEntry has been dmaRead |
| CQueueProcessEvent | |
| CRQLEntry | |
| CSignalState | |
| CHSAQueueDescriptor | |
| CHSAQueueEntry | |
| ►CHWScheduler | |
| CSchedulerWakeupEvent | |
| CHybridGen | Hybrid NVM + DRAM specific generator is for issuing request with variable buffer hit length and bank utilization |
| CI2CBus | |
| CI2CDevice | |
| ►CIdeController | Device model for an Intel PIIX4 IDE controller |
| ►CChannel | |
| CBMIRegs | Registers used for bus master interface |
| ►CIdeDisk | IDE Disk device model |
| CIdeDiskStats | |
| CIdleGen | The idle generator does nothing |
| CIdleStartEvent | |
| ►CIGbE | |
| CDescCache | |
| CRxDescCache | |
| CTxDescCache | |
| CIGbEInt | |
| CIllegalExecInst | This class is modelling instructions which are not going to be executed since they are flagged as Illegal Execution Instructions (PSTATE.IL = 1 or CPSR.IL = 1) |
| CImgWriter | |
| CImmOp | |
| CImmOp64 | |
| CIndexingPolicyTemplate | A common base class for indexing table locations |
| ►CIniFile | This class represents the contents of a ".ini" file |
| CEntry | A single key/value pair |
| CSection | A section |
| CInstDecoder | |
| CInstResult | |
| ►CIntel8254Timer | Programmable Interval Timer (Intel 8254) |
| ►CCounter | Counter element for PIT |
| CCounterEvent | Event for counter interrupt |
| CIntSinkPinBase | |
| CIntSourcePinBase | |
| CInvalidateGenerator | |
| ►CIob | |
| CIntBusy | |
| CIntCtl | |
| CIntMan | |
| ►CIPACache | |
| CEntry | |
| Cis_iterable | |
| Cis_iterable< T, std::void_t< decltype(begin(std::declval< T >())), decltype(end(std::declval< T >()))> > | |
| Cis_std_hash_enabled | |
| Cis_std_hash_enabled< T, std::void_t< decltype(std::hash< T >())> > | |
| Cis_vec_reg_container | |
| Cis_vec_reg_container< gem5::VecRegContainer< SIZE > > | |
| CIsaFake | IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites |
| CItsAction | |
| ►CItsCommand | An ItsCommand is created whenever there is a new command in the command queue |
| CCommandEntry | |
| CDispatchEntry | Dispatch entry is a metadata struct which contains information about the command (like the name) and the function object implementing the command |
| CItsProcess | ItsProcess is a base coroutine wrapper which is spawned by the Gicv3Its module when the latter needs to perform different actions, like translating a peripheral's MSI into an LPI (See derived ItsTranslation) or processing a Command from the ITS queue (ItsCommand) |
| CItsTranslation | An ItsTranslation is created whenever a peripheral writes a message in GITS_TRANSLATER (MSI) |
| CKernelLaunchStaticInst | |
| CKernelWorkload | |
| Ckfd_event_data | |
| Ckfd_hsa_hw_exception_data | |
| Ckfd_hsa_memory_exception_data | |
| Ckfd_ioctl_acquire_vm_args | |
| Ckfd_ioctl_alloc_memory_of_gpu_args | |
| Ckfd_ioctl_alloc_queue_gws_args | |
| Ckfd_ioctl_create_event_args | |
| Ckfd_ioctl_create_queue_args | |
| Ckfd_ioctl_dbg_address_watch_args | |
| Ckfd_ioctl_dbg_register_args | |
| Ckfd_ioctl_dbg_unregister_args | |
| Ckfd_ioctl_dbg_wave_control_args | |
| Ckfd_ioctl_destroy_event_args | |
| Ckfd_ioctl_destroy_queue_args | |
| Ckfd_ioctl_free_memory_of_gpu_args | |
| Ckfd_ioctl_get_clock_counters_args | |
| Ckfd_ioctl_get_dmabuf_info_args | |
| Ckfd_ioctl_get_process_apertures_args | |
| Ckfd_ioctl_get_process_apertures_new_args | |
| Ckfd_ioctl_get_queue_wave_state_args | |
| Ckfd_ioctl_get_tile_config_args | |
| Ckfd_ioctl_get_version_args | |
| Ckfd_ioctl_import_dmabuf_args | |
| Ckfd_ioctl_map_memory_to_gpu_args | |
| Ckfd_ioctl_reset_event_args | |
| Ckfd_ioctl_set_cu_mask_args | |
| Ckfd_ioctl_set_event_args | |
| Ckfd_ioctl_set_memory_policy_args | |
| Ckfd_ioctl_set_scratch_backing_va_args | |
| Ckfd_ioctl_set_trap_handler_args | |
| Ckfd_ioctl_smi_events_args | |
| Ckfd_ioctl_unmap_memory_from_gpu_args | |
| Ckfd_ioctl_update_queue_args | |
| Ckfd_ioctl_wait_events_args | |
| Ckfd_memory_exception_failure | |
| Ckfd_process_device_apertures | |
| CKvm | KVM parent interface |
| CKvmDevice | KVM device wrapper |
| CKvmFPReg | |
| CKvmKernelGic | KVM in-kernel GIC abstraction |
| CKvmKernelGicV2 | |
| CKvmKernelGicV3 | |
| ►CKvmVM | KVM VM container |
| CMemorySlot | Structures tracking memory slots |
| CMemSlot | |
| CLdsChunk | This represents a slice of the overall LDS, intended to be associated with an individual workgroup |
| ►CLdsState | |
| CCuSidePort | CuSidePort is the LDS Port closer to the CU side |
| CTickEvent | Event to allow event-driven execution |
| CLinearEquation | This class describes a linear equation with constant coefficients |
| CLinearGen | The linear generator generates sequential requests from a start to an end address, with a fixed block size |
| CLinearSystem | |
| ►CLinux | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface |
| Cfd_set | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | |
| Ctgt_iovec | |
| Ctgt_stat | Stat buffer |
| Ctgt_stat64 | |
| Ctimespec | For clock_gettime() |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| Cutsname | Interface struct for uname() |
| CListenSocket | |
| CListenSocketConfig | |
| CListenSocketInet | |
| CListenSocketUnix | |
| CListenSocketUnixAbstract | |
| CListenSocketUnixFile | |
| CLocalInstTracker | |
| ►CLocalMemPipeline | |
| CLocalMemPipelineStats | |
| CLocalSimLoopExitEvent | |
| ►CLogger | |
| CLoc | |
| CLooppointAnalysis | |
| CLooppointAnalysisManager | |
| CLupioBLK | LupioBLK: A virtual block device which aims to provide a disk-like interface for second-level storage |
| CLupioIPI | LupioIPI: An inter-processor interrupt virtual device |
| CLupioPIC | LupioPIC: A programmable interrupt controller virtual device that can manage input IRQs coming from up to 32 sources |
| CLupioRNG | LupioRNG: A Random Number Generator virtual device that returns either a random value, or a seed that can be configured by the user |
| CLupioRTC | LupioRTC: A Real-Time Clock Virtual Device that returns the current date and time in ISO 8601 format |
| CLupioSYS | LupioSYS: A Real-Time System Controller virtual device which provides a way for the software to halt or reboot the computer system |
| ►CLupioTMR | LupioTMR: A virtual timer device which provides a real time counter, as well as a configurable timer offering periodic and one shot modes |
| CLupioTimer | |
| CLupioTTY | LupioTTY: The LupioTTY is a virtual terminal device that can both transmit characters to a screen, as well as receive characters input from a keyboard |
| CLupV | The LupV collection consists of a RISC-V processor, as well as the set of LupiIO devices |
| CMalta | Top level class for Malta Chipset emulation |
| CMaltaCChip | Malta CChip CSR Emulation |
| ►CMaltaIO | Malta I/O device is a catch all for all the south bridge stuff we care to implement |
| CRTC | |
| CMasterPort | |
| ►CMathExpr | |
| CNode | |
| COpSearch | |
| CMathExprPowerModel | A Equation power model |
| CMatStore | Backing store for matrices |
| ►CMC146818 | Real-Time Clock (MC146818) |
| CRTCEvent | Event for RTC periodic interrupt |
| CRTCTickEvent | Event for RTC periodic interrupt |
| CMcrMrcImplDefined | This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable even for unimplemented registers |
| CMcrMrcMiscInst | Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access |
| CMcrrOp | |
| CMemBackdoor | |
| CMemBackdoorReq | |
| CMemberEventWrapper | Wrap a member function inside MemberEventWrapper to use it as an event callback |
| CMemberFunctionSignature | |
| CMemberFunctionSignature< R(C::*)(A...) const > | |
| CMemberFunctionSignature< R(C::*)(A...) const volatile > | |
| CMemberFunctionSignature< R(C::*)(A...) volatile > | |
| CMemberFunctionSignature< R(C::*)(A...)> | |
| ►CMemChecker | MemChecker |
| CByteTracker | The ByteTracker keeps track of transactions for the same byte – all outstanding reads, the completed reads (and what they observed) and write clusters (see WriteCluster) |
| CTransaction | Captures the lifetimes of read and write operations, and the values they consumed or produced respectively |
| CWriteCluster | Captures sets of writes where all writes are overlapping with at least one other write |
| ►CMemCheckerMonitor | Implements a MemChecker monitor, to be inserted between two ports |
| CMemCheckerMonitorSenderState | |
| CMonitorRequestPort | This is the request port of the communication monitor |
| CMonitorResponsePort | This is the response port of the communication monitor |
| ►CMemCmd | |
| CCommandInfo | Structure that defines attributes and other data associated with a Command |
| ►CMemDelay | This abstract component provides a mechanism to delay packets |
| CRequestPort | |
| CResponsePort | |
| ►CMemFootprintProbe | Probe to track footprint of accessed memory Two granularity of footprint measurement i.e |
| CMemFootprintProbeStats | |
| CMemoizer | This class takes a function as a constructor argument and memoizes it: every time the function gets invoked through the Memoizer object (see operator()), the result gets saved in the internal cache, ready to be retrieved next time an invokation is made with the same arguments |
| CMemPool | Class for handling allocation of physical pages in SE mode |
| CMemPools | |
| CMemState | This class holds the memory state for the Process class and all of its derived, architecture-specific children |
| ►CMemTest | Tests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes |
| CCpuPort | |
| CMemTestStats | |
| CMemTraceProbe | |
| CMHU | Message Handling Unit |
| CMhuDoorbell | |
| ►CMinorCPU | MinorCPU is an in-order CPU model with four fixed pipeline stages: |
| CMinorCPUPort | Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Execute |
| CMinorFU | A functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit) |
| CMinorFUPool | A collection of MinorFUs |
| CMinorFUTiming | Extra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction |
| CMinorOpClass | Boxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking |
| CMinorOpClassSet | Wrapper for a matchable set of op classes |
| ►CMipsLinux | |
| Ctgt_sysinfo | |
| CMipsProcess | |
| CMiscRegImmOp64 | |
| CMiscRegImplDefined64 | |
| CMiscRegOp64 | This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS |
| CMiscRegRegImmOp | |
| CMiscRegRegImmOp64 | |
| CMmDisk | |
| CMmioVirtIO | |
| CMonitorCallEvent | |
| CMrrcOp | |
| CMrsOp | |
| ►CMSHR | Miss Status and handling Register |
| CTarget | |
| CTargetList | |
| CMSHRQueue | A Class for maintaining a list of pending and allocated memory requests |
| CMsrBase | |
| CMsrImmOp | |
| CMsrRegOp | |
| CMultiLevelPageTable | |
| CMuxingKvmGic | |
| CNamed | Interface for things with names |
| CNoMaliGpu | |
| CNonCachingSimpleCPU | The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of just 'atomic' |
| CNoncoherentCache | A non-coherent cache |
| ►CNoncoherentXBar | A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides, and routes the request and response packets based on the address |
| CNoncoherentXBarRequestPort | Declaration of the crossbar memory-side port type, one will be instantiated for each of the CPU-side ports connecting to the crossbar |
| CNoncoherentXBarResponsePort | Declaration of the non-coherent crossbar CPU-side port type, one will be instantiated for each of the memory-side ports connecting to the crossbar |
| Cns_desc32 | |
| Cns_desc64 | |
| CNSGigE | NS DP83820 Ethernet device model |
| CNSGigEInt | |
| CNvmGen | NVM specific generator is for issuing request with variable buffer hit length and bank utilization |
| CObjectMatch | ObjectMatch contains a vector of expressions |
| COFSchedulingPolicy | |
| COpDesc | |
| COpenFlagTable | |
| COperandInfo | |
| ►COperatingSystem | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctimeval | For gettimeofday() |
| Cutsname | Interface struct for uname() |
| ►COutgoingRequestBridge | |
| COutgoingRequestPort | |
| COutputDirectory | Interface for creating files in a gem5 output directory |
| COutputFile | |
| COutputStream | |
| CP9MsgHeader | |
| CP9MsgInfo | |
| ►CPacket | A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache) |
| ►CPrintReqState | Object used to maintain state of a PrintReq |
| CLabelStackEntry | An entry in the label stack |
| CSenderState | A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet |
| CPacketFifo | |
| CPacketFifoEntry | |
| ►CPacketQueue | A packet queue is a class that holds deferred packets and later sends them using the associated CPU-side port or memory-side port |
| CDeferredPacket | A deferred packet, buffered to transmit later |
| CPanicPCEvent | |
| CParseParam | |
| CParseParam< BitUnionType< T > > | |
| CParseParam< bool > | |
| CParseParam< DummyMatRegContainer > | |
| CParseParam< DummyVecPredRegContainer > | |
| CParseParam< DummyVecRegContainer > | |
| CParseParam< MatStore< X, Y > > | Calls required for serialization/deserialization |
| CParseParam< std::string > | |
| CParseParam< T, decltype(to_number("", std::declval< T & >()), void())> | |
| CParseParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > > | |
| CParseParam< VecPredRegContainer< NumBits, Packed > > | |
| CParseParam< VecRegContainer< Sz > > | Calls required for serialization/deserialization |
| CPc | |
| Cpcap_file_header | |
| Cpcap_pkthdr | |
| ►CPcCountPair | |
| CHashFunction | Enable hashing for this parameter |
| CPcCountTracker | |
| CPcCountTrackerManager | |
| CPCEvent | |
| ►CPCEventQueue | |
| CMapCompare | |
| CPCEventScope | |
| CPciBar | |
| CPciBarNone | |
| CPciBusAddr | |
| CPciDevice | PCI device, base implementation is only config space |
| ►CPciHost | The PCI host describes the interface between PCI devices and a simulated system |
| CDeviceInterface | Callback interface from PCI devices to the host |
| CPciIoBar | |
| CPciLegacyIoBar | |
| CPciMemBar | |
| CPciMemUpperBar | |
| CPciVirtIO | |
| CPCStateBase | |
| CPerfKvmCounter | An instance of a performance counter |
| CPerfKvmCounterConfig | PerfEvent counter configuration |
| CPerfKvmTimer | PerfEvent based timer using the host's CPU cycle counter |
| CPhysRegId | Physical register ID |
| CPioDevice | This device is the base class which all devices senstive to an address range inherit from |
| CPioPort | The PioPort class is a programmed i/o port that all devices that are sensitive to an address range use |
| CPipeFDEntry | Holds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants |
| CPipeStageIFace | |
| CPixel | Internal gem5 representation of a Pixel |
| ►CPixelConverter | Configurable RGB pixel converter |
| CChannel | Color channel conversion and scaling helper class |
| CPl011 | |
| CPL031 | |
| CPl050 | |
| CPl111 | |
| CPlatform | |
| ►CPlic | |
| CPlicRegisters | MMIO Registers |
| CPlicBase | |
| CPlicIntDevice | |
| CPlicOutput | NOTE: This implementation of PLIC is based on he riscv-plic-spec repository: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0 |
| CPM4PacketProcessor | |
| CPM4Queue | Class defining a PM4 queue |
| ►CPngWriter | Image writer implementing support for PNG |
| CPngPixel24 | Png Pixel type: not containing padding |
| CPngStructHandle | |
| CPollEvent | |
| CPollQueue | |
| CPoolManager | |
| ►CPort | Ports are used to interface objects to each other |
| CUnboundPortException | |
| CPortProxy | This object is a proxy for a port or other object which implements the functional response protocol, to be used for debug accesses |
| ►CPortTerminator | |
| CReqPort | Definition of the ReqPort class |
| CRespPort | Definition of the RespPort class |
| CPosixKvmTimer | Timer based on standard POSIX timers |
| ►CPowerDomain | The PowerDomain groups PowerState objects together to regulate their power states |
| CPowerDomainStats | |
| ►CPowerLinux | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctms | For times() |
| ►CPowerModel | |
| CThermalProbeListener | Listener class to catch thermal events |
| CPowerModelState | A PowerModelState is an abstract class used as interface to get power figures out of SimObjects |
| CPowerProcess | |
| ►CPowerState | Helper class for objects that have power states |
| CPowerStateStats | |
| CPrdEntry_t | |
| CPrdTableEntry | |
| CPrimaryQueue | |
| CPrintable | Abstract base class for objects which support being printed to a stream for debugging |
| CProbeListener | ProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener |
| CProbeListenerArg | ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call |
| CProbeListenerArgBase | ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type) |
| CProbeListenerArgFunc | ProbeListenerArgFunc generates a listener for the class of Arg and a lambda callback function that is called by the notify |
| CProbeListenerObject | This class is a minimal wrapper around SimObject |
| CProbeManager | ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points |
| CProbePoint | ProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint |
| CProbePointArg | ProbePointArg generates a point for the class of Arg |
| ►CProcess | |
| CLoader | Each instance of a Loader subclass will have a chance to try to load an object file when tryLoaders is called |
| CProfileNode | |
| ►CProtocolTester | |
| CGMTokenPort | |
| CSenderState | |
| CSeqPort | |
| CProxyPtr | |
| CProxyPtr< void, Proxy > | |
| CProxyPtrBuffer | |
| CPybindModuleInit | |
| CPybindSimObjectResolver | Resolve a SimObject name using the Pybind configuration |
| CPyEvent | PyBind wrapper for Events |
| CPyTrafficGen | |
| CQCntxt | |
| CQueue | A high-level queue interface, to be used by both the MSHR queue and the write buffer |
| CQueuedRequestPort | The QueuedRequestPort combines two queues, a request queue and a snoop response queue, that both share the same port |
| CQueuedResponsePort | A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port |
| ►CQueueEntry | A queue entry base class, to be used by both the MSHRs and write-queue entries |
| CTarget | A queue entry is holding packets that will be serviced as soon as resources are available |
| CRandom | |
| CRandomGen | The random generator is similar to the linear one, but does not generate sequential addresses |
| CRandomStreamGen | |
| CRandomTest | Helper class to access private members of Random |
| CRangeAddrMapper | Range address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset |
| CRawDiskImage | Specialization for accessing a raw disk image |
| CRealView | |
| ►CRealViewCtrl | |
| CDevice | |
| CRealViewOsc | This is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface |
| CRealViewTemperatureSensor | This device implements the temperature sensor used in the RealView/Versatile Express platform |
| CRedirectPath | RedirectPath stores a mapping from one 'appPath' to a vector of 'hostPath' |
| CReExec | |
| CRefCounted | Derive from RefCounted if you want to enable reference counting of this class |
| CRefCountingPtr | If you want a reference counting pointer to a mutable object, create it like this: |
| CRegClass | |
| CRegClassIterator | |
| CRegClassOps | |
| CRegFile | |
| CRegId | Register ID: describe an architectural register with its class and index |
| CRegImmImmOp | |
| CRegImmImmOp64 | |
| CRegImmOp | |
| CRegImmRegOp | |
| CRegImmRegShiftOp | |
| ►CRegisterBank | |
| CRegister | |
| CRegisterAdder | |
| CRegisterBase | |
| CRegisterBuf | |
| CRegisterLBuf | |
| CRegisterRao | |
| CRegisterRaz | |
| CRegisterRoFill | |
| ►CRegisterBankBase | |
| CRegisterBaseBase | |
| ►CRegisterFile | |
| CMarkRegBusyScbEvent | |
| CMarkRegFreeScbEvent | |
| CRegisterEvent | |
| CRegisterFileStats | |
| ►CRegisterFileCache | |
| CMarkRegCachedEvent | |
| COrderedRegs | |
| CRegisterCacheEvent | |
| CRegisterManager | |
| CRegisterManagerPolicy | Register Manager Policy abstract class |
| CRegisterOperandInfo | |
| CRegMiscRegImmOp | |
| CRegMiscRegImmOp64 | |
| CRegNone | |
| CRegOp | |
| CRegOp64 | |
| CRegRegImmImmOp | |
| CRegRegImmImmOp64 | |
| CRegRegImmOp | |
| CRegRegOp | |
| CRegRegRegImmOp | |
| CRegRegRegImmOp64 | |
| CRegRegRegOp | |
| CRegRegRegRegOp | |
| CReplaceableEntry | A replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality |
| CReqPacketQueue | |
| CRequest | |
| CRequestorInfo | Data about a specific requestor |
| CRequestPort | A RequestPort is a specialisation of a Port, which implements the default protocol for the three different level of transport functions |
| CRequestPortWrapper | The RequestPortWrapper converts inherit-based RequestPort into callback-based |
| CResponsePort | A ResponsePort is a specialization of a port |
| CResponsePortWrapper | The ResponsePortWrapper converts inherit-based ResponsePort into callback-based |
| CRespPacketQueue | |
| ►CRiscvLinux | |
| Ccpumask | |
| Criscv_hwprobe | |
| ►CRiscvLinux32 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Ctgt_fsid_t | |
| Ctgt_stat | |
| Ctgt_statfs | |
| Ctgt_sysinfo | |
| Ctimespec | |
| ►CRiscvLinux64 | |
| Ctgt_clone_args | |
| Ctgt_fsid_t | |
| Ctgt_stat64 | |
| Ctgt_statfs | |
| Ctgt_sysinfo | |
| Ctimespec | |
| CRiscvProcess | |
| CRiscvProcess32 | |
| CRiscvProcess64 | |
| ►CRiscvRTC | NOTE: This is a generic wrapper around the MC146818 RTC |
| CRTC | |
| ►CRiscvSemihosting | Semihosting for RV32 and RV64 |
| CAbi32 | |
| CAbi64 | |
| ►CRiscvSemihostingAbi | |
| CState | |
| ►CRoot | |
| CRootStats | |
| CRRSchedulingPolicy | |
| ►CRubyDirectedTester | |
| CCpuPort | |
| ►CRubyTester | |
| CCpuPort | |
| CSenderState | |
| CScalarMemPipeline | |
| CScalarRegisterFile | |
| ►CScalarStatTester | |
| CScalarStatTesterStats | |
| CScheduler | |
| ►CScheduleStage | |
| CScheduleStageStats | |
| CScheduleToExecute | Communication interface between Schedule and Execute stages |
| CSchedulingPolicy | Interface class for the wave scheduling policy |
| ►CScoreboardCheckStage | |
| CScoreboardCheckStageStats | |
| CScoreboardCheckToSchedule | Communication interface between ScoreboardCheck and Schedule stages |
| CScp | |
| CScp2ApDoorbell | |
| ►CSDMAEngine | System DMA Engine class for AMD dGPU |
| CSDMAQueue | |
| CSectorBlk | A Basic Sector block |
| CSectorSubBlk | A sector is composed of sub-blocks, and each sub-block has information regarding its sector and a pointer to its sector tag |
| ►CSectorTags | A SectorTags cache tag store |
| CSectorTagsStats | |
| ►CSemiPseudoAbi32 | |
| CState | |
| ►CSemiPseudoAbi64 | |
| CState | |
| CSerialDevice | Base class for serial devices such as terminals |
| ►CSerializable | Basic support for object serialization |
| CScopedCheckpointSection | |
| CSerializationFixture | Fixture class that handles temporary directory creation |
| ►CSerialLink | SerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CSerialLinkRequestPort | Port on the side that forwards requests and receives responses |
| CSerialLinkResponsePort | The port on the side that receives requests and sends responses |
| CSerialNullDevice | Dummy serial device that discards all data sent to it |
| CSeriesRequestGenerator | |
| CSESyscallFault | |
| CSetAssociative | A set associative indexing policy |
| CSETranslatingPortProxy | |
| CSEWorkload | |
| ►CShader | |
| CShaderStats | |
| CShowParam | |
| CShowParam< BitUnionType< T > > | |
| CShowParam< bool > | |
| CShowParam< MatStore< X, Y > > | |
| CShowParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > > | |
| CShowParam< T, std::enable_if_t< std::is_same_v< char, T >||std::is_same_v< unsigned char, T >||std::is_same_v< signed char, T > > > | |
| CShowParam< VecPredRegContainer< NumBits, Packed > > | |
| CShowParam< VecRegContainer< Sz > > | |
| CSignalInterruptBwIf | |
| CSignalInterruptDummyProtocolType | |
| CSignalInterruptFwIf | |
| CSignalInterruptInitiatorSocket | |
| CSignalInterruptSlaveBase | |
| CSignalInterruptTargetSocket | |
| CSignalSinkPort | |
| CSignalSourcePort | |
| CSimObject | Abstract superclass for simulation objects |
| CSimObjectResolver | Base class to wrap object resolving functionality |
| ►CSimpleCache | A very simple cache object |
| CCPUSidePort | Port on the CPU-side that receives requests |
| CMemSidePort | Port on the memory-side that receives responses |
| CSimpleCacheStats | Cache statistics |
| CSimpleDisk | |
| ►CSimpleExecContext | |
| CExecContextStats | |
| CSimpleMemDelay | Delay packets by a constant time |
| ►CSimpleMemobj | A very simple memory object |
| CCPUSidePort | Port on the CPU-side that receives requests |
| CMemSidePort | Port on the memory-side that receives responses |
| CSimpleObject | |
| CSimplePoolManager | |
| CSimpleThread | The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface |
| CSimpleTimingPort | The simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic |
| CSimpleUart | |
| ►CSimPoint | |
| CBBInfo | Basic Block information |
| CSimulatorThreads | |
| CSkewedAssociative | A skewed associative indexing policy |
| CSkipFuncBase | |
| CSlavePort | |
| CSMMUAction | |
| CSMMUATSDevicePort | |
| CSMMUATSMemoryPort | |
| CSMMUCommand | |
| CSMMUCommandExecProcess | |
| CSMMUControlPort | |
| CSMMUDevicePort | |
| CSMMUDeviceRetryEvent | |
| ►CSMMUEvent | |
| CData | |
| CSMMUProcess | |
| CSMMURequestPort | |
| CSMMUSemaphore | |
| CSMMUSignal | |
| CSMMUTableWalkPort | |
| ►CSMMUTLB | |
| CEntry | |
| ►CSMMUTranslationProcess | |
| CFault | |
| CTranslContext | |
| CTranslResult | |
| CSMMUTranslRequest | |
| ►CSMMUv3 | |
| CSMMUv3Stats | |
| ►CSMMUv3BaseCache | |
| CSMMUv3BaseCacheStats | |
| CSMMUv3DeviceInterface | |
| CSNHash | |
| ►CSnoopFilter | This snoop filter keeps track of which connected port has a particular line of data |
| CReqLookupResult | A request lookup must be followed by a call to finishRequest to inform the operation's success |
| CSnoopFilterStats | Statistics |
| CSnoopItem | Per cache line item tracking a bitmask of ResponsePorts who have an outstanding request to this line (requested) or already share a cache line with this address (holder) |
| CSnoopRespPacketQueue | |
| CSocketFDEntry | |
| ►CSolaris | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface |
| Ctgt_stat | Stat buffer |
| Ctgt_stat64 | |
| Ctgt_timespec | |
| Cutsname | Interface struct for uname() |
| CSouthBridge | |
| ►CSp804 | |
| CTimer | |
| CSp805 | |
| ►CSparc32Linux | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| CSparc32Process | |
| CSparc64Process | |
| ►CSparcLinux | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| CSparcProcess | |
| CSparcPseudoInstABI | |
| CSparcSolaris | |
| ►CSparseHistStatTester | |
| CSparseHistStatTesterStats | |
| CSpatterAccess | |
| ►CSpatterGen | Spatter Kernel Player |
| CSpatterGenEvent | |
| CSpatterGenPort | |
| CSpatterGenStats | |
| ►CSpatterKernel | |
| CIndexGen | |
| CSrcClockDomain | The source clock domains provides the notion of a clock domain that is connected to a tunable clock source |
| CSSTResponderInterface | |
| ►CStackDistCalc | The stack distance calculator is a passive object that merely observes the addresses pass to it |
| CNode | Node which takes form of Leaf, INode or Root |
| ►CStackDistProbe | |
| CStackDistProbeStats | |
| CStaticInst | Base, ISA-independent static instruction class |
| CStaticRegisterManagerPolicy | |
| CStatTester | This classes are used to test the stats system from setting through to output |
| CStochasticGen | |
| CStreamGen | |
| CStreamTableEntry | |
| CStridedGen | The strided generator generates sequential requests from a start to an end address, with a fixed block size |
| CStringWrap | |
| CStubSlavePort | Implement a ‘stub’ port which just responds to requests by printing a message |
| CStubSlavePortHandler | |
| CStubWorkload | |
| CSubSystem | The SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system |
| CSuperBlk | A basic compression superblock |
| ►CSysBridge | Each System object in gem5 is responsible for a set of RequestorIDs which identify different sources for memory requests within that System |
| CBridgingPort | |
| CPacketData | |
| CSysBridgeSenderState | |
| CSysBridgeSourcePort | |
| CSysBridgeTargetPort | |
| CSyscallDesc | This class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e |
| CSyscallDescABI | |
| CSyscallDescTable | |
| CSyscallRetryFault | |
| CSyscallReturn | This class represents the return value from an emulated system call, including any errno setting |
| CSysSecCtrl | System Security Control registers |
| ►CSystem | |
| CSystemPort | Private class for the system port which is only used as a requestor for debug access and for non-structural entities that do not have a port of their own |
| ►CThreads | |
| Cconst_iterator | |
| CThread | |
| CSystemCounter | Global system counter |
| CSystemCounterListener | Abstract class for elements whose events depend on the counting speed of the System Counter |
| CT1000 | |
| CTaggedEntry | A tagged entry is an entry containing a tag |
| CTaggedSetAssociative | This version of set associative indexing deals with a Lookup structure made of address and secure bit |
| ►CTaggedTypes | |
| CKeyType | |
| CTapEvent | |
| ►CTapListener | |
| CEvent | |
| ►CTCPIface | |
| CNodeInfo | Compute node info and storage for the very first connection from each node (used by the switch) |
| CTempCacheBlk | Special instance of CacheBlk for use with tempBlk that deals with its block address regeneration |
| CTemperature | The class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius |
| ►CTerminal | |
| CDataEvent | |
| CListenEvent | |
| CTesterDma | |
| ►CTesterThread | |
| CDeadlockCheckEvent | |
| COutstandingReq | |
| CTesterThreadEvent | |
| CThermalCapacitor | A ThermalCapacitor is used to model a thermal capacitance between two thermal domains |
| CThermalDomain | A ThermalDomain is used to group objects under that operate under the same temperature |
| CThermalEntity | An abstract class that represents any thermal entity which is used in the circuital thermal equivalent model |
| CThermalModel | |
| CThermalNode | A ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains |
| CThermalReference | A ThermalReference is a thermal domain with fixed temperature |
| CThermalResistor | A ThermalResistor is used to model a thermal resistance between two thermal domains |
| ►CThreadBridge | |
| CIncomingPort | |
| COutgoingPort | |
| CThreadContext | ThreadContext is the external interface to all thread state for anything outside of the CPU |
| ►CThreadState | Struct for holding general thread state that is needed across CPU models |
| CThreadStateStats | |
| CTicked | Ticked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking |
| CTickedObject | TickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation |
| CTile | Provides a view of a matrix that is row-interleaved onto a MatStore |
| CTime | |
| ►CTimeBuffer | |
| Cwire | |
| CTimedQueue | |
| CTimingExpr | |
| CTimingExprBin | |
| CTimingExprEvalContext | Object to gather the visible context for evaluation |
| CTimingExprIf | |
| CTimingExprLet | |
| CTimingExprLiteral | |
| CTimingExprRef | |
| CTimingExprSrcReg | |
| CTimingExprUn | |
| CTimingRequestProtocol | |
| CTimingResponseProtocol | |
| ►CTimingSimpleCPU | |
| ►CDcachePort | |
| CDTickEvent | |
| CFetchTranslation | |
| ►CIcachePort | |
| CITickEvent | |
| CIprEvent | |
| CSplitFragmentSenderState | |
| CSplitMainSenderState | |
| ►CTimingCPUPort | A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle |
| CTickEvent | |
| ►CTLBCoalescer | The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB |
| CCpuSidePort | |
| CMemSidePort | |
| CTLBCoalescerStats | |
| CTlbiOp | |
| CTlbiOp64 | |
| CTokenManager | |
| CTokenRequestPort | |
| CTokenResponsePort | |
| ►CTraceCPU | The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model |
| CDcachePort | DcachePort class that interfaces with L1 Data Cache |
| ►CElasticDataGen | The elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies |
| CElasticDataGenStatGroup | |
| CGraphNode | The struct GraphNode stores an instruction in the trace file |
| CHardwareResource | Models structures that hold the in-flight nodes |
| CInputStream | The InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on the input |
| CReadyNode | Struct to store a ready-to-execute node and its execution tick |
| ►CFixedRetryGen | Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests |
| CFixedRetryGenStatGroup | |
| CInputStream | The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input |
| CTraceElement | This struct stores a line in the trace file |
| CIcachePort | IcachePort class that interfaces with L1 Instruction Cache |
| CTraceStats | |
| ►CTraceGen | The trace replay generator reads a trace file and plays back the transactions |
| CInputStream | The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input |
| CTraceElement | This struct stores a line in the trace file |
| CTracingExtension | TracingExtension is an Extension of the Packet for recording the trace of the Packet |
| ►CTrafficGen | The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple behaviours that are either probabilistic or based on traces |
| CTransition | Struct to represent a probabilistic transition during parsing |
| CTranslatingPortProxy | This proxy attempts to translate virtual addresses using the TLBs |
| ►CTranslationGen | TranslationGen is a base class for a generator object which returns information about address translations over a range of virtual addresses |
| CRange | This structure represents a single, contiguous translation, or carries information about whatever fault might have happened while attempting it |
| CTranslationGenConstIterator | An iterator for pulling "Range" instances out of a TranslationGen |
| ►CTrie | A trie is a tree-based data structure used for data retrieval |
| CNode | |
| CTypedAtomicOpFunctor | |
| CTypedBufferArg | TypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call |
| CTypedRegClassOps | |
| CUart | |
| ►CUart8250 | |
| ►CRegisters | |
| CBankedRegister | |
| CPairedRegister | |
| CRWSwitchedRegister | |
| ►CUFSHostDevice | Host controller layer: This is your Host controller This layer handles the UFS functionality |
| CHCIMem | Host Controller Interface This is a set of registers that allow the driver to control the transactions to the flash devices |
| CLUNInfo | Logic unit information structure |
| CSCSIReply | SCSI reply structure |
| CSCSIResumeInfo | After a SCSI command has been identified, the SCSI resume function will handle it |
| CtaskStart | Task start information |
| CtransferDoneInfo | Transfer completion info |
| CtransferInfo | Different events, and scenarios require different types of information |
| CtransferStart | Transfer start information |
| CUFSHCDSGEntry | Struct UFSHCDSGEntry - UFSHCI PRD Entry baseAddr: Lower 32bit physical address DW-0 upperAddr: Upper 32bit physical address DW-1 reserved: Reserved for future use DW-2 size: size of physical segment DW-3 |
| CUFSHostDeviceStats | Statistics |
| CUFSSCSIDevice | Device layer: This is your Logic unit This layer implements the SCSI functionality of the UFS Device One logic unit controls one or more disk partitions |
| CUPIUMessage | UPIU tranfer message |
| CUTPTransferCMDDesc | Struct UTPTransferCMDDesc - UFS Commad Descriptor structure commandUPIU: Command UPIU Frame address responseUPIU: Response UPIU Frame address PRDTable: Physcial Region Descriptor All lengths as defined by JEDEC220 |
| ►CUTPTransferReqDesc | Struct UTPTransferReqDesc - UTRD structure header: UTRD header DW-0 to DW-3 commandDescBaseAddrLo: UCD base address low DW-4 commandDescBaseAddrHi: UCD base address high DW-5 responseUPIULength: response UPIU length DW-6 responseUPIUOffset: response UPIU offset DW-6 PRDTableLength: Physical region descriptor length DW-7 PRDTableOffset: Physical region descriptor offset DW-7 |
| CRequestDescHeader | Struct RequestDescHeader dword0: Descriptor Header DW0 dword1: Descriptor Header DW1 dword2: Descriptor Header DW2 dword3: Descriptor Header DW3 |
| CUTPUPIUHeader | All the data structures are defined in the UFS standard This standard be found at the JEDEC website free of charge (login required): http://www.jedec.org/standards-documents/results/jesd220 |
| CUTPUPIURSP | Struct UTPUPIURSP - Response UPIU structure header: UPIU header DW-0 to DW-2 residualTransferCount: Residual transfer count DW-3 reserved: Reserved DW-4 to DW-7 senseDataLen: Sense data length DW-8 U16 senseData: Sense data field DW-8 to DW-12 |
| CUTPUPIUTaskReq | Struct UTPUPIUTaskReq - Task request UPIU structure header - UPIU header structure DW0 to DW-2 inputParam1: Input param 1 DW-3 inputParam2: Input param 2 DW-4 inputParam3: Input param 3 DW-5 reserved: Reserver DW-6 to DW-7 |
| CwriteToDiskBurst | Disk transfer burst information |
| CUncontendedMutex | |
| CUnimpFault | |
| CUnknownOp | |
| CUnknownOp64 | |
| CVecElemRegClassOps | |
| CVecPredRegContainer | Generic predicate register container |
| CVecPredRegT | Predicate register view |
| CVecRegContainer | Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers |
| ►CVector2dStatTester | |
| CVector2dStatTesterStats | |
| CVectorRegisterFile | |
| ►CVectorStatTester | |
| CVectorStatTesterStats | |
| ►CVegaTLBCoalescer | The VegaTLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB |
| CCpuSidePort | |
| CMemSidePort | |
| CVerticalSlice | Provides a view of a vertical slice of either a MatStore or a Tile |
| CVGic | |
| CVirtDescriptor | VirtIO descriptor (chain) wrapper |
| ►CVirtIO9PBase | This class implements a VirtIO transport layer for the 9p network file system |
| CConfig | VirtIO 9p configuration structure |
| CFSQueue | Virtqueue for 9p requests |
| ►CVirtIO9PDiod | VirtIO 9p proxy that communicates with the diod 9p server using pipes |
| CDiodDataEvent | |
| CVirtIO9PProxy | VirtIO 9p proxy base class |
| ►CVirtIO9PSocket | VirtIO 9p proxy that communicates with a 9p server over tcp sockets |
| CSocketDataEvent | |
| ►CVirtIOBlock | VirtIO block device |
| CBlkRequest | VirtIO block device request as sent by guest |
| CConfig | Block device configuration structure |
| CRequestQueue | Virtqueue for disk requests |
| ►CVirtIOConsole | VirtIO console |
| CConfig | Console configuration structure |
| CTermRecvQueue | Virtqueue for data going from the host to the guest |
| CTermTransQueue | Virtqueue for data going from the guest to the host |
| CVirtIODeviceBase | Base class for all VirtIO-based devices |
| CVirtIODummyDevice | |
| ►CVirtIORng | VirtIO Rng |
| CRngQueue | Virtqueue for data going from the host to the guest |
| ►CVirtQueue | Base wrapper around a virtqueue |
| ►CVirtRing | VirtIO ring buffer wrapper |
| CHeader | |
| ►CVMA | |
| CMappedFileBuffer | MappedFileBuffer is a wrapper around a region of host memory backed by a file |
| ►CVncInput | |
| CClientCutTextMessage | |
| CFrameBufferUpdateReq | |
| CKeyEventMessage | |
| CPixelEncodingsMessage | |
| CPixelFormat | |
| CPixelFormatMessage | |
| CPointerEventMessage | |
| CVncKeyboard | A device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server |
| CVncMouse | |
| ►CVncServer | |
| CDataEvent | DataEvent to read data from vnc |
| CFrameBufferRect | |
| CFrameBufferUpdate | |
| CListenEvent | ListenEvent to accept a vnc client connection |
| CServerCutText | |
| CServerInitMsg | |
| ►CVoltageDomain | A VoltageDomain is used to group clock domains that operate under the same voltage |
| CVoltageDomainStats | |
| CWaitClass | |
| CWaiterState | WaiterState defines internal state of a waiter thread |
| ►CWalkCache | |
| CEntry | |
| CWalkCacheStats | |
| CWarnUnimplemented | Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation) |
| ►CWavefront | |
| CWavefrontStats | |
| CWFBarrier | WF barrier slots |
| CWholeTranslationState | This class captures the state of an address translation |
| ►CWorkload | |
| ►CWorkloadStats | |
| CInstStats | |
| CWriteAllocator | The write allocator inspects write packets and detects streaming patterns |
| CWriteQueue | A write queue for all eviction packets, i.e |
| ►CWriteQueueEntry | Write queue entry |
| CTargetList | |
| CX86IdeController | |
| CX86KvmCPU | X86 implementation of a KVM-based hardware virtualized CPU |
| ►CX86Linux | |
| CSyscallABI | |
| ►CX86Linux32 | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| ►CX86Linux64 | |
| Ctgt_clone_args | |
| Ctgt_fsid | |
| Ctgt_iovec | |
| Ctgt_stat64 | |
| Ctgt_statfs | |
| Ctgt_statx | |
| Ctgt_sysinfo | |
| CX86PseudoInstABI | |
| ►NGem5SystemC | |
| CAtomicExtension | |
| CControlExtension | |
| CGem5Extension | |
| CMemoryManager | |
| CTlmSenderState | |
| Nminor | Minor contains all the definitions within the MinorCPU apart from the CPU class itself |
| NProtoMessage | |
| ►Nsc_core | |
| Csc_attr_base | |
| Csc_attr_cltn | |
| Csc_attribute | |
| Csc_bind_proxy | |
| Csc_buffer | |
| Csc_byte_heap | |
| Csc_clock | |
| Csc_curr_proc_info | |
| Csc_direct_access | |
| Csc_event | |
| Csc_event_and_expr | |
| Csc_event_and_list | |
| Csc_event_finder | |
| Csc_event_finder_t | |
| Csc_event_or_expr | |
| Csc_event_or_list | |
| Csc_event_queue | |
| Csc_event_queue_if | |
| Csc_export | |
| Csc_export_base | |
| Csc_fifo | |
| Csc_fifo_blocking_in_if | |
| Csc_fifo_blocking_out_if | |
| Csc_fifo_in | |
| Csc_fifo_in_if | |
| Csc_fifo_nonblocking_in_if | |
| Csc_fifo_nonblocking_out_if | |
| Csc_fifo_out | |
| Csc_fifo_out_if | |
| Csc_in | |
| Csc_in< bool > | |
| Csc_in< sc_dt::sc_bigint< W > > | |
| Csc_in< sc_dt::sc_biguint< W > > | |
| Csc_in< sc_dt::sc_int< W > > | |
| Csc_in< sc_dt::sc_logic > | |
| Csc_in< sc_dt::sc_uint< W > > | |
| Csc_in_resolved | |
| Csc_in_rv | |
| Csc_inout | |
| Csc_inout< bool > | |
| Csc_inout< sc_dt::sc_bigint< W > > | |
| Csc_inout< sc_dt::sc_biguint< W > > | |
| Csc_inout< sc_dt::sc_int< W > > | |
| Csc_inout< sc_dt::sc_logic > | |
| Csc_inout< sc_dt::sc_uint< W > > | |
| Csc_inout_resolved | |
| Csc_inout_rv | |
| Csc_int_part_if | |
| Csc_int_sigref | |
| Csc_interface | |
| Csc_join | |
| Csc_member_access | |
| Csc_mempool | |
| Csc_module | |
| Csc_module_name | |
| Csc_mpobject | |
| Csc_mutex | |
| Csc_mutex_if | |
| Csc_object | |
| Csc_out | |
| Csc_out< sc_dt::sc_bigint< W > > | |
| Csc_out< sc_dt::sc_biguint< W > > | |
| Csc_out< sc_dt::sc_int< W > > | |
| Csc_out< sc_dt::sc_uint< W > > | |
| Csc_out_resolved | |
| Csc_out_rv | |
| Csc_port | |
| Csc_port_b | |
| Csc_port_base | |
| Csc_prim_channel | |
| Csc_process_b | |
| Csc_process_handle | |
| Csc_report | |
| Csc_report_handler | |
| Csc_semaphore | |
| Csc_semaphore_if | |
| Csc_sensitive | |
| Csc_signal | |
| Csc_signal< bool, WRITER_POLICY > | |
| Csc_signal< sc_dt::sc_bigint< W > > | |
| Csc_signal< sc_dt::sc_biguint< W > > | |
| Csc_signal< sc_dt::sc_int< W > > | |
| Csc_signal< sc_dt::sc_logic, WRITER_POLICY > | |
| Csc_signal< sc_dt::sc_uint< W > > | |
| Csc_signal_in_if | |
| Csc_signal_in_if< bool > | |
| Csc_signal_in_if< sc_dt::sc_bigint< W > > | |
| Csc_signal_in_if< sc_dt::sc_biguint< W > > | |
| Csc_signal_in_if< sc_dt::sc_int< W > > | |
| Csc_signal_in_if< sc_dt::sc_logic > | |
| Csc_signal_in_if< sc_dt::sc_uint< W > > | |
| Csc_signal_inout_if | |
| Csc_signal_resolved | |
| Csc_signal_rv | |
| Csc_signal_write_if | |
| Csc_signed_part_if | |
| Csc_signed_sigref | |
| Csc_simcontext | |
| ►Csc_spawn_options | |
| CReset | |
| Csc_time | |
| Csc_time_tuple | |
| Csc_trace_file | |
| Csc_trace_params | |
| Csc_uint_part_if | |
| Csc_uint_sigref | |
| Csc_unsigned_part_if | |
| Csc_unsigned_sigref | |
| Csc_unwind_exception | |
| Csc_user | |
| Csc_vector | |
| Csc_vector_assembly | |
| Csc_vector_base | |
| ►Csc_vector_iter | |
| CSelectIter | |
| CSelectIter< const U > | |
| Csc_vpool | |
| ►Nsc_dp | |
| Csc_barrier | |
| ►Nsc_dt | |
| Cieee_double | |
| Cieee_float | |
| Csc_bigint | |
| Csc_biguint | |
| Csc_bit | |
| Csc_bitref | |
| Csc_bitref_conv_r | |
| Csc_bitref_conv_r< T, sc_proxy_traits< sc_bv_base > > | |
| Csc_bitref_r | |
| Csc_bv | |
| Csc_bv_base | |
| Csc_concat_bool | |
| Csc_concatref | |
| Csc_concref | |
| Csc_concref_r | |
| Csc_context | |
| Csc_fix | |
| Csc_fix_fast | |
| Csc_fixed | |
| Csc_fixed_fast | |
| Csc_fxcast_switch | |
| Csc_fxnum | |
| Csc_fxnum_bitref | |
| Csc_fxnum_fast | |
| Csc_fxnum_fast_bitref | |
| Csc_fxnum_fast_observer | |
| Csc_fxnum_fast_subref | |
| Csc_fxnum_observer | |
| Csc_fxnum_subref | |
| Csc_fxtype_params | |
| Csc_fxval | |
| Csc_fxval_fast | |
| Csc_fxval_fast_observer | |
| Csc_fxval_observer | |
| Csc_generic_base | |
| Csc_global | |
| Csc_int | |
| Csc_int_base | |
| Csc_int_bitref | |
| Csc_int_bitref_r | |
| Csc_int_subref | |
| Csc_int_subref_r | |
| Csc_length_param | |
| Csc_logic | |
| Csc_lv | |
| Csc_lv_base | |
| Csc_mixed_proxy_traits_helper | |
| Csc_mixed_proxy_traits_helper< X, X > | |
| Csc_proxy | |
| Csc_proxy_traits | |
| Csc_proxy_traits< sc_bitref< X > > | |
| Csc_proxy_traits< sc_bitref_r< X > > | |
| Csc_proxy_traits< sc_bv_base > | |
| Csc_proxy_traits< sc_concref< X, Y > > | |
| Csc_proxy_traits< sc_concref_r< X, Y > > | |
| Csc_proxy_traits< sc_lv_base > | |
| Csc_proxy_traits< sc_proxy< X > > | |
| Csc_proxy_traits< sc_subref< X > > | |
| Csc_proxy_traits< sc_subref_r< X > > | |
| Csc_signed | |
| Csc_signed_bitref | |
| Csc_signed_bitref_r | |
| Csc_signed_subref | |
| Csc_signed_subref_r | |
| Csc_subref | |
| Csc_subref_r | |
| Csc_ufix | |
| Csc_ufix_fast | |
| Csc_ufixed | |
| Csc_ufixed_fast | |
| Csc_uint | |
| Csc_uint_base | |
| Csc_uint_bitref | |
| Csc_uint_bitref_r | |
| Csc_uint_subref | |
| Csc_uint_subref_r | |
| Csc_unsigned | |
| Csc_unsigned_bitref | |
| Csc_unsigned_bitref_r | |
| Csc_unsigned_subref | |
| Csc_unsigned_subref_r | |
| Csc_value_base | |
| Csc_without_context | |
| Cscfx_ieee_double | |
| Cscfx_ieee_float | |
| Cscfx_index | |
| Cscfx_mant | |
| Cscfx_mant_ref | |
| Cscfx_params | |
| Cscfx_pow10 | |
| Cscfx_rep | |
| Cscfx_rep_node | |
| Cscfx_string | |
| Cword_list | |
| Cword_short | |
| ►Nsc_gem5 | |
| CBuiltinExceptionWrapper | |
| CChannel | |
| CClockTick | |
| CCThread | |
| CDefaultReportMessages | |
| CDynamicSensitivity | |
| CDynamicSensitivityEvent | |
| CDynamicSensitivityEventAndList | |
| CDynamicSensitivityEventOrList | |
| Cenable_if | |
| Cenable_if< true, T > | |
| CEvent | |
| CExceptionWrapper | |
| CExceptionWrapperBase | |
| ►CGem5ToTlmBridge | |
| CBridgeResponsePort | |
| CGem5ToTlmBridgeBase | |
| CInternalScEvent | |
| Cis_const | |
| Cis_const< const T > | |
| Cis_more_const | |
| Cis_same | |
| Cis_same< T, T > | |
| CKernel | |
| CListNode | |
| CMethod | |
| CModule | |
| CNodeList | |
| CObject | |
| ►CPort | |
| CBinding | |
| CSensitivity | |
| CProcess | |
| CProcessFuncWrapper | |
| CProcessMemberFuncWrapper | |
| CProcessObjFuncWrapper | |
| CProcessObjRetFuncWrapper | |
| CPythonInitFunc | |
| Cremove_const | |
| Cremove_const< const T > | |
| Cremove_special_fptr | |
| Cremove_special_fptr< special_result &(*)(T)> | |
| CReportMsgInfo | |
| CReportSevInfo | |
| CReset | |
| CScEvent | |
| CScExportWrapper | |
| CScHalt | |
| ►CScheduler | |
| CTimeSlot | |
| CScInterfaceWrapper | |
| CScMainFiber | |
| CScPortWrapper | |
| CScSignalBase | |
| CScSignalBaseBinary | |
| CScSignalBasePicker | |
| CScSignalBasePicker< bool > | |
| CScSignalBasePicker< sc_dt::sc_logic > | |
| CScSignalBaseT | |
| CScSignalBinary | |
| CSensitivity | |
| CSensitivityEvent | |
| CSensitivityEvents | |
| Cspecial_result | |
| CStaticSensitivity | |
| CStaticSensitivityEvent | |
| CStaticSensitivityExport | |
| CStaticSensitivityFinder | |
| CStaticSensitivityInterface | |
| CStaticSensitivityPort | |
| ►CThread | |
| CContext | |
| CTlmInitiatorBaseWrapper | |
| CTlmTargetBaseWrapper | |
| ►CTlmToGem5Bridge | |
| CBridgeRequestPort | |
| CTlmToGem5BridgeBase | |
| CTraceFile | |
| CTraceVal | |
| CTraceVal<::sc_core::sc_event, Base > | |
| CTraceVal<::sc_core::sc_signal_in_if< T >, Base > | |
| CTraceVal<::sc_dt::sc_fxnum, Base > | |
| CTraceVal<::sc_dt::sc_fxnum_fast, Base > | |
| CTraceValBase | |
| CTraceValFxnumBase | |
| CUniqueNameGen | |
| CUnwindExceptionKill | |
| CUnwindExceptionReset | |
| CVcdTraceFile | |
| CVcdTraceScope | |
| CVcdTraceVal | |
| CVcdTraceValBase | |
| CVcdTraceValBool | |
| CVcdTraceValEvent | |
| CVcdTraceValFinite | |
| CVcdTraceValFloat | |
| CVcdTraceValFxnum | |
| CVcdTraceValFxval | |
| CVcdTraceValInt | |
| CVcdTraceValLogic | |
| CVcdTraceValScLogic | |
| CVcdTraceValTime | |
| CWriteChecker | |
| CWriteChecker< sc_core::SC_MANY_WRITERS > | |
| CWriteChecker< sc_core::SC_ONE_WRITER > | |
| Nsc_unnamed | |
| ►Nstd | Overload hash function for BasicBlockRange type |
| Cdeque | STL deque class |
| Chash< gem5::ArmISA::MiscRegNum32 > | |
| Chash< gem5::ArmISA::MiscRegNum64 > | |
| Chash< gem5::BasicBlockRange > | |
| Chash< gem5::BitUnionType< T > > | |
| Chash< gem5::ChannelAddr > | |
| Chash< gem5::FutexKey > | The unordered_map structure needs the parenthesis operator defined for std::hash if a user defined key is used |
| Chash< gem5::PowerISA::ExtMachInst > | |
| Chash< gem5::RegId > | |
| Chash< gem5::ruby::MachineID > | |
| Chash< gem5::X86ISA::ExtMachInst > | |
| Clist | STL list class |
| Cnumeric_limits< gem5::AMDGPU::binary32 > | |
| Cnumeric_limits< gem5::AMDGPU::fp16_e5m10_info > | |
| Cnumeric_limits< gem5::AMDGPU::fp16_e8m7_info > | |
| Cnumeric_limits< gem5::AMDGPU::fp8_e4m3_info > | |
| Cnumeric_limits< gem5::AMDGPU::fp8_e5m2_info > | |
| Cpair | STL pair class |
| Cvector | STL vector class |
| ►Ntlm | |
| Ccircular_buffer | |
| Ctlm_analysis_fifo | |
| Ctlm_analysis_if | |
| Ctlm_analysis_port | |
| Ctlm_analysis_triple | |
| Ctlm_array | |
| Ctlm_base_initiator_socket | |
| Ctlm_base_initiator_socket_b | |
| Ctlm_base_protocol_types | |
| Ctlm_base_socket_if | |
| Ctlm_base_target_socket | |
| Ctlm_base_target_socket_b | |
| Ctlm_blocking_get_if | |
| Ctlm_blocking_get_peek_if | |
| Ctlm_blocking_master_if | |
| Ctlm_blocking_peek_if | |
| Ctlm_blocking_put_if | |
| Ctlm_blocking_slave_if | |
| Ctlm_blocking_transport_if | |
| Ctlm_bool | |
| Ctlm_bw_direct_mem_if | |
| Ctlm_bw_nonblocking_transport_if | |
| Ctlm_bw_transport_if | |
| Ctlm_delayed_analysis_if | |
| Ctlm_delayed_write_if | |
| Ctlm_dmi | |
| Ctlm_endian_context | |
| Ctlm_endian_context_pool | |
| Ctlm_event_finder_t | |
| Ctlm_extension | |
| Ctlm_extension_base | |
| Ctlm_fifo | |
| Ctlm_fifo_config_size_if | |
| Ctlm_fifo_debug_if | |
| Ctlm_fifo_get_if | |
| Ctlm_fifo_put_if | |
| Ctlm_fw_direct_mem_if | |
| Ctlm_fw_nonblocking_transport_if | |
| Ctlm_fw_transport_if | |
| Ctlm_generic_payload | |
| Ctlm_get_if | |
| Ctlm_get_peek_if | |
| Ctlm_global_quantum | |
| Ctlm_initiator_socket | |
| Ctlm_master_if | |
| Ctlm_master_imp | |
| Ctlm_mm_interface | |
| Ctlm_nonblocking_get_if | |
| Ctlm_nonblocking_get_peek_if | |
| Ctlm_nonblocking_get_port | |
| Ctlm_nonblocking_master_if | |
| Ctlm_nonblocking_peek_if | |
| Ctlm_nonblocking_peek_port | |
| Ctlm_nonblocking_put_if | |
| Ctlm_nonblocking_put_port | |
| Ctlm_nonblocking_slave_if | |
| Ctlm_peek_if | |
| Ctlm_phase | |
| Ctlm_put_get_imp | |
| Ctlm_put_if | |
| Ctlm_req_rsp_channel | |
| Ctlm_slave_if | |
| Ctlm_slave_imp | |
| Ctlm_slave_to_transport | |
| Ctlm_tag | |
| Ctlm_target_socket | |
| Ctlm_transport_channel | |
| Ctlm_transport_dbg_if | |
| Ctlm_transport_if | |
| Ctlm_transport_to_master | |
| Ctlm_write_if | |
| ►Ntlm_utils | |
| Ccallback_binder_bw | |
| Ccallback_binder_fw | |
| Cconvenience_socket_base | |
| Cconvenience_socket_cb_holder | |
| Cfn_container | |
| Cinstance_specific_extension | |
| Cinstance_specific_extension_accessor | |
| Cinstance_specific_extension_carrier | |
| Cinstance_specific_extension_container | |
| Cinstance_specific_extension_container_pool | |
| Cinstance_specific_extensions_per_accessor | |
| Cispex_base | |
| Cmulti_init_base | |
| Cmulti_init_base_if | |
| Cmulti_passthrough_initiator_socket | |
| Cmulti_passthrough_initiator_socket_optional | |
| Cmulti_passthrough_target_socket | |
| Cmulti_passthrough_target_socket_optional | |
| Cmulti_socket_base | |
| Cmulti_target_base | |
| Cmulti_target_base_if | |
| Cmulti_to_multi_bind_base | |
| Cpassthrough_socket_base | |
| Cpassthrough_target_socket | |
| ►Cpassthrough_target_socket_b | |
| Cprocess | |
| Cpassthrough_target_socket_optional | |
| Cpassthrough_target_socket_tagged | |
| ►Cpassthrough_target_socket_tagged_b | |
| Cprocess | |
| Cpassthrough_target_socket_tagged_optional | |
| ►Cpeq_with_cb_and_phase | An event queue that can contain any number of pending notifications |
| Cdelta_list | |
| Cpeq_with_get | |
| Csimple_initiator_socket | |
| ►Csimple_initiator_socket_b | |
| Cprocess | |
| Csimple_initiator_socket_optional | |
| Csimple_initiator_socket_tagged | |
| ►Csimple_initiator_socket_tagged_b | |
| Cprocess | |
| Csimple_initiator_socket_tagged_optional | |
| Csimple_socket_base | |
| Csimple_target_socket | |
| ►Csimple_target_socket_b | |
| Cbw_process | |
| ►Cfw_process | |
| Cmm_end_event_ext | |
| Cprocess_handle_class | |
| Cprocess_handle_list | |
| Csimple_target_socket_optional | |
| Csimple_target_socket_tagged | |
| ►Csimple_target_socket_tagged_b | |
| Cbw_process | |
| ►Cfw_process | |
| Cmm_end_event_ext | |
| Cprocess_handle_class | |
| Cprocess_handle_list | |
| Csimple_target_socket_tagged_optional | |
| ►Ctime_ordered_list | |
| Celement | |
| Ctlm_quantumkeeper | |
