35#include "debug/RubyNetwork.hh"
62 : m_nodes(ruby_system->MachineType_base_number(MachineType_NUM)),
63 m_number_of_switches(num_routers), m_vnets(num_vnets),
64 m_ext_link_vector(ext_links), m_int_link_vector(int_links),
65 m_ruby_system(ruby_system)
79 i != ext_links.end(); ++
i) {
84 int machine_base_idx =
86 int ext_idx1 = machine_base_idx + abs_cntrl->
getVersion();
87 int ext_idx2 = ext_idx1 +
m_nodes;
92 addLink(ext_idx1, int_idx, ext_link);
94 addLink(int_idx, ext_idx2, ext_link);
99 i != int_links.end(); ++
i) {
114 addLink(src, dst, int_link, src_outport, dst_inport);
123 for (LinkMap::const_iterator
i =
m_link_map.begin();
126 max_switch_id = std::max(max_switch_id, src_dest.first);
127 max_switch_id = std::max(max_switch_id, src_dest.second);
131 int num_switches = max_switch_id+1;
135 Matrix component_latencies(num_switches,
138 Matrix component_inter_switches(num_switches,
143 for (
int i = 0;
i < topology_weights[0].size();
i++) {
145 topology_weights[
v][
i][
i] = 0;
153 int src = src_dest.first;
154 int dst = src_dest.second;
158 for (
int l = 0;
l < link_entries.size();
l++) {
160 if (link->
mVnets.size() == 0) {
164 fatal_if(vnet_done[
v],
"Two links connecting same src"
165 " and destination cannot support same vnets");
167 component_latencies[src][dst][
v] = link->
m_latency;
168 topology_weights[
v][src][dst] = link->
m_weight;
172 for (
int v = 0;
v < link->
mVnets.size();
v++) {
175 "(setting latency and weight for vnet %d)", vnet);
178 fatal_if(vnet_done[vnet],
"Two links connecting same src"
179 " and destination cannot support same vnets");
181 component_latencies[src][dst][vnet] = link->
m_latency;
182 topology_weights[vnet][src][dst] = link->
m_weight;
183 vnet_done[vnet] =
true;
191 component_inter_switches);
193 for (
int i = 0;
i < topology_weights[0].size();
i++) {
194 for (
int j = 0; j < topology_weights[0][
i].size(); j++) {
201 bool realLink =
false;
204 int weight = topology_weights[
v][
i][j];
230 src_dest_pair.first = src;
231 src_dest_pair.second = dest;
234 link_entry.
link = link;
245 lit->second.push_back(link_entry);
248 links.push_back(link_entry);
265 src_dest.first = src;
266 src_dest.second = dest;
268 for (
int l = 0;
l < links.size();
l++) {
269 link_entry = links[
l];
273 if (link->
mVnets.size() == 0) {
275 routing_table_entry);
277 for (
int v = 0;
v< link->
mVnets.size();
v++) {
279 linkRoute[vnet] = routing_table_entry[vnet];
288 src_dest.first = src;
289 src_dest.second = dest;
291 for (
int l = 0;
l < links.size();
l++) {
292 link_entry = links[
l];
296 if (link->
mVnets.size() == 0) {
298 routing_table_entry);
300 for (
int v = 0;
v< link->
mVnets.size();
v++) {
302 linkRoute[vnet] = routing_table_entry[vnet];
310 src_dest.first = src;
311 src_dest.second = dest;
313 for (
int l = 0;
l < links.size();
l++) {
314 link_entry = links[
l];
318 if (link->
mVnets.size() == 0) {
320 dest - (2 *
m_nodes), link, routing_table_entry,
324 for (
int v = 0;
v< link->
mVnets.size();
v++) {
326 linkRoute[vnet] = routing_table_entry[vnet];
329 dest - (2 *
m_nodes), link, linkRoute,
343 int nodes = current_dist[0].size();
355 for (
int i = 0;
i < nodes;
i++) {
356 for (
int j = 0; j < nodes; j++) {
368 int minimum = current_dist[
v][
i][j];
369 int previous_minimum = minimum;
370 int intermediate_switch = -1;
371 for (
int k = 0;
k < nodes;
k++) {
372 minimum = std::min(minimum,
373 current_dist[
v][
i][
k] + current_dist[
v][
k][j]);
374 if (previous_minimum != minimum) {
375 intermediate_switch =
k;
376 inter_switches[
i][j][
v] =
377 inter_switches[
i][
k][
v] +
378 inter_switches[
k][j][
v] + 1;
380 previous_minimum = minimum;
382 if (current_dist[
v][
i][j] != minimum) {
384 current_dist[
v][
i][j] = minimum;
385 assert(intermediate_switch >= 0);
386 assert(intermediate_switch < latencies[
i].size());
388 latencies[
i][intermediate_switch][
v] +
389 latencies[intermediate_switch][j][
v];
411 return weights[vnet][src][next] +
dist[vnet][next][
final] ==
412 dist[vnet][src][
final];
425 machines = MachineType_NUM;
428 for (
int m = 0;
m < machines;
m++) {
437 weights,
dist, vnet)) {
445 DPRINTF(RubyNetwork,
"Returning shortest path\n"
446 "(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, "
447 "src: %d, next: %d, vnet:%d result: %s\n",
448 (src-(2*max_machines)), (next-(2*max_machines)),
449 src, next, vnet, result);
MachineType getType() const
NodeID getVersion() const
std::vector< int > mVnets
void add(MachineID newElement)
virtual void makeInternalLink(SwitchID src, SwitchID dest, BasicLink *link, std::vector< NetDest > &routing_table_entry, PortDirection src_outport, PortDirection dst_inport)=0
virtual void makeExtOutLink(SwitchID src, NodeID dest, BasicLink *link, std::vector< NetDest > &routing_table_entry)=0
virtual void makeExtInLink(NodeID src, SwitchID dest, BasicLink *link, std::vector< NetDest > &routing_table_entry)=0
int MachineType_base_number(const MachineType &obj)
int MachineType_base_count(const MachineType &obj)
std::vector< BasicIntLink * > m_int_link_vector
void makeLink(Network *net, SwitchID src, SwitchID dest, std::vector< NetDest > &routing_table_entry)
RubySystem * m_ruby_system
void addLink(SwitchID src, SwitchID dest, BasicLink *link, PortDirection src_outport_dirn="", PortDirection dest_inport_dirn="")
const uint32_t m_number_of_switches
void createLinks(Network *net)
void extend_shortest_path(Matrix ¤t_dist, Matrix &latencies, Matrix &inter_switches)
bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, const Matrix &weights, const Matrix &dist, int vnet)
Matrix shortest_path(const Matrix &weights, Matrix &latencies, Matrix &inter_switches)
Topology(uint32_t num_nodes, uint32_t num_routers, uint32_t num_vnets, const std::vector< BasicExtLink * > &ext_links, const std::vector< BasicIntLink * > &int_links, RubySystem *ruby_system)
NetDest shortest_path_to_node(SwitchID src, SwitchID next, const Matrix &weights, const Matrix &dist, int vnet)
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
const Params & params() const
std::string PortDirection
const int INFINITE_LATENCY
const FlagsType dist
Print the distribution.
Copyright (c) 2024 Arm Limited All rights reserved.
PortDirection dst_inport_dirn
PortDirection src_outport_dirn