gem5 v24.1.0.1
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interrupts.cc
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1/*
2 * Copyright (c) 2009, 2012-2013, 2016, 2019, 2023 Arm Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
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23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "arch/arm/interrupts.hh"
39
40#include "arch/arm/system.hh"
41
42namespace gem5
43{
44
45bool
46ArmISA::Interrupts::takeInt32(InterruptTypes int_type) const
47{
48 InterruptMask mask;
49 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
50 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
51 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
52 ExceptionLevel el = currEL(tc);
53 bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
54 bool is_secure = isSecure(tc);
55
56 switch(int_type) {
57 case INT_FIQ:
58 cpsr_mask_bit = cpsr.f;
59 scr_routing_bit = scr.fiq;
60 scr_fwaw_bit = scr.fw;
61 hcr_mask_override_bit = hcr.fmo;
62 break;
63 case INT_IRQ:
64 cpsr_mask_bit = cpsr.i;
65 scr_routing_bit = scr.irq;
66 scr_fwaw_bit = 1;
67 hcr_mask_override_bit = hcr.imo;
68 break;
69 case INT_ABT:
70 cpsr_mask_bit = cpsr.a;
71 scr_routing_bit = scr.ea;
72 scr_fwaw_bit = scr.aw;
73 hcr_mask_override_bit = hcr.amo;
74 break;
75 default:
76 panic("Unhandled interrupt type!");
77 }
78
79 if (hcr.tge)
80 hcr_mask_override_bit = 1;
81
82 if (!scr_routing_bit) {
83 // SCR IRQ == 0
84 if (!hcr_mask_override_bit)
85 mask = INT_MASK_M;
86 else {
87 if (!is_secure && (el == EL0 || el == EL1))
88 mask = INT_MASK_T;
89 else
90 mask = INT_MASK_M;
91 }
92 } else {
93 // SCR IRQ == 1
94 if ((!is_secure) &&
95 (hcr_mask_override_bit ||
96 (!scr_fwaw_bit && !hcr_mask_override_bit)))
97 mask = INT_MASK_T;
98 else
99 mask = INT_MASK_M;
100 }
101 return ((mask == INT_MASK_T) ||
102 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
103 (mask != INT_MASK_P);
104}
105
106
107bool
108ArmISA::Interrupts::takeInt64(InterruptTypes int_type) const
109{
110 InterruptMask mask;
111 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
112 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
113 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
114 ExceptionLevel el = currEL(tc);
115 bool cpsr_mask_bit, scr_routing_bit, hcr_mask_override_bit;
116 bool is_secure = isSecureBelowEL3(tc);
117
118 switch(int_type) {
119 case INT_FIQ:
120 cpsr_mask_bit = cpsr.f;
121 scr_routing_bit = scr.fiq;
122 hcr_mask_override_bit = hcr.fmo;
123 break;
124 case INT_IRQ:
125 cpsr_mask_bit = cpsr.i;
126 scr_routing_bit = scr.irq;
127 hcr_mask_override_bit = hcr.imo;
128 break;
129 case INT_ABT:
130 cpsr_mask_bit = cpsr.a;
131 scr_routing_bit = scr.ea;
132 hcr_mask_override_bit = hcr.amo;
133 break;
134 default:
135 panic("Unhandled interrupt type!");
136 }
137
138 if (is_secure) {
139 if (!scr.eel2) {
140 if (!scr_routing_bit) {
141 // NS=0,EEL2=0,EAI/IRQ/FIQ=0
142 if (el == EL3)
143 mask = INT_MASK_P;
144 else
145 mask = INT_MASK_M;
146 } else {
147 // NS=0,EEL2=0,EAI/IRQ/FIQ=1
148 if (el == EL3)
149 mask = INT_MASK_M;
150 else
151 mask = INT_MASK_T;
152 }
153 } else {
154 if (!scr_routing_bit) {
155 if (!hcr.tge) {
156 if (!hcr_mask_override_bit) {
157 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=0,AMO/IMO/FMO=0
158 if (el == EL3 || el == EL2)
159 mask = INT_MASK_P;
160 else
161 mask = INT_MASK_M;
162 } else {
163 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=0,AMO/IMO/FMO=1
164 if (el == EL3)
165 mask = INT_MASK_P;
166 else if (el == EL2)
167 mask = INT_MASK_M;
168 else
169 mask = INT_MASK_T;
170 }
171 } else {
172 if (!hcr.e2h) {
173 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=1,E2H=0
174 if (el == EL3)
175 mask = INT_MASK_P;
176 else if (el == EL2)
177 mask = INT_MASK_M;
178 else
179 mask = INT_MASK_T;
180 } else {
181 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=1,E2H=1
182 if (el == EL3)
183 mask = INT_MASK_P;
184 else
185 mask = INT_MASK_M;
186 }
187 }
188 } else {
189 if (!hcr.tge) {
190 // NS=0,EEL2=1,EAI/IRQ/FIQ=1,TGE=0
191 if (el == EL3)
192 mask = INT_MASK_M;
193 else
194 mask = INT_MASK_T;
195 } else {
196 // NS=0,EEL2=1,EAI/IRQ/FIQ=1,TGE=1
197 if (el == EL3)
198 mask = INT_MASK_M;
199 else
200 mask = INT_MASK_T;
201 }
202 }
203 }
204 } else {
205 if (!scr_routing_bit) {
206 if (!scr.rw) {
207 if (!hcr.tge) {
208 if (!hcr_mask_override_bit) {
209 // NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=0,AMO/IMO?/FMO=0
210 if (el == EL3)
211 mask = INT_MASK_P;
212 else
213 mask = INT_MASK_M;
214 } else {
215 // NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=0,AMO/IMO?/FMO=1
216 if (el == EL3)
217 mask = INT_MASK_P;
218 else if (el == EL2)
219 mask = INT_MASK_M;
220 else
221 mask = INT_MASK_T;
222 }
223 } else {
224 // NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=1
225 if (el == EL3)
226 mask = INT_MASK_P;
227 else if (el == EL2)
228 mask = INT_MASK_M;
229 else
230 mask = INT_MASK_T;
231 }
232 } else {
233 if (!hcr.tge) {
234 if (!hcr_mask_override_bit) {
235 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=0,AMO/IMO/FMO=0
236 if (el == EL3 || el == EL2)
237 mask = INT_MASK_P;
238 else
239 mask = INT_MASK_M;
240 } else {
241 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=0,AMO/IMO/FMO=1
242 if (el == EL3)
243 mask = INT_MASK_P;
244 else if (el == EL2)
245 mask = INT_MASK_M;
246 else
247 mask = INT_MASK_T;
248 }
249 } else {
250 if (!hcr.e2h) {
251 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=1,E2H=0
252 if (el == EL3)
253 mask = INT_MASK_P;
254 else if (el == EL2)
255 mask = INT_MASK_M;
256 else
257 mask = INT_MASK_T;
258 } else {
259 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=1,E2H=1
260 if (el == EL3)
261 mask = INT_MASK_P;
262 else
263 mask = INT_MASK_M;
264 }
265 }
266 }
267 } else {
268 if (el == EL3)
269 mask = INT_MASK_M;
270 else
271 mask = INT_MASK_T;
272 }
273 }
274 return ((mask == INT_MASK_T) ||
275 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
276 (mask != INT_MASK_P);
277}
278
279bool
280ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
281{
282 // Table G1-17~19 of ARM V8 ARM
283 return ArmSystem::highestELIs64(tc) ? takeInt64(int_type) :
284 takeInt32(int_type);
285
286}
287
288bool
289ArmISA::Interrupts::takeVirtualInt(InterruptTypes int_type) const
290{
291 return ArmSystem::highestELIs64(tc) ? takeVirtualInt64(int_type) :
292 takeVirtualInt32(int_type);
293
294}
295
296bool
297ArmISA::Interrupts::takeVirtualInt32(InterruptTypes int_type) const
298{
299 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
300 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
301
302 bool no_vhe = !HaveExt(tc, ArmExtension::FEAT_VHE);
303 bool amo, fmo, imo;
304 bool cpsr_mask_bit, hcr_mask_override_bit;
305
306 if (hcr.tge == 1){
307 amo = (no_vhe || hcr.e2h == 0);
308 fmo = (no_vhe || hcr.e2h == 0);
309 imo = (no_vhe || hcr.e2h == 0);
310 } else {
311 amo = hcr.amo;
312 fmo = hcr.fmo;
313 imo = hcr.imo;
314 }
315
316 bool is_hyp_mode = currEL(tc) == EL2;
317 bool is_secure = ArmISA::isSecure(tc);
318
319 switch(int_type) {
320 case INT_VIRT_FIQ:
321 cpsr_mask_bit = cpsr.f;
322 hcr_mask_override_bit = fmo;
323 break;
324 case INT_VIRT_IRQ:
325 cpsr_mask_bit = cpsr.i;
326 hcr_mask_override_bit = imo;
327 break;
328 case INT_VIRT_ABT:
329 cpsr_mask_bit = cpsr.a;
330 hcr_mask_override_bit = amo;
331 break;
332 default:
333 panic("Unhandled interrupt type!");
334 }
335 return !cpsr_mask_bit && hcr_mask_override_bit &&
336 !is_secure && !is_hyp_mode;
337}
338
339bool
340ArmISA::Interrupts::takeVirtualInt64(InterruptTypes int_type) const
341{
342 InterruptMask mask;
343 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
344 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
345 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
346
347 ExceptionLevel el = currEL(tc);
348 bool cpsr_mask_bit, hcr_mask_override_bit;
349 bool is_secure = ArmISA::isSecureBelowEL3(tc);
350
351 switch(int_type) {
352 case INT_VIRT_FIQ:
353 cpsr_mask_bit = cpsr.f;
354 hcr_mask_override_bit = hcr.fmo;
355 break;
356 case INT_VIRT_IRQ:
357 cpsr_mask_bit = cpsr.i;
358 hcr_mask_override_bit = hcr.imo;
359 break;
360 case INT_VIRT_ABT:
361 cpsr_mask_bit = cpsr.a;
362 hcr_mask_override_bit = hcr.amo;
363 break;
364 default:
365 panic("Unhandled interrupt type!");
366 }
367
368 if (is_secure) {
369 if (!scr.eel2) {
370 // NS=0,EEL2=0
371 mask = INT_MASK_P;
372 } else {
373 if (!hcr.tge) {
374 if (!hcr_mask_override_bit) {
375 // NS=0,EEL2=1,TGE=0,AMO/IMO/FMO=0
376 mask = INT_MASK_P;
377 } else {
378 // NS=0,EEL2=1,TGE=0,AMO/IMO/FMO=1
379 if (el == EL2 || el == EL3)
380 mask = INT_MASK_P;
381 else
382 mask = INT_MASK_M;
383 }
384 } else {
385 // NS=0,EEL2=1,TGE=1
386 mask = INT_MASK_P;
387 }
388 }
389 } else {
390 if (!hcr.tge) {
391 if (!hcr_mask_override_bit) {
392 // NS=1,TGE=0,AMO/IMO/FMO=0
393 mask = INT_MASK_P;
394 } else {
395 // NS=1,TGE=0,AMO/IMO/FMO=1
396 if (el == EL2 || el == EL3)
397 mask = INT_MASK_P;
398 else
399 mask = INT_MASK_M;
400 }
401 } else {
402 // NS=1,TGE=1
403 mask = INT_MASK_P;
404 }
405 }
406
407 return ((mask == INT_MASK_T) ||
408 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
409 (mask != INT_MASK_P);
410}
411
412} // namespace gem5
gem5::ArmISA::Interrupts::takeInt64
bool takeInt64(InterruptTypes int_type) const
Definition interrupts.cc:108
gem5::ArmISA::Interrupts::takeInt
bool takeInt(InterruptTypes int_type) const
Definition interrupts.cc:280
gem5::ArmISA::Interrupts::takeInt32
bool takeInt32(InterruptTypes int_type) const
Definition interrupts.cc:46
gem5::ArmISA::Interrupts::takeVirtualInt64
bool takeVirtualInt64(InterruptTypes int_type) const
Definition interrupts.cc:340
gem5::ArmISA::Interrupts::takeVirtualInt
bool takeVirtualInt(InterruptTypes int_type) const
Definition interrupts.cc:289
gem5::ArmISA::Interrupts::takeVirtualInt32
bool takeVirtualInt32(InterruptTypes int_type) const
Definition interrupts.cc:297
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition system.hh:187
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition interrupts.hh:44
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition utility.cc:134
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition utility.cc:74
gem5::ArmISA::imo
Bitfield< 4 > imo
Definition misc_types.hh:362
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition utility.cc:86
gem5::ArmISA::fmo
Bitfield< 3 > fmo
Definition misc_types.hh:363
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition misc.hh:628
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition misc.hh:79
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition misc.hh:619
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition misc_types.hh:73
gem5::ArmISA::amo
Bitfield< 5 > amo
Definition misc_types.hh:361
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition utility.cc:232
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
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