gem5 v24.1.0.1
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
misc.cc
Go to the documentation of this file.
1/*
2 * Copyright (c) 2010-2013, 2015-2024 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "arch/arm/regs/misc.hh"
39
40#include <tuple>
41
42#include "arch/arm/insts/misc64.hh"
43#include "arch/arm/isa.hh"
44#include "base/bitfield.hh"
45#include "base/logging.hh"
46#include "cpu/thread_context.hh"
47#include "dev/arm/gic_v3_cpu_interface.hh"
48#include "params/ArmISA.hh"
49#include "sim/full_system.hh"
50
51namespace gem5
52{
53
54namespace ArmISA
55{
56
57namespace
58{
59
60std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
61 // MCR/MRC regs
62 { MiscRegNum32(14, 0, 0, 0, 0), MISCREG_DBGDIDR },
63 { MiscRegNum32(14, 0, 0, 0, 2), MISCREG_DBGDTRRXext },
64 { MiscRegNum32(14, 0, 0, 0, 4), MISCREG_DBGBVR0 },
65 { MiscRegNum32(14, 0, 0, 0, 5), MISCREG_DBGBCR0 },
66 { MiscRegNum32(14, 0, 0, 0, 6), MISCREG_DBGWVR0 },
67 { MiscRegNum32(14, 0, 0, 0, 7), MISCREG_DBGWCR0 },
68 { MiscRegNum32(14, 0, 0, 1, 0), MISCREG_DBGDSCRint },
69 { MiscRegNum32(14, 0, 0, 1, 4), MISCREG_DBGBVR1 },
70 { MiscRegNum32(14, 0, 0, 1, 5), MISCREG_DBGBCR1 },
71 { MiscRegNum32(14, 0, 0, 1, 6), MISCREG_DBGWVR1 },
72 { MiscRegNum32(14, 0, 0, 1, 7), MISCREG_DBGWCR1 },
73 { MiscRegNum32(14, 0, 0, 2, 2), MISCREG_DBGDSCRext },
74 { MiscRegNum32(14, 0, 0, 2, 4), MISCREG_DBGBVR2 },
75 { MiscRegNum32(14, 0, 0, 2, 5), MISCREG_DBGBCR2 },
76 { MiscRegNum32(14, 0, 0, 2, 6), MISCREG_DBGWVR2 },
77 { MiscRegNum32(14, 0, 0, 2, 7), MISCREG_DBGWCR2 },
78 { MiscRegNum32(14, 0, 0, 3, 2), MISCREG_DBGDTRTXext },
79 { MiscRegNum32(14, 0, 0, 3, 4), MISCREG_DBGBVR3 },
80 { MiscRegNum32(14, 0, 0, 3, 5), MISCREG_DBGBCR3 },
81 { MiscRegNum32(14, 0, 0, 3, 6), MISCREG_DBGWVR3 },
82 { MiscRegNum32(14, 0, 0, 3, 7), MISCREG_DBGWCR3 },
83 { MiscRegNum32(14, 0, 0, 4, 4), MISCREG_DBGBVR4 },
84 { MiscRegNum32(14, 0, 0, 4, 5), MISCREG_DBGBCR4 },
85 { MiscRegNum32(14, 0, 0, 4, 6), MISCREG_DBGWVR4 },
86 { MiscRegNum32(14, 0, 0, 4, 7), MISCREG_DBGWCR4 },
87 { MiscRegNum32(14, 0, 0, 5, 4), MISCREG_DBGBVR5 },
88 { MiscRegNum32(14, 0, 0, 5, 5), MISCREG_DBGBCR5 },
89 { MiscRegNum32(14, 0, 0, 5, 6), MISCREG_DBGWVR5 },
90 { MiscRegNum32(14, 0, 0, 5, 7), MISCREG_DBGWCR5 },
91 { MiscRegNum32(14, 0, 0, 6, 2), MISCREG_DBGOSECCR },
92 { MiscRegNum32(14, 0, 0, 6, 4), MISCREG_DBGBVR6 },
93 { MiscRegNum32(14, 0, 0, 6, 5), MISCREG_DBGBCR6 },
94 { MiscRegNum32(14, 0, 0, 6, 6), MISCREG_DBGWVR6 },
95 { MiscRegNum32(14, 0, 0, 6, 7), MISCREG_DBGWCR6 },
96 { MiscRegNum32(14, 0, 0, 7, 0), MISCREG_DBGVCR },
97 { MiscRegNum32(14, 0, 0, 7, 4), MISCREG_DBGBVR7 },
98 { MiscRegNum32(14, 0, 0, 7, 5), MISCREG_DBGBCR7 },
99 { MiscRegNum32(14, 0, 0, 7, 6), MISCREG_DBGWVR7 },
100 { MiscRegNum32(14, 0, 0, 7, 7), MISCREG_DBGWCR7 },
101 { MiscRegNum32(14, 0, 0, 8, 4), MISCREG_DBGBVR8 },
102 { MiscRegNum32(14, 0, 0, 8, 5), MISCREG_DBGBCR8 },
103 { MiscRegNum32(14, 0, 0, 8, 6), MISCREG_DBGWVR8 },
104 { MiscRegNum32(14, 0, 0, 8, 7), MISCREG_DBGWCR8 },
105 { MiscRegNum32(14, 0, 0, 9, 4), MISCREG_DBGBVR9 },
106 { MiscRegNum32(14, 0, 0, 9, 5), MISCREG_DBGBCR9 },
107 { MiscRegNum32(14, 0, 0, 9, 6), MISCREG_DBGWVR9 },
108 { MiscRegNum32(14, 0, 0, 9, 7), MISCREG_DBGWCR9 },
109 { MiscRegNum32(14, 0, 0, 10, 4), MISCREG_DBGBVR10 },
110 { MiscRegNum32(14, 0, 0, 10, 5), MISCREG_DBGBCR10 },
111 { MiscRegNum32(14, 0, 0, 10, 6), MISCREG_DBGWVR10 },
112 { MiscRegNum32(14, 0, 0, 10, 7), MISCREG_DBGWCR10 },
113 { MiscRegNum32(14, 0, 0, 11, 4), MISCREG_DBGBVR11 },
114 { MiscRegNum32(14, 0, 0, 11, 5), MISCREG_DBGBCR11 },
115 { MiscRegNum32(14, 0, 0, 11, 6), MISCREG_DBGWVR11 },
116 { MiscRegNum32(14, 0, 0, 11, 7), MISCREG_DBGWCR11 },
117 { MiscRegNum32(14, 0, 0, 12, 4), MISCREG_DBGBVR12 },
118 { MiscRegNum32(14, 0, 0, 12, 5), MISCREG_DBGBCR12 },
119 { MiscRegNum32(14, 0, 0, 12, 6), MISCREG_DBGWVR12 },
120 { MiscRegNum32(14, 0, 0, 12, 7), MISCREG_DBGWCR12 },
121 { MiscRegNum32(14, 0, 0, 13, 4), MISCREG_DBGBVR13 },
122 { MiscRegNum32(14, 0, 0, 13, 5), MISCREG_DBGBCR13 },
123 { MiscRegNum32(14, 0, 0, 13, 6), MISCREG_DBGWVR13 },
124 { MiscRegNum32(14, 0, 0, 13, 7), MISCREG_DBGWCR13 },
125 { MiscRegNum32(14, 0, 0, 14, 4), MISCREG_DBGBVR14 },
126 { MiscRegNum32(14, 0, 0, 14, 5), MISCREG_DBGBCR14 },
127 { MiscRegNum32(14, 0, 0, 14, 6), MISCREG_DBGWVR14 },
128 { MiscRegNum32(14, 0, 0, 14, 7), MISCREG_DBGWCR14 },
129 { MiscRegNum32(14, 0, 0, 15, 4), MISCREG_DBGBVR15 },
130 { MiscRegNum32(14, 0, 0, 15, 5), MISCREG_DBGBCR15 },
131 { MiscRegNum32(14, 0, 0, 15, 6), MISCREG_DBGWVR15 },
132 { MiscRegNum32(14, 0, 0, 15, 7), MISCREG_DBGWCR15 },
133 { MiscRegNum32(14, 0, 1, 0, 1), MISCREG_DBGBXVR0 },
134 { MiscRegNum32(14, 0, 1, 0, 4), MISCREG_DBGOSLAR },
135 { MiscRegNum32(14, 0, 1, 1, 1), MISCREG_DBGBXVR1 },
136 { MiscRegNum32(14, 0, 1, 1, 4), MISCREG_DBGOSLSR },
137 { MiscRegNum32(14, 0, 1, 2, 1), MISCREG_DBGBXVR2 },
138 { MiscRegNum32(14, 0, 1, 3, 1), MISCREG_DBGBXVR3 },
139 { MiscRegNum32(14, 0, 1, 3, 4), MISCREG_DBGOSDLR },
140 { MiscRegNum32(14, 0, 1, 4, 1), MISCREG_DBGBXVR4 },
141 { MiscRegNum32(14, 0, 1, 4, 4), MISCREG_DBGPRCR },
142 { MiscRegNum32(14, 0, 1, 5, 1), MISCREG_DBGBXVR5 },
143 { MiscRegNum32(14, 0, 1, 6, 1), MISCREG_DBGBXVR6 },
144 { MiscRegNum32(14, 0, 1, 7, 1), MISCREG_DBGBXVR7 },
145 { MiscRegNum32(14, 0, 1, 8, 1), MISCREG_DBGBXVR8 },
146 { MiscRegNum32(14, 0, 1, 9, 1), MISCREG_DBGBXVR9 },
147 { MiscRegNum32(14, 0, 1, 10, 1), MISCREG_DBGBXVR10 },
148 { MiscRegNum32(14, 0, 1, 11, 1), MISCREG_DBGBXVR11 },
149 { MiscRegNum32(14, 0, 1, 12, 1), MISCREG_DBGBXVR12 },
150 { MiscRegNum32(14, 0, 1, 13, 1), MISCREG_DBGBXVR13 },
151 { MiscRegNum32(14, 0, 1, 14, 1), MISCREG_DBGBXVR14 },
152 { MiscRegNum32(14, 0, 1, 15, 1), MISCREG_DBGBXVR15 },
153 { MiscRegNum32(14, 6, 1, 0, 0), MISCREG_TEEHBR },
154 { MiscRegNum32(14, 7, 0, 0, 0), MISCREG_JIDR },
155 { MiscRegNum32(14, 7, 1, 0, 0), MISCREG_JOSCR },
156 { MiscRegNum32(14, 7, 2, 0, 0), MISCREG_JMCR },
157 { MiscRegNum32(15, 0, 0, 0, 0), MISCREG_MIDR },
158 { MiscRegNum32(15, 0, 0, 0, 1), MISCREG_CTR },
159 { MiscRegNum32(15, 0, 0, 0, 2), MISCREG_TCMTR },
160 { MiscRegNum32(15, 0, 0, 0, 3), MISCREG_TLBTR },
161 { MiscRegNum32(15, 0, 0, 0, 4), MISCREG_MIDR },
162 { MiscRegNum32(15, 0, 0, 0, 5), MISCREG_MPIDR },
163 { MiscRegNum32(15, 0, 0, 0, 6), MISCREG_REVIDR },
164 { MiscRegNum32(15, 0, 0, 0, 7), MISCREG_MIDR },
165 { MiscRegNum32(15, 0, 0, 1, 0), MISCREG_ID_PFR0 },
166 { MiscRegNum32(15, 0, 0, 1, 1), MISCREG_ID_PFR1 },
167 { MiscRegNum32(15, 0, 0, 1, 2), MISCREG_ID_DFR0 },
168 { MiscRegNum32(15, 0, 0, 1, 3), MISCREG_ID_AFR0 },
169 { MiscRegNum32(15, 0, 0, 1, 4), MISCREG_ID_MMFR0 },
170 { MiscRegNum32(15, 0, 0, 1, 5), MISCREG_ID_MMFR1 },
171 { MiscRegNum32(15, 0, 0, 1, 6), MISCREG_ID_MMFR2 },
172 { MiscRegNum32(15, 0, 0, 1, 7), MISCREG_ID_MMFR3 },
173 { MiscRegNum32(15, 0, 0, 2, 0), MISCREG_ID_ISAR0 },
174 { MiscRegNum32(15, 0, 0, 2, 1), MISCREG_ID_ISAR1 },
175 { MiscRegNum32(15, 0, 0, 2, 2), MISCREG_ID_ISAR2 },
176 { MiscRegNum32(15, 0, 0, 2, 3), MISCREG_ID_ISAR3 },
177 { MiscRegNum32(15, 0, 0, 2, 4), MISCREG_ID_ISAR4 },
178 { MiscRegNum32(15, 0, 0, 2, 5), MISCREG_ID_ISAR5 },
179 { MiscRegNum32(15, 0, 0, 2, 6), MISCREG_ID_MMFR4 },
180 { MiscRegNum32(15, 0, 0, 2, 7), MISCREG_ID_ISAR6 },
181 { MiscRegNum32(15, 0, 0, 3, 0), MISCREG_RAZ },
182 { MiscRegNum32(15, 0, 0, 3, 1), MISCREG_RAZ },
183 { MiscRegNum32(15, 0, 0, 3, 2), MISCREG_RAZ },
184 { MiscRegNum32(15, 0, 0, 3, 3), MISCREG_RAZ },
185 { MiscRegNum32(15, 0, 0, 3, 4), MISCREG_RAZ },
186 { MiscRegNum32(15, 0, 0, 3, 5), MISCREG_RAZ },
187 { MiscRegNum32(15, 0, 0, 3, 6), MISCREG_RAZ },
188 { MiscRegNum32(15, 0, 0, 3, 7), MISCREG_RAZ },
189 { MiscRegNum32(15, 0, 0, 4, 0), MISCREG_RAZ },
190 { MiscRegNum32(15, 0, 0, 4, 1), MISCREG_RAZ },
191 { MiscRegNum32(15, 0, 0, 4, 2), MISCREG_RAZ },
192 { MiscRegNum32(15, 0, 0, 4, 3), MISCREG_RAZ },
193 { MiscRegNum32(15, 0, 0, 4, 4), MISCREG_RAZ },
194 { MiscRegNum32(15, 0, 0, 4, 5), MISCREG_RAZ },
195 { MiscRegNum32(15, 0, 0, 4, 6), MISCREG_RAZ },
196 { MiscRegNum32(15, 0, 0, 4, 7), MISCREG_RAZ },
197 { MiscRegNum32(15, 0, 0, 5, 0), MISCREG_RAZ },
198 { MiscRegNum32(15, 0, 0, 5, 1), MISCREG_RAZ },
199 { MiscRegNum32(15, 0, 0, 5, 2), MISCREG_RAZ },
200 { MiscRegNum32(15, 0, 0, 5, 3), MISCREG_RAZ },
201 { MiscRegNum32(15, 0, 0, 5, 4), MISCREG_RAZ },
202 { MiscRegNum32(15, 0, 0, 5, 5), MISCREG_RAZ },
203 { MiscRegNum32(15, 0, 0, 5, 6), MISCREG_RAZ },
204 { MiscRegNum32(15, 0, 0, 5, 7), MISCREG_RAZ },
205 { MiscRegNum32(15, 0, 0, 6, 0), MISCREG_RAZ },
206 { MiscRegNum32(15, 0, 0, 6, 1), MISCREG_RAZ },
207 { MiscRegNum32(15, 0, 0, 6, 2), MISCREG_RAZ },
208 { MiscRegNum32(15, 0, 0, 6, 3), MISCREG_RAZ },
209 { MiscRegNum32(15, 0, 0, 6, 4), MISCREG_RAZ },
210 { MiscRegNum32(15, 0, 0, 6, 5), MISCREG_RAZ },
211 { MiscRegNum32(15, 0, 0, 6, 6), MISCREG_RAZ },
212 { MiscRegNum32(15, 0, 0, 6, 7), MISCREG_RAZ },
213 { MiscRegNum32(15, 0, 0, 7, 0), MISCREG_RAZ },
214 { MiscRegNum32(15, 0, 0, 7, 1), MISCREG_RAZ },
215 { MiscRegNum32(15, 0, 0, 7, 2), MISCREG_RAZ },
216 { MiscRegNum32(15, 0, 0, 7, 3), MISCREG_RAZ },
217 { MiscRegNum32(15, 0, 0, 7, 4), MISCREG_RAZ },
218 { MiscRegNum32(15, 0, 0, 7, 5), MISCREG_RAZ },
219 { MiscRegNum32(15, 0, 0, 7, 6), MISCREG_RAZ },
220 { MiscRegNum32(15, 0, 0, 7, 7), MISCREG_RAZ },
221 { MiscRegNum32(15, 0, 0, 8, 0), MISCREG_RAZ },
222 { MiscRegNum32(15, 0, 0, 8, 1), MISCREG_RAZ },
223 { MiscRegNum32(15, 0, 0, 8, 2), MISCREG_RAZ },
224 { MiscRegNum32(15, 0, 0, 8, 3), MISCREG_RAZ },
225 { MiscRegNum32(15, 0, 0, 8, 4), MISCREG_RAZ },
226 { MiscRegNum32(15, 0, 0, 8, 5), MISCREG_RAZ },
227 { MiscRegNum32(15, 0, 0, 8, 6), MISCREG_RAZ },
228 { MiscRegNum32(15, 0, 0, 8, 7), MISCREG_RAZ },
229 { MiscRegNum32(15, 0, 0, 9, 0), MISCREG_RAZ },
230 { MiscRegNum32(15, 0, 0, 9, 1), MISCREG_RAZ },
231 { MiscRegNum32(15, 0, 0, 9, 2), MISCREG_RAZ },
232 { MiscRegNum32(15, 0, 0, 9, 3), MISCREG_RAZ },
233 { MiscRegNum32(15, 0, 0, 9, 4), MISCREG_RAZ },
234 { MiscRegNum32(15, 0, 0, 9, 5), MISCREG_RAZ },
235 { MiscRegNum32(15, 0, 0, 9, 6), MISCREG_RAZ },
236 { MiscRegNum32(15, 0, 0, 9, 7), MISCREG_RAZ },
237 { MiscRegNum32(15, 0, 0, 10, 0), MISCREG_RAZ },
238 { MiscRegNum32(15, 0, 0, 10, 1), MISCREG_RAZ },
239 { MiscRegNum32(15, 0, 0, 10, 2), MISCREG_RAZ },
240 { MiscRegNum32(15, 0, 0, 10, 3), MISCREG_RAZ },
241 { MiscRegNum32(15, 0, 0, 10, 4), MISCREG_RAZ },
242 { MiscRegNum32(15, 0, 0, 10, 5), MISCREG_RAZ },
243 { MiscRegNum32(15, 0, 0, 10, 6), MISCREG_RAZ },
244 { MiscRegNum32(15, 0, 0, 10, 7), MISCREG_RAZ },
245 { MiscRegNum32(15, 0, 0, 11, 0), MISCREG_RAZ },
246 { MiscRegNum32(15, 0, 0, 11, 1), MISCREG_RAZ },
247 { MiscRegNum32(15, 0, 0, 11, 2), MISCREG_RAZ },
248 { MiscRegNum32(15, 0, 0, 11, 3), MISCREG_RAZ },
249 { MiscRegNum32(15, 0, 0, 11, 4), MISCREG_RAZ },
250 { MiscRegNum32(15, 0, 0, 11, 5), MISCREG_RAZ },
251 { MiscRegNum32(15, 0, 0, 11, 6), MISCREG_RAZ },
252 { MiscRegNum32(15, 0, 0, 11, 7), MISCREG_RAZ },
253 { MiscRegNum32(15, 0, 0, 12, 0), MISCREG_RAZ },
254 { MiscRegNum32(15, 0, 0, 12, 1), MISCREG_RAZ },
255 { MiscRegNum32(15, 0, 0, 12, 2), MISCREG_RAZ },
256 { MiscRegNum32(15, 0, 0, 12, 3), MISCREG_RAZ },
257 { MiscRegNum32(15, 0, 0, 12, 4), MISCREG_RAZ },
258 { MiscRegNum32(15, 0, 0, 12, 5), MISCREG_RAZ },
259 { MiscRegNum32(15, 0, 0, 12, 6), MISCREG_RAZ },
260 { MiscRegNum32(15, 0, 0, 12, 7), MISCREG_RAZ },
261 { MiscRegNum32(15, 0, 0, 13, 0), MISCREG_RAZ },
262 { MiscRegNum32(15, 0, 0, 13, 1), MISCREG_RAZ },
263 { MiscRegNum32(15, 0, 0, 13, 2), MISCREG_RAZ },
264 { MiscRegNum32(15, 0, 0, 13, 3), MISCREG_RAZ },
265 { MiscRegNum32(15, 0, 0, 13, 4), MISCREG_RAZ },
266 { MiscRegNum32(15, 0, 0, 13, 5), MISCREG_RAZ },
267 { MiscRegNum32(15, 0, 0, 13, 6), MISCREG_RAZ },
268 { MiscRegNum32(15, 0, 0, 13, 7), MISCREG_RAZ },
269 { MiscRegNum32(15, 0, 0, 14, 0), MISCREG_RAZ },
270 { MiscRegNum32(15, 0, 0, 14, 1), MISCREG_RAZ },
271 { MiscRegNum32(15, 0, 0, 14, 2), MISCREG_RAZ },
272 { MiscRegNum32(15, 0, 0, 14, 3), MISCREG_RAZ },
273 { MiscRegNum32(15, 0, 0, 14, 4), MISCREG_RAZ },
274 { MiscRegNum32(15, 0, 0, 14, 5), MISCREG_RAZ },
275 { MiscRegNum32(15, 0, 0, 14, 6), MISCREG_RAZ },
276 { MiscRegNum32(15, 0, 0, 14, 7), MISCREG_RAZ },
277 { MiscRegNum32(15, 0, 0, 15, 0), MISCREG_RAZ },
278 { MiscRegNum32(15, 0, 0, 15, 1), MISCREG_RAZ },
279 { MiscRegNum32(15, 0, 0, 15, 2), MISCREG_RAZ },
280 { MiscRegNum32(15, 0, 0, 15, 3), MISCREG_RAZ },
281 { MiscRegNum32(15, 0, 0, 15, 4), MISCREG_RAZ },
282 { MiscRegNum32(15, 0, 0, 15, 5), MISCREG_RAZ },
283 { MiscRegNum32(15, 0, 0, 15, 6), MISCREG_RAZ },
284 { MiscRegNum32(15, 0, 0, 15, 7), MISCREG_RAZ },
285 { MiscRegNum32(15, 0, 1, 0, 0), MISCREG_SCTLR },
286 { MiscRegNum32(15, 0, 1, 0, 1), MISCREG_ACTLR },
287 { MiscRegNum32(15, 0, 1, 0, 2), MISCREG_CPACR },
288 { MiscRegNum32(15, 0, 1, 1, 0), MISCREG_SCR },
289 { MiscRegNum32(15, 0, 1, 1, 1), MISCREG_SDER },
290 { MiscRegNum32(15, 0, 1, 1, 2), MISCREG_NSACR },
291 { MiscRegNum32(15, 0, 1, 3, 1), MISCREG_SDCR },
292 { MiscRegNum32(15, 0, 2, 0, 0), MISCREG_TTBR0 },
293 { MiscRegNum32(15, 0, 2, 0, 1), MISCREG_TTBR1 },
294 { MiscRegNum32(15, 0, 2, 0, 2), MISCREG_TTBCR },
295 { MiscRegNum32(15, 0, 3, 0, 0), MISCREG_DACR },
296 { MiscRegNum32(15, 0, 4, 6, 0), MISCREG_ICC_PMR },
297 { MiscRegNum32(15, 0, 5, 0, 0), MISCREG_DFSR },
298 { MiscRegNum32(15, 0, 5, 0, 1), MISCREG_IFSR },
299 { MiscRegNum32(15, 0, 5, 1, 0), MISCREG_ADFSR },
300 { MiscRegNum32(15, 0, 5, 1, 1), MISCREG_AIFSR },
301 { MiscRegNum32(15, 0, 6, 0, 0), MISCREG_DFAR },
302 { MiscRegNum32(15, 0, 6, 0, 2), MISCREG_IFAR },
303 { MiscRegNum32(15, 0, 7, 0, 4), MISCREG_NOP },
304 { MiscRegNum32(15, 0, 7, 1, 0), MISCREG_ICIALLUIS },
305 { MiscRegNum32(15, 0, 7, 1, 6), MISCREG_BPIALLIS },
306 { MiscRegNum32(15, 0, 7, 2, 7), MISCREG_DBGDEVID0 },
307 { MiscRegNum32(15, 0, 7, 4, 0), MISCREG_PAR },
308 { MiscRegNum32(15, 0, 7, 5, 0), MISCREG_ICIALLU },
309 { MiscRegNum32(15, 0, 7, 5, 1), MISCREG_ICIMVAU },
310 { MiscRegNum32(15, 0, 7, 5, 4), MISCREG_CP15ISB },
311 { MiscRegNum32(15, 0, 7, 5, 6), MISCREG_BPIALL },
312 { MiscRegNum32(15, 0, 7, 5, 7), MISCREG_BPIMVA },
313 { MiscRegNum32(15, 0, 7, 6, 1), MISCREG_DCIMVAC },
314 { MiscRegNum32(15, 0, 7, 6, 2), MISCREG_DCISW },
315 { MiscRegNum32(15, 0, 7, 8, 0), MISCREG_ATS1CPR },
316 { MiscRegNum32(15, 0, 7, 8, 1), MISCREG_ATS1CPW },
317 { MiscRegNum32(15, 0, 7, 8, 2), MISCREG_ATS1CUR },
318 { MiscRegNum32(15, 0, 7, 8, 3), MISCREG_ATS1CUW },
319 { MiscRegNum32(15, 0, 7, 8, 4), MISCREG_ATS12NSOPR },
320 { MiscRegNum32(15, 0, 7, 8, 5), MISCREG_ATS12NSOPW },
321 { MiscRegNum32(15, 0, 7, 8, 6), MISCREG_ATS12NSOUR },
322 { MiscRegNum32(15, 0, 7, 8, 7), MISCREG_ATS12NSOUW },
323 { MiscRegNum32(15, 0, 7, 10, 1), MISCREG_DCCMVAC },
324 { MiscRegNum32(15, 0, 7, 10, 2), MISCREG_DCCSW },
325 { MiscRegNum32(15, 0, 7, 10, 4), MISCREG_CP15DSB },
326 { MiscRegNum32(15, 0, 7, 10, 5), MISCREG_CP15DMB },
327 { MiscRegNum32(15, 0, 7, 11, 1), MISCREG_DCCMVAU },
328 { MiscRegNum32(15, 0, 7, 13, 1), MISCREG_NOP },
329 { MiscRegNum32(15, 0, 7, 14, 1), MISCREG_DCCIMVAC },
330 { MiscRegNum32(15, 0, 7, 14, 2), MISCREG_DCCISW },
331 { MiscRegNum32(15, 0, 8, 3, 0), MISCREG_TLBIALLIS },
332 { MiscRegNum32(15, 0, 8, 3, 1), MISCREG_TLBIMVAIS },
333 { MiscRegNum32(15, 0, 8, 3, 2), MISCREG_TLBIASIDIS },
334 { MiscRegNum32(15, 0, 8, 3, 3), MISCREG_TLBIMVAAIS },
335 { MiscRegNum32(15, 0, 8, 3, 5), MISCREG_TLBIMVALIS },
336 { MiscRegNum32(15, 0, 8, 3, 7), MISCREG_TLBIMVAALIS },
337 { MiscRegNum32(15, 0, 8, 5, 0), MISCREG_ITLBIALL },
338 { MiscRegNum32(15, 0, 8, 5, 1), MISCREG_ITLBIMVA },
339 { MiscRegNum32(15, 0, 8, 5, 2), MISCREG_ITLBIASID },
340 { MiscRegNum32(15, 0, 8, 6, 0), MISCREG_DTLBIALL },
341 { MiscRegNum32(15, 0, 8, 6, 1), MISCREG_DTLBIMVA },
342 { MiscRegNum32(15, 0, 8, 6, 2), MISCREG_DTLBIASID },
343 { MiscRegNum32(15, 0, 8, 7, 0), MISCREG_TLBIALL },
344 { MiscRegNum32(15, 0, 8, 7, 1), MISCREG_TLBIMVA },
345 { MiscRegNum32(15, 0, 8, 7, 2), MISCREG_TLBIASID },
346 { MiscRegNum32(15, 0, 8, 7, 3), MISCREG_TLBIMVAA },
347 { MiscRegNum32(15, 0, 8, 7, 5), MISCREG_TLBIMVAL },
348 { MiscRegNum32(15, 0, 8, 7, 7), MISCREG_TLBIMVAAL },
349 { MiscRegNum32(15, 0, 9, 12, 0), MISCREG_PMCR },
350 { MiscRegNum32(15, 0, 9, 12, 1), MISCREG_PMCNTENSET },
351 { MiscRegNum32(15, 0, 9, 12, 2), MISCREG_PMCNTENCLR },
352 { MiscRegNum32(15, 0, 9, 12, 3), MISCREG_PMOVSR },
353 { MiscRegNum32(15, 0, 9, 12, 4), MISCREG_PMSWINC },
354 { MiscRegNum32(15, 0, 9, 12, 5), MISCREG_PMSELR },
355 { MiscRegNum32(15, 0, 9, 12, 6), MISCREG_PMCEID0 },
356 { MiscRegNum32(15, 0, 9, 12, 7), MISCREG_PMCEID1 },
357 { MiscRegNum32(15, 0, 9, 13, 0), MISCREG_PMCCNTR },
358 { MiscRegNum32(15, 0, 9, 13, 1), MISCREG_PMXEVTYPER_PMCCFILTR },
359 { MiscRegNum32(15, 0, 9, 13, 2), MISCREG_PMXEVCNTR },
360 { MiscRegNum32(15, 0, 9, 14, 0), MISCREG_PMUSERENR },
361 { MiscRegNum32(15, 0, 9, 14, 1), MISCREG_PMINTENSET },
362 { MiscRegNum32(15, 0, 9, 14, 2), MISCREG_PMINTENCLR },
363 { MiscRegNum32(15, 0, 9, 14, 3), MISCREG_PMOVSSET },
364 { MiscRegNum32(15, 0, 10, 2, 0), MISCREG_PRRR_MAIR0 },
365 { MiscRegNum32(15, 0, 10, 2, 1), MISCREG_NMRR_MAIR1 },
366 { MiscRegNum32(15, 0, 10, 3, 0), MISCREG_AMAIR0 },
367 { MiscRegNum32(15, 0, 10, 3, 1), MISCREG_AMAIR1 },
368 { MiscRegNum32(15, 0, 12, 0, 0), MISCREG_VBAR },
369 { MiscRegNum32(15, 0, 12, 0, 1), MISCREG_MVBAR },
370 { MiscRegNum32(15, 0, 12, 1, 0), MISCREG_ISR },
371 { MiscRegNum32(15, 0, 12, 8, 0), MISCREG_ICC_IAR0 },
372 { MiscRegNum32(15, 0, 12, 8, 1), MISCREG_ICC_EOIR0 },
373 { MiscRegNum32(15, 0, 12, 8, 2), MISCREG_ICC_HPPIR0 },
374 { MiscRegNum32(15, 0, 12, 8, 3), MISCREG_ICC_BPR0 },
375 { MiscRegNum32(15, 0, 12, 8, 4), MISCREG_ICC_AP0R0 },
376 { MiscRegNum32(15, 0, 12, 8, 5), MISCREG_ICC_AP0R1 },
377 { MiscRegNum32(15, 0, 12, 8, 6), MISCREG_ICC_AP0R2 },
378 { MiscRegNum32(15, 0, 12, 8, 7), MISCREG_ICC_AP0R3 },
379 { MiscRegNum32(15, 0, 12, 9, 0), MISCREG_ICC_AP1R0 },
380 { MiscRegNum32(15, 0, 12, 9, 1), MISCREG_ICC_AP1R1 },
381 { MiscRegNum32(15, 0, 12, 9, 2), MISCREG_ICC_AP1R2 },
382 { MiscRegNum32(15, 0, 12, 9, 3), MISCREG_ICC_AP1R3 },
383 { MiscRegNum32(15, 0, 12, 11, 1), MISCREG_ICC_DIR },
384 { MiscRegNum32(15, 0, 12, 11, 3), MISCREG_ICC_RPR },
385 { MiscRegNum32(15, 0, 12, 12, 0), MISCREG_ICC_IAR1 },
386 { MiscRegNum32(15, 0, 12, 12, 1), MISCREG_ICC_EOIR1 },
387 { MiscRegNum32(15, 0, 12, 12, 2), MISCREG_ICC_HPPIR1 },
388 { MiscRegNum32(15, 0, 12, 12, 3), MISCREG_ICC_BPR1 },
389 { MiscRegNum32(15, 0, 12, 12, 4), MISCREG_ICC_CTLR },
390 { MiscRegNum32(15, 0, 12, 12, 5), MISCREG_ICC_SRE },
391 { MiscRegNum32(15, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0 },
392 { MiscRegNum32(15, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1 },
393 { MiscRegNum32(15, 0, 13, 0, 0), MISCREG_FCSEIDR },
394 { MiscRegNum32(15, 0, 13, 0, 1), MISCREG_CONTEXTIDR },
395 { MiscRegNum32(15, 0, 13, 0, 2), MISCREG_TPIDRURW },
396 { MiscRegNum32(15, 0, 13, 0, 3), MISCREG_TPIDRURO },
397 { MiscRegNum32(15, 0, 13, 0, 4), MISCREG_TPIDRPRW },
398 { MiscRegNum32(15, 0, 14, 0, 0), MISCREG_CNTFRQ },
399 { MiscRegNum32(15, 0, 14, 1, 0), MISCREG_CNTKCTL },
400 { MiscRegNum32(15, 0, 14, 2, 0), MISCREG_CNTP_TVAL },
401 { MiscRegNum32(15, 0, 14, 2, 1), MISCREG_CNTP_CTL },
402 { MiscRegNum32(15, 0, 14, 3, 0), MISCREG_CNTV_TVAL },
403 { MiscRegNum32(15, 0, 14, 3, 1), MISCREG_CNTV_CTL },
404 { MiscRegNum32(15, 0, 14, 8, 0), MISCREG_PMEVCNTR0 },
405 { MiscRegNum32(15, 0, 14, 8, 1), MISCREG_PMEVCNTR1 },
406 { MiscRegNum32(15, 0, 14, 8, 2), MISCREG_PMEVCNTR2 },
407 { MiscRegNum32(15, 0, 14, 8, 3), MISCREG_PMEVCNTR3 },
408 { MiscRegNum32(15, 0, 14, 8, 4), MISCREG_PMEVCNTR4 },
409 { MiscRegNum32(15, 0, 14, 8, 5), MISCREG_PMEVCNTR5 },
410 { MiscRegNum32(15, 0, 14, 12, 0), MISCREG_PMEVTYPER0 },
411 { MiscRegNum32(15, 0, 14, 12, 1), MISCREG_PMEVTYPER1 },
412 { MiscRegNum32(15, 0, 14, 12, 2), MISCREG_PMEVTYPER2 },
413 { MiscRegNum32(15, 0, 14, 12, 3), MISCREG_PMEVTYPER3 },
414 { MiscRegNum32(15, 0, 14, 12, 4), MISCREG_PMEVTYPER4 },
415 { MiscRegNum32(15, 0, 14, 12, 5), MISCREG_PMEVTYPER5 },
416 { MiscRegNum32(15, 0, 14, 15, 7), MISCREG_PMCCFILTR },
417 { MiscRegNum32(15, 1, 0, 0, 0), MISCREG_CCSIDR },
418 { MiscRegNum32(15, 1, 0, 0, 1), MISCREG_CLIDR },
419 { MiscRegNum32(15, 1, 0, 0, 7), MISCREG_AIDR },
420 { MiscRegNum32(15, 2, 0, 0, 0), MISCREG_CSSELR },
421 { MiscRegNum32(15, 4, 0, 0, 0), MISCREG_VPIDR },
422 { MiscRegNum32(15, 4, 0, 0, 5), MISCREG_VMPIDR },
423 { MiscRegNum32(15, 4, 1, 0, 0), MISCREG_HSCTLR },
424 { MiscRegNum32(15, 4, 1, 0, 1), MISCREG_HACTLR },
425 { MiscRegNum32(15, 4, 1, 1, 0), MISCREG_HCR },
426 { MiscRegNum32(15, 4, 1, 1, 1), MISCREG_HDCR },
427 { MiscRegNum32(15, 4, 1, 1, 2), MISCREG_HCPTR },
428 { MiscRegNum32(15, 4, 1, 1, 3), MISCREG_HSTR },
429 { MiscRegNum32(15, 4, 1, 1, 4), MISCREG_HCR2 },
430 { MiscRegNum32(15, 4, 1, 1, 7), MISCREG_HACR },
431 { MiscRegNum32(15, 4, 2, 0, 2), MISCREG_HTCR },
432 { MiscRegNum32(15, 4, 2, 1, 2), MISCREG_VTCR },
433 { MiscRegNum32(15, 4, 5, 1, 0), MISCREG_HADFSR },
434 { MiscRegNum32(15, 4, 5, 1, 1), MISCREG_HAIFSR },
435 { MiscRegNum32(15, 4, 5, 2, 0), MISCREG_HSR },
436 { MiscRegNum32(15, 4, 6, 0, 0), MISCREG_HDFAR },
437 { MiscRegNum32(15, 4, 6, 0, 2), MISCREG_HIFAR },
438 { MiscRegNum32(15, 4, 6, 0, 4), MISCREG_HPFAR },
439 { MiscRegNum32(15, 4, 7, 8, 0), MISCREG_ATS1HR },
440 { MiscRegNum32(15, 4, 7, 8, 1), MISCREG_ATS1HW },
441 { MiscRegNum32(15, 4, 8, 0, 1), MISCREG_TLBIIPAS2IS },
442 { MiscRegNum32(15, 4, 8, 0, 5), MISCREG_TLBIIPAS2LIS },
443 { MiscRegNum32(15, 4, 8, 3, 0), MISCREG_TLBIALLHIS },
444 { MiscRegNum32(15, 4, 8, 3, 1), MISCREG_TLBIMVAHIS },
445 { MiscRegNum32(15, 4, 8, 3, 4), MISCREG_TLBIALLNSNHIS },
446 { MiscRegNum32(15, 4, 8, 3, 5), MISCREG_TLBIMVALHIS },
447 { MiscRegNum32(15, 4, 8, 4, 1), MISCREG_TLBIIPAS2 },
448 { MiscRegNum32(15, 4, 8, 4, 5), MISCREG_TLBIIPAS2L },
449 { MiscRegNum32(15, 4, 8, 7, 0), MISCREG_TLBIALLH },
450 { MiscRegNum32(15, 4, 8, 7, 1), MISCREG_TLBIMVAH },
451 { MiscRegNum32(15, 4, 8, 7, 4), MISCREG_TLBIALLNSNH },
452 { MiscRegNum32(15, 4, 8, 7, 5), MISCREG_TLBIMVALH },
453 { MiscRegNum32(15, 4, 10, 2, 0), MISCREG_HMAIR0 },
454 { MiscRegNum32(15, 4, 10, 2, 1), MISCREG_HMAIR1 },
455 { MiscRegNum32(15, 4, 10, 3, 0), MISCREG_HAMAIR0 },
456 { MiscRegNum32(15, 4, 10, 3, 1), MISCREG_HAMAIR1 },
457 { MiscRegNum32(15, 4, 12, 0, 0), MISCREG_HVBAR },
458 { MiscRegNum32(15, 4, 12, 8, 0), MISCREG_ICH_AP0R0 },
459 { MiscRegNum32(15, 4, 12, 8, 1), MISCREG_ICH_AP0R1 },
460 { MiscRegNum32(15, 4, 12, 8, 2), MISCREG_ICH_AP0R2 },
461 { MiscRegNum32(15, 4, 12, 8, 3), MISCREG_ICH_AP0R3 },
462 { MiscRegNum32(15, 4, 12, 9, 0), MISCREG_ICH_AP1R0 },
463 { MiscRegNum32(15, 4, 12, 9, 1), MISCREG_ICH_AP1R1 },
464 { MiscRegNum32(15, 4, 12, 9, 2), MISCREG_ICH_AP1R2 },
465 { MiscRegNum32(15, 4, 12, 9, 3), MISCREG_ICH_AP1R3 },
466 { MiscRegNum32(15, 4, 12, 9, 5), MISCREG_ICC_HSRE },
467 { MiscRegNum32(15, 4, 12, 11, 0), MISCREG_ICH_HCR },
468 { MiscRegNum32(15, 4, 12, 11, 1), MISCREG_ICH_VTR },
469 { MiscRegNum32(15, 4, 12, 11, 2), MISCREG_ICH_MISR },
470 { MiscRegNum32(15, 4, 12, 11, 3), MISCREG_ICH_EISR },
471 { MiscRegNum32(15, 4, 12, 11, 5), MISCREG_ICH_ELRSR },
472 { MiscRegNum32(15, 4, 12, 11, 7), MISCREG_ICH_VMCR },
473 { MiscRegNum32(15, 4, 12, 12, 0), MISCREG_ICH_LR0 },
474 { MiscRegNum32(15, 4, 12, 12, 1), MISCREG_ICH_LR1 },
475 { MiscRegNum32(15, 4, 12, 12, 2), MISCREG_ICH_LR2 },
476 { MiscRegNum32(15, 4, 12, 12, 3), MISCREG_ICH_LR3 },
477 { MiscRegNum32(15, 4, 12, 12, 4), MISCREG_ICH_LR4 },
478 { MiscRegNum32(15, 4, 12, 12, 5), MISCREG_ICH_LR5 },
479 { MiscRegNum32(15, 4, 12, 12, 6), MISCREG_ICH_LR6 },
480 { MiscRegNum32(15, 4, 12, 12, 7), MISCREG_ICH_LR7 },
481 { MiscRegNum32(15, 4, 12, 13, 0), MISCREG_ICH_LR8 },
482 { MiscRegNum32(15, 4, 12, 13, 1), MISCREG_ICH_LR9 },
483 { MiscRegNum32(15, 4, 12, 13, 2), MISCREG_ICH_LR10 },
484 { MiscRegNum32(15, 4, 12, 13, 3), MISCREG_ICH_LR11 },
485 { MiscRegNum32(15, 4, 12, 13, 4), MISCREG_ICH_LR12 },
486 { MiscRegNum32(15, 4, 12, 13, 5), MISCREG_ICH_LR13 },
487 { MiscRegNum32(15, 4, 12, 13, 6), MISCREG_ICH_LR14 },
488 { MiscRegNum32(15, 4, 12, 13, 7), MISCREG_ICH_LR15 },
489 { MiscRegNum32(15, 4, 12, 14, 0), MISCREG_ICH_LRC0 },
490 { MiscRegNum32(15, 4, 12, 14, 1), MISCREG_ICH_LRC1 },
491 { MiscRegNum32(15, 4, 12, 14, 2), MISCREG_ICH_LRC2 },
492 { MiscRegNum32(15, 4, 12, 14, 3), MISCREG_ICH_LRC3 },
493 { MiscRegNum32(15, 4, 12, 14, 4), MISCREG_ICH_LRC4 },
494 { MiscRegNum32(15, 4, 12, 14, 5), MISCREG_ICH_LRC5 },
495 { MiscRegNum32(15, 4, 12, 14, 6), MISCREG_ICH_LRC6 },
496 { MiscRegNum32(15, 4, 12, 14, 7), MISCREG_ICH_LRC7 },
497 { MiscRegNum32(15, 4, 12, 15, 0), MISCREG_ICH_LRC8 },
498 { MiscRegNum32(15, 4, 12, 15, 1), MISCREG_ICH_LRC9 },
499 { MiscRegNum32(15, 4, 12, 15, 2), MISCREG_ICH_LRC10 },
500 { MiscRegNum32(15, 4, 12, 15, 3), MISCREG_ICH_LRC11 },
501 { MiscRegNum32(15, 4, 12, 15, 4), MISCREG_ICH_LRC12 },
502 { MiscRegNum32(15, 4, 12, 15, 5), MISCREG_ICH_LRC13 },
503 { MiscRegNum32(15, 4, 12, 15, 6), MISCREG_ICH_LRC14 },
504 { MiscRegNum32(15, 4, 12, 15, 7), MISCREG_ICH_LRC15 },
505 { MiscRegNum32(15, 4, 13, 0, 2), MISCREG_HTPIDR },
506 { MiscRegNum32(15, 4, 14, 1, 0), MISCREG_CNTHCTL },
507 { MiscRegNum32(15, 4, 14, 2, 0), MISCREG_CNTHP_TVAL },
508 { MiscRegNum32(15, 4, 14, 2, 1), MISCREG_CNTHP_CTL },
509 { MiscRegNum32(15, 6, 12, 12, 4), MISCREG_ICC_MCTLR },
510 { MiscRegNum32(15, 6, 12, 12, 5), MISCREG_ICC_MSRE },
511 { MiscRegNum32(15, 6, 12, 12, 7), MISCREG_ICC_MGRPEN1 },
512 // MCRR/MRRC regs
513 { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 },
514 { MiscRegNum32(15, 0, 7), MISCREG_PAR },
515 { MiscRegNum32(15, 0, 9), MISCREG_PMCCNTR }, // ARMv8 AArch32 register
516 { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R },
517 { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT },
518 { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },
519 { MiscRegNum32(15, 1, 2), MISCREG_TTBR1 },
520 { MiscRegNum32(15, 1, 12), MISCREG_ICC_ASGI1R },
521 { MiscRegNum32(15, 1, 14), MISCREG_CNTVCT },
522 { MiscRegNum32(15, 1, 15), MISCREG_L2MERRSR },
523 { MiscRegNum32(15, 2, 12), MISCREG_ICC_SGI0R },
524 { MiscRegNum32(15, 2, 14), MISCREG_CNTP_CVAL },
525 { MiscRegNum32(15, 3, 14), MISCREG_CNTV_CVAL },
526 { MiscRegNum32(15, 4, 2), MISCREG_HTTBR },
527 { MiscRegNum32(15, 4, 14), MISCREG_CNTVOFF },
528 { MiscRegNum32(15, 6, 2), MISCREG_VTTBR },
529 { MiscRegNum32(15, 6, 14), MISCREG_CNTHP_CVAL },
530};
531
532}
533
534MiscRegIndex
535decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
536{
537 MiscRegNum32 cop_reg(14, opc1, crn, crm, opc2);
538 auto it = miscRegNum32ToIdx.find(cop_reg);
539 if (it != miscRegNum32ToIdx.end()) {
540 return it->second;
541 } else {
542 warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
543 crn, opc1, crm, opc2);
544 return MISCREG_UNKNOWN;
545 }
546}
547
548MiscRegIndex
549decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
550{
551 MiscRegNum32 cop_reg(15, opc1, crn, crm, opc2);
552 auto it = miscRegNum32ToIdx.find(cop_reg);
553 if (it != miscRegNum32ToIdx.end()) {
554 return it->second;
555 } else {
556 if ((crn == 15) ||
557 (crn == 9 && (crm <= 2 || crm >= 5)) ||
558 (crn == 10 && opc1 == 0 && crm <= 1) ||
559 (crn == 11 && opc1 <= 7 && (crm <= 8 || crm ==15))) {
560 return MISCREG_IMPDEF_UNIMPL;
561 } else {
562 return MISCREG_UNKNOWN;
563 }
564 }
565}
566
567MiscRegIndex
568decodeCP15Reg64(unsigned crm, unsigned opc1)
569{
570 MiscRegNum32 cop_reg(15, opc1, crm);
571 auto it = miscRegNum32ToIdx.find(cop_reg);
572 if (it != miscRegNum32ToIdx.end()) {
573 return it->second;
574 } else {
575 return MISCREG_UNKNOWN;
576 }
577}
578
579std::tuple<bool, bool>
580canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
581{
582 bool secure = !scr.ns;
583 bool can_read = false;
584 bool undefined = false;
585 auto& miscreg_info = lookUpMiscReg[reg].info;
586
587 switch (cpsr.mode) {
588 case MODE_USER:
589 can_read = secure ? miscreg_info[MISCREG_USR_S_RD] :
590 miscreg_info[MISCREG_USR_NS_RD];
591 break;
592 case MODE_FIQ:
593 case MODE_IRQ:
594 case MODE_SVC:
595 case MODE_ABORT:
596 case MODE_UNDEFINED:
597 case MODE_SYSTEM:
598 can_read = secure ? miscreg_info[MISCREG_PRI_S_RD] :
599 miscreg_info[MISCREG_PRI_NS_RD];
600 break;
601 case MODE_MON:
602 can_read = secure ? miscreg_info[MISCREG_MON_NS0_RD] :
603 miscreg_info[MISCREG_MON_NS1_RD];
604 break;
605 case MODE_HYP:
606 can_read = miscreg_info[MISCREG_HYP_NS_RD];
607 break;
608 default:
609 undefined = true;
610 }
611
612 switch (reg) {
613 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
614 if (!undefined)
615 undefined = AArch32isUndefinedGenericTimer(reg, tc);
616 break;
617 default:
618 break;
619 }
620
621 // can't do permissions checkes on the root of a banked pair of regs
622 assert(!miscreg_info[MISCREG_BANKED]);
623 return std::make_tuple(can_read, undefined);
624}
625
626std::tuple<bool, bool>
627canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
628{
629 bool secure = !scr.ns;
630 bool can_write = false;
631 bool undefined = false;
632 const auto& miscreg_info = lookUpMiscReg[reg].info;
633
634 switch (cpsr.mode) {
635 case MODE_USER:
636 can_write = secure ? miscreg_info[MISCREG_USR_S_WR] :
637 miscreg_info[MISCREG_USR_NS_WR];
638 break;
639 case MODE_FIQ:
640 case MODE_IRQ:
641 case MODE_SVC:
642 case MODE_ABORT:
643 case MODE_UNDEFINED:
644 case MODE_SYSTEM:
645 can_write = secure ? miscreg_info[MISCREG_PRI_S_WR] :
646 miscreg_info[MISCREG_PRI_NS_WR];
647 break;
648 case MODE_MON:
649 can_write = secure ? miscreg_info[MISCREG_MON_NS0_WR] :
650 miscreg_info[MISCREG_MON_NS1_WR];
651 break;
652 case MODE_HYP:
653 can_write = miscreg_info[MISCREG_HYP_NS_WR];
654 break;
655 default:
656 undefined = true;
657 }
658
659 switch (reg) {
660 case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
661 if (!undefined)
662 undefined = AArch32isUndefinedGenericTimer(reg, tc);
663 break;
664 default:
665 break;
666 }
667
668 // can't do permissions checkes on the root of a banked pair of regs
669 assert(!miscreg_info[MISCREG_BANKED]);
670 return std::make_tuple(can_write, undefined);
671}
672
673bool
674AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
675{
676 if (currEL(tc) == EL0 && ELIs32(tc, EL1)) {
677 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
678 bool trap_cond = condGenericTimerSystemAccessTrapEL1(reg, tc);
679 if (trap_cond && (!EL2Enabled(tc) || !hcr.tge))
680 return true;
681 }
682 return false;
683}
684
685int
686snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
687{
688 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
689 return snsBankedIndex(reg, tc, scr.ns);
690}
691
692int
693snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
694{
695 int reg_as_int = static_cast<int>(reg);
696 if (lookUpMiscReg[reg].info[MISCREG_BANKED]) {
697 reg_as_int += (ArmSystem::haveEL(tc, EL3) &&
698 !ArmSystem::highestELIs64(tc) && !ns) ? 2 : 1;
699 }
700 return reg_as_int;
701}
702
703int
704snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
705{
706 auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
707 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
708 return isa->snsBankedIndex64(reg, scr.ns);
709}
710
719int unflattenResultMiscReg[NUM_MISCREGS];
720
721void
722preUnflattenMiscReg()
723{
724 int reg = -1;
725 for (int i = 0 ; i < NUM_MISCREGS; i++){
726 if (lookUpMiscReg[i].info[MISCREG_BANKED])
727 reg = i;
728 if (lookUpMiscReg[i].info[MISCREG_BANKED_CHILD])
729 unflattenResultMiscReg[i] = reg;
730 else
731 unflattenResultMiscReg[i] = i;
732 // if this assert fails, no parent was found, and something is broken
733 assert(unflattenResultMiscReg[i] > -1);
734 }
735}
736
737int
738unflattenMiscReg(int reg)
739{
740 return unflattenResultMiscReg[reg];
741}
742
743Fault
744checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr,
745 ThreadContext *tc, const MiscRegOp64 &inst)
746{
747 return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
748}
749
750std::vector<struct MiscRegLUTEntry> lookUpMiscReg(NUM_MISCREGS);
751
752namespace {
753// The map is translating a MiscRegIndex into AArch64 system register
754// numbers (op0, op1, crn, crm, op2)
755std::unordered_map<MiscRegIndex, MiscRegNum64> idxToMiscRegNum;
756
757// The map is translating AArch64 system register numbers
758// (op0, op1, crn, crm, op2) into a MiscRegIndex
759std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
760 { MiscRegNum64(1, 0, 7, 1, 0), MISCREG_IC_IALLUIS },
761 { MiscRegNum64(1, 0, 7, 5, 0), MISCREG_IC_IALLU },
762 { MiscRegNum64(1, 0, 7, 6, 1), MISCREG_DC_IVAC_Xt },
763 { MiscRegNum64(1, 0, 7, 6, 2), MISCREG_DC_ISW_Xt },
764 { MiscRegNum64(1, 0, 7, 8, 0), MISCREG_AT_S1E1R_Xt },
765 { MiscRegNum64(1, 0, 7, 8, 1), MISCREG_AT_S1E1W_Xt },
766 { MiscRegNum64(1, 0, 7, 8, 2), MISCREG_AT_S1E0R_Xt },
767 { MiscRegNum64(1, 0, 7, 8, 3), MISCREG_AT_S1E0W_Xt },
768 { MiscRegNum64(1, 0, 7, 10, 2), MISCREG_DC_CSW_Xt },
769 { MiscRegNum64(1, 0, 7, 14, 2), MISCREG_DC_CISW_Xt },
770 { MiscRegNum64(1, 0, 8, 1, 0), MISCREG_TLBI_VMALLE1OS },
771 { MiscRegNum64(1, 0, 8, 1, 1), MISCREG_TLBI_VAE1OS },
772 { MiscRegNum64(1, 0, 8, 1, 2), MISCREG_TLBI_ASIDE1OS },
773 { MiscRegNum64(1, 0, 8, 1, 3), MISCREG_TLBI_VAAE1OS },
774 { MiscRegNum64(1, 0, 8, 1, 5), MISCREG_TLBI_VALE1OS },
775 { MiscRegNum64(1, 0, 8, 1, 7), MISCREG_TLBI_VAALE1OS },
776 { MiscRegNum64(1, 0, 8, 2, 1), MISCREG_TLBI_RVAE1IS },
777 { MiscRegNum64(1, 0, 8, 2, 3), MISCREG_TLBI_RVAAE1IS },
778 { MiscRegNum64(1, 0, 8, 2, 5), MISCREG_TLBI_RVALE1IS },
779 { MiscRegNum64(1, 0, 8, 2, 7), MISCREG_TLBI_RVAALE1IS },
780 { MiscRegNum64(1, 0, 8, 3, 0), MISCREG_TLBI_VMALLE1IS },
781 { MiscRegNum64(1, 0, 8, 3, 1), MISCREG_TLBI_VAE1IS },
782 { MiscRegNum64(1, 0, 8, 3, 2), MISCREG_TLBI_ASIDE1IS },
783 { MiscRegNum64(1, 0, 8, 3, 3), MISCREG_TLBI_VAAE1IS },
784 { MiscRegNum64(1, 0, 8, 3, 5), MISCREG_TLBI_VALE1IS },
785 { MiscRegNum64(1, 0, 8, 3, 7), MISCREG_TLBI_VAALE1IS },
786 { MiscRegNum64(1, 0, 8, 5, 1), MISCREG_TLBI_RVAE1OS },
787 { MiscRegNum64(1, 0, 8, 5, 3), MISCREG_TLBI_RVAAE1OS },
788 { MiscRegNum64(1, 0, 8, 5, 5), MISCREG_TLBI_RVALE1OS },
789 { MiscRegNum64(1, 0, 8, 5, 7), MISCREG_TLBI_RVAALE1OS },
790 { MiscRegNum64(1, 0, 8, 6, 1), MISCREG_TLBI_RVAE1 },
791 { MiscRegNum64(1, 0, 8, 6, 3), MISCREG_TLBI_RVAAE1 },
792 { MiscRegNum64(1, 0, 8, 6, 5), MISCREG_TLBI_RVALE1 },
793 { MiscRegNum64(1, 0, 8, 6, 7), MISCREG_TLBI_RVAALE1 },
794 { MiscRegNum64(1, 0, 8, 7, 0), MISCREG_TLBI_VMALLE1 },
795 { MiscRegNum64(1, 0, 8, 7, 1), MISCREG_TLBI_VAE1 },
796 { MiscRegNum64(1, 0, 8, 7, 2), MISCREG_TLBI_ASIDE1 },
797 { MiscRegNum64(1, 0, 8, 7, 3), MISCREG_TLBI_VAAE1 },
798 { MiscRegNum64(1, 0, 8, 7, 5), MISCREG_TLBI_VALE1 },
799 { MiscRegNum64(1, 0, 8, 7, 7), MISCREG_TLBI_VAALE1 },
800 { MiscRegNum64(1, 0, 9, 1, 0), MISCREG_TLBI_VMALLE1OSNXS },
801 { MiscRegNum64(1, 0, 9, 1, 1), MISCREG_TLBI_VAE1OSNXS },
802 { MiscRegNum64(1, 0, 9, 1, 2), MISCREG_TLBI_ASIDE1OSNXS },
803 { MiscRegNum64(1, 0, 9, 1, 3), MISCREG_TLBI_VAAE1OSNXS },
804 { MiscRegNum64(1, 0, 9, 1, 5), MISCREG_TLBI_VALE1OSNXS },
805 { MiscRegNum64(1, 0, 9, 1, 7), MISCREG_TLBI_VAALE1OSNXS },
806 { MiscRegNum64(1, 0, 9, 2, 1), MISCREG_TLBI_RVAE1ISNXS },
807 { MiscRegNum64(1, 0, 9, 2, 3), MISCREG_TLBI_RVAAE1ISNXS },
808 { MiscRegNum64(1, 0, 9, 2, 5), MISCREG_TLBI_RVALE1ISNXS },
809 { MiscRegNum64(1, 0, 9, 2, 7), MISCREG_TLBI_RVAALE1ISNXS },
810 { MiscRegNum64(1, 0, 9, 3, 0), MISCREG_TLBI_VMALLE1ISNXS },
811 { MiscRegNum64(1, 0, 9, 3, 1), MISCREG_TLBI_VAE1ISNXS },
812 { MiscRegNum64(1, 0, 9, 3, 2), MISCREG_TLBI_ASIDE1ISNXS },
813 { MiscRegNum64(1, 0, 9, 3, 3), MISCREG_TLBI_VAAE1ISNXS },
814 { MiscRegNum64(1, 0, 9, 3, 5), MISCREG_TLBI_VALE1ISNXS },
815 { MiscRegNum64(1, 0, 9, 3, 7), MISCREG_TLBI_VAALE1ISNXS },
816 { MiscRegNum64(1, 0, 9, 5, 1), MISCREG_TLBI_RVAE1OSNXS },
817 { MiscRegNum64(1, 0, 9, 5, 3), MISCREG_TLBI_RVAAE1OSNXS },
818 { MiscRegNum64(1, 0, 9, 5, 5), MISCREG_TLBI_RVALE1OSNXS },
819 { MiscRegNum64(1, 0, 9, 5, 7), MISCREG_TLBI_RVAALE1OSNXS },
820 { MiscRegNum64(1, 0, 9, 6, 1), MISCREG_TLBI_RVAE1NXS },
821 { MiscRegNum64(1, 0, 9, 6, 3), MISCREG_TLBI_RVAAE1NXS },
822 { MiscRegNum64(1, 0, 9, 6, 5), MISCREG_TLBI_RVALE1NXS },
823 { MiscRegNum64(1, 0, 9, 6, 7), MISCREG_TLBI_RVAALE1NXS },
824 { MiscRegNum64(1, 0, 9, 7, 0), MISCREG_TLBI_VMALLE1NXS },
825 { MiscRegNum64(1, 0, 9, 7, 1), MISCREG_TLBI_VAE1NXS },
826 { MiscRegNum64(1, 0, 9, 7, 2), MISCREG_TLBI_ASIDE1NXS },
827 { MiscRegNum64(1, 0, 9, 7, 3), MISCREG_TLBI_VAAE1NXS },
828 { MiscRegNum64(1, 0, 9, 7, 5), MISCREG_TLBI_VALE1NXS },
829 { MiscRegNum64(1, 0, 9, 7, 7), MISCREG_TLBI_VAALE1NXS },
830 { MiscRegNum64(1, 3, 7, 4, 1), MISCREG_DC_ZVA_Xt },
831 { MiscRegNum64(1, 3, 7, 5, 1), MISCREG_IC_IVAU_Xt },
832 { MiscRegNum64(1, 3, 7, 10, 1), MISCREG_DC_CVAC_Xt },
833 { MiscRegNum64(1, 3, 7, 11, 1), MISCREG_DC_CVAU_Xt },
834 { MiscRegNum64(1, 3, 7, 14, 1), MISCREG_DC_CIVAC_Xt },
835 { MiscRegNum64(1, 4, 7, 8, 0), MISCREG_AT_S1E2R_Xt },
836 { MiscRegNum64(1, 4, 7, 8, 1), MISCREG_AT_S1E2W_Xt },
837 { MiscRegNum64(1, 4, 7, 8, 4), MISCREG_AT_S12E1R_Xt },
838 { MiscRegNum64(1, 4, 7, 8, 5), MISCREG_AT_S12E1W_Xt },
839 { MiscRegNum64(1, 4, 7, 8, 6), MISCREG_AT_S12E0R_Xt },
840 { MiscRegNum64(1, 4, 7, 8, 7), MISCREG_AT_S12E0W_Xt },
841 { MiscRegNum64(1, 4, 8, 0, 1), MISCREG_TLBI_IPAS2E1IS },
842 { MiscRegNum64(1, 4, 8, 0, 2), MISCREG_TLBI_RIPAS2E1IS },
843 { MiscRegNum64(1, 4, 8, 0, 5), MISCREG_TLBI_IPAS2LE1IS },
844 { MiscRegNum64(1, 4, 8, 1, 0), MISCREG_TLBI_ALLE2OS },
845 { MiscRegNum64(1, 4, 8, 1, 1), MISCREG_TLBI_VAE2OS },
846 { MiscRegNum64(1, 4, 8, 1, 4), MISCREG_TLBI_ALLE1OS },
847 { MiscRegNum64(1, 4, 8, 1, 5), MISCREG_TLBI_VALE2OS },
848 { MiscRegNum64(1, 4, 8, 1, 6), MISCREG_TLBI_VMALLS12E1OS },
849 { MiscRegNum64(1, 4, 8, 0, 6), MISCREG_TLBI_RIPAS2LE1IS },
850 { MiscRegNum64(1, 4, 8, 2, 1), MISCREG_TLBI_RVAE2IS },
851 { MiscRegNum64(1, 4, 8, 2, 5), MISCREG_TLBI_RVALE2IS },
852 { MiscRegNum64(1, 4, 8, 3, 0), MISCREG_TLBI_ALLE2IS },
853 { MiscRegNum64(1, 4, 8, 3, 1), MISCREG_TLBI_VAE2IS },
854 { MiscRegNum64(1, 4, 8, 3, 4), MISCREG_TLBI_ALLE1IS },
855 { MiscRegNum64(1, 4, 8, 3, 5), MISCREG_TLBI_VALE2IS },
856 { MiscRegNum64(1, 4, 8, 3, 6), MISCREG_TLBI_VMALLS12E1IS },
857 { MiscRegNum64(1, 4, 8, 4, 0), MISCREG_TLBI_IPAS2E1OS },
858 { MiscRegNum64(1, 4, 8, 4, 1), MISCREG_TLBI_IPAS2E1 },
859 { MiscRegNum64(1, 4, 8, 4, 2), MISCREG_TLBI_RIPAS2E1 },
860 { MiscRegNum64(1, 4, 8, 4, 3), MISCREG_TLBI_RIPAS2E1OS },
861 { MiscRegNum64(1, 4, 8, 4, 4), MISCREG_TLBI_IPAS2LE1OS },
862 { MiscRegNum64(1, 4, 8, 4, 5), MISCREG_TLBI_IPAS2LE1 },
863 { MiscRegNum64(1, 4, 8, 4, 6), MISCREG_TLBI_RIPAS2LE1 },
864 { MiscRegNum64(1, 4, 8, 4, 7), MISCREG_TLBI_RIPAS2LE1OS },
865 { MiscRegNum64(1, 4, 8, 5, 1), MISCREG_TLBI_RVAE2OS },
866 { MiscRegNum64(1, 4, 8, 5, 5), MISCREG_TLBI_RVALE2OS },
867 { MiscRegNum64(1, 4, 8, 6, 1), MISCREG_TLBI_RVAE2 },
868 { MiscRegNum64(1, 4, 8, 6, 5), MISCREG_TLBI_RVALE2 },
869 { MiscRegNum64(1, 4, 8, 7, 0), MISCREG_TLBI_ALLE2 },
870 { MiscRegNum64(1, 4, 8, 7, 1), MISCREG_TLBI_VAE2 },
871 { MiscRegNum64(1, 4, 8, 7, 4), MISCREG_TLBI_ALLE1 },
872 { MiscRegNum64(1, 4, 8, 7, 5), MISCREG_TLBI_VALE2 },
873 { MiscRegNum64(1, 4, 8, 7, 6), MISCREG_TLBI_VMALLS12E1 },
874 { MiscRegNum64(1, 4, 9, 0, 1), MISCREG_TLBI_IPAS2E1ISNXS },
875 { MiscRegNum64(1, 4, 9, 0, 2), MISCREG_TLBI_RIPAS2E1ISNXS },
876 { MiscRegNum64(1, 4, 9, 0, 5), MISCREG_TLBI_IPAS2LE1ISNXS },
877 { MiscRegNum64(1, 4, 9, 1, 0), MISCREG_TLBI_ALLE2OSNXS },
878 { MiscRegNum64(1, 4, 9, 1, 1), MISCREG_TLBI_VAE2OSNXS },
879 { MiscRegNum64(1, 4, 9, 1, 4), MISCREG_TLBI_ALLE1OSNXS },
880 { MiscRegNum64(1, 4, 9, 1, 5), MISCREG_TLBI_VALE2OSNXS },
881 { MiscRegNum64(1, 4, 9, 1, 6), MISCREG_TLBI_VMALLS12E1OSNXS },
882 { MiscRegNum64(1, 4, 9, 0, 6), MISCREG_TLBI_RIPAS2LE1ISNXS },
883 { MiscRegNum64(1, 4, 9, 2, 1), MISCREG_TLBI_RVAE2ISNXS },
884 { MiscRegNum64(1, 4, 9, 2, 5), MISCREG_TLBI_RVALE2ISNXS },
885 { MiscRegNum64(1, 4, 9, 3, 0), MISCREG_TLBI_ALLE2ISNXS },
886 { MiscRegNum64(1, 4, 9, 3, 1), MISCREG_TLBI_VAE2ISNXS },
887 { MiscRegNum64(1, 4, 9, 3, 4), MISCREG_TLBI_ALLE1ISNXS },
888 { MiscRegNum64(1, 4, 9, 3, 5), MISCREG_TLBI_VALE2ISNXS },
889 { MiscRegNum64(1, 4, 9, 3, 6), MISCREG_TLBI_VMALLS12E1ISNXS },
890 { MiscRegNum64(1, 4, 9, 4, 0), MISCREG_TLBI_IPAS2E1OSNXS },
891 { MiscRegNum64(1, 4, 9, 4, 1), MISCREG_TLBI_IPAS2E1NXS },
892 { MiscRegNum64(1, 4, 9, 4, 2), MISCREG_TLBI_RIPAS2E1NXS },
893 { MiscRegNum64(1, 4, 9, 4, 3), MISCREG_TLBI_RIPAS2E1OSNXS },
894 { MiscRegNum64(1, 4, 9, 4, 4), MISCREG_TLBI_IPAS2LE1OSNXS },
895 { MiscRegNum64(1, 4, 9, 4, 5), MISCREG_TLBI_IPAS2LE1NXS },
896 { MiscRegNum64(1, 4, 9, 4, 6), MISCREG_TLBI_RIPAS2LE1NXS },
897 { MiscRegNum64(1, 4, 9, 4, 7), MISCREG_TLBI_RIPAS2LE1OSNXS },
898 { MiscRegNum64(1, 4, 9, 5, 1), MISCREG_TLBI_RVAE2OSNXS },
899 { MiscRegNum64(1, 4, 9, 5, 5), MISCREG_TLBI_RVALE2OSNXS },
900 { MiscRegNum64(1, 4, 9, 6, 1), MISCREG_TLBI_RVAE2NXS },
901 { MiscRegNum64(1, 4, 9, 6, 5), MISCREG_TLBI_RVALE2NXS },
902 { MiscRegNum64(1, 4, 9, 7, 0), MISCREG_TLBI_ALLE2NXS },
903 { MiscRegNum64(1, 4, 9, 7, 1), MISCREG_TLBI_VAE2NXS },
904 { MiscRegNum64(1, 4, 9, 7, 4), MISCREG_TLBI_ALLE1NXS },
905 { MiscRegNum64(1, 4, 9, 7, 5), MISCREG_TLBI_VALE2NXS },
906 { MiscRegNum64(1, 4, 9, 7, 6), MISCREG_TLBI_VMALLS12E1NXS },
907 { MiscRegNum64(1, 6, 7, 8, 0), MISCREG_AT_S1E3R_Xt },
908 { MiscRegNum64(1, 6, 7, 8, 1), MISCREG_AT_S1E3W_Xt },
909 { MiscRegNum64(1, 6, 8, 1, 0), MISCREG_TLBI_ALLE3OS },
910 { MiscRegNum64(1, 6, 8, 1, 1), MISCREG_TLBI_VAE3OS },
911 { MiscRegNum64(1, 6, 8, 1, 5), MISCREG_TLBI_VALE3OS },
912 { MiscRegNum64(1, 6, 8, 2, 1), MISCREG_TLBI_RVAE3IS },
913 { MiscRegNum64(1, 6, 8, 2, 5), MISCREG_TLBI_RVALE3IS },
914 { MiscRegNum64(1, 6, 8, 3, 0), MISCREG_TLBI_ALLE3IS },
915 { MiscRegNum64(1, 6, 8, 3, 1), MISCREG_TLBI_VAE3IS },
916 { MiscRegNum64(1, 6, 8, 3, 5), MISCREG_TLBI_VALE3IS },
917 { MiscRegNum64(1, 6, 8, 5, 1), MISCREG_TLBI_RVAE3OS },
918 { MiscRegNum64(1, 6, 8, 5, 5), MISCREG_TLBI_RVALE3OS },
919 { MiscRegNum64(1, 6, 8, 6, 1), MISCREG_TLBI_RVAE3 },
920 { MiscRegNum64(1, 6, 8, 6, 5), MISCREG_TLBI_RVALE3 },
921 { MiscRegNum64(1, 6, 8, 7, 0), MISCREG_TLBI_ALLE3 },
922 { MiscRegNum64(1, 6, 8, 7, 1), MISCREG_TLBI_VAE3 },
923 { MiscRegNum64(1, 6, 8, 7, 5), MISCREG_TLBI_VALE3 },
924 { MiscRegNum64(1, 6, 9, 1, 0), MISCREG_TLBI_ALLE3OSNXS },
925 { MiscRegNum64(1, 6, 9, 1, 1), MISCREG_TLBI_VAE3OSNXS },
926 { MiscRegNum64(1, 6, 9, 1, 5), MISCREG_TLBI_VALE3OSNXS },
927 { MiscRegNum64(1, 6, 9, 2, 1), MISCREG_TLBI_RVAE3ISNXS },
928 { MiscRegNum64(1, 6, 9, 2, 5), MISCREG_TLBI_RVALE3ISNXS },
929 { MiscRegNum64(1, 6, 9, 3, 0), MISCREG_TLBI_ALLE3ISNXS },
930 { MiscRegNum64(1, 6, 9, 3, 1), MISCREG_TLBI_VAE3ISNXS },
931 { MiscRegNum64(1, 6, 9, 3, 5), MISCREG_TLBI_VALE3ISNXS },
932 { MiscRegNum64(1, 6, 9, 5, 1), MISCREG_TLBI_RVAE3OSNXS },
933 { MiscRegNum64(1, 6, 9, 5, 5), MISCREG_TLBI_RVALE3OSNXS },
934 { MiscRegNum64(1, 6, 9, 6, 1), MISCREG_TLBI_RVAE3NXS },
935 { MiscRegNum64(1, 6, 9, 6, 5), MISCREG_TLBI_RVALE3NXS },
936 { MiscRegNum64(1, 6, 9, 7, 0), MISCREG_TLBI_ALLE3NXS },
937 { MiscRegNum64(1, 6, 9, 7, 1), MISCREG_TLBI_VAE3NXS },
938 { MiscRegNum64(1, 6, 9, 7, 5), MISCREG_TLBI_VALE3NXS },
939 { MiscRegNum64(2, 0, 0, 0, 2), MISCREG_OSDTRRX_EL1 },
940 { MiscRegNum64(2, 0, 0, 0, 4), MISCREG_DBGBVR0_EL1 },
941 { MiscRegNum64(2, 0, 0, 0, 5), MISCREG_DBGBCR0_EL1 },
942 { MiscRegNum64(2, 0, 0, 0, 6), MISCREG_DBGWVR0_EL1 },
943 { MiscRegNum64(2, 0, 0, 0, 7), MISCREG_DBGWCR0_EL1 },
944 { MiscRegNum64(2, 0, 0, 1, 4), MISCREG_DBGBVR1_EL1 },
945 { MiscRegNum64(2, 0, 0, 1, 5), MISCREG_DBGBCR1_EL1 },
946 { MiscRegNum64(2, 0, 0, 1, 6), MISCREG_DBGWVR1_EL1 },
947 { MiscRegNum64(2, 0, 0, 1, 7), MISCREG_DBGWCR1_EL1 },
948 { MiscRegNum64(2, 0, 0, 2, 0), MISCREG_MDCCINT_EL1 },
949 { MiscRegNum64(2, 0, 0, 2, 2), MISCREG_MDSCR_EL1 },
950 { MiscRegNum64(2, 0, 0, 2, 4), MISCREG_DBGBVR2_EL1 },
951 { MiscRegNum64(2, 0, 0, 2, 5), MISCREG_DBGBCR2_EL1 },
952 { MiscRegNum64(2, 0, 0, 2, 6), MISCREG_DBGWVR2_EL1 },
953 { MiscRegNum64(2, 0, 0, 2, 7), MISCREG_DBGWCR2_EL1 },
954 { MiscRegNum64(2, 0, 0, 3, 2), MISCREG_OSDTRTX_EL1 },
955 { MiscRegNum64(2, 0, 0, 3, 4), MISCREG_DBGBVR3_EL1 },
956 { MiscRegNum64(2, 0, 0, 3, 5), MISCREG_DBGBCR3_EL1 },
957 { MiscRegNum64(2, 0, 0, 3, 6), MISCREG_DBGWVR3_EL1 },
958 { MiscRegNum64(2, 0, 0, 3, 7), MISCREG_DBGWCR3_EL1 },
959 { MiscRegNum64(2, 0, 0, 4, 4), MISCREG_DBGBVR4_EL1 },
960 { MiscRegNum64(2, 0, 0, 4, 5), MISCREG_DBGBCR4_EL1 },
961 { MiscRegNum64(2, 0, 0, 4, 6), MISCREG_DBGWVR4_EL1 },
962 { MiscRegNum64(2, 0, 0, 4, 7), MISCREG_DBGWCR4_EL1 },
963 { MiscRegNum64(2, 0, 0, 5, 4), MISCREG_DBGBVR5_EL1 },
964 { MiscRegNum64(2, 0, 0, 5, 5), MISCREG_DBGBCR5_EL1 },
965 { MiscRegNum64(2, 0, 0, 5, 6), MISCREG_DBGWVR5_EL1 },
966 { MiscRegNum64(2, 0, 0, 5, 7), MISCREG_DBGWCR5_EL1 },
967 { MiscRegNum64(2, 0, 0, 6, 2), MISCREG_OSECCR_EL1 },
968 { MiscRegNum64(2, 0, 0, 6, 4), MISCREG_DBGBVR6_EL1 },
969 { MiscRegNum64(2, 0, 0, 6, 5), MISCREG_DBGBCR6_EL1 },
970 { MiscRegNum64(2, 0, 0, 6, 6), MISCREG_DBGWVR6_EL1 },
971 { MiscRegNum64(2, 0, 0, 6, 7), MISCREG_DBGWCR6_EL1 },
972 { MiscRegNum64(2, 0, 0, 7, 4), MISCREG_DBGBVR7_EL1 },
973 { MiscRegNum64(2, 0, 0, 7, 5), MISCREG_DBGBCR7_EL1 },
974 { MiscRegNum64(2, 0, 0, 7, 6), MISCREG_DBGWVR7_EL1 },
975 { MiscRegNum64(2, 0, 0, 7, 7), MISCREG_DBGWCR7_EL1 },
976 { MiscRegNum64(2, 0, 0, 8, 4), MISCREG_DBGBVR8_EL1 },
977 { MiscRegNum64(2, 0, 0, 8, 5), MISCREG_DBGBCR8_EL1 },
978 { MiscRegNum64(2, 0, 0, 8, 6), MISCREG_DBGWVR8_EL1 },
979 { MiscRegNum64(2, 0, 0, 8, 7), MISCREG_DBGWCR8_EL1 },
980 { MiscRegNum64(2, 0, 0, 9, 4), MISCREG_DBGBVR9_EL1 },
981 { MiscRegNum64(2, 0, 0, 9, 5), MISCREG_DBGBCR9_EL1 },
982 { MiscRegNum64(2, 0, 0, 9, 6), MISCREG_DBGWVR9_EL1 },
983 { MiscRegNum64(2, 0, 0, 9, 7), MISCREG_DBGWCR9_EL1 },
984 { MiscRegNum64(2, 0, 0, 10, 4), MISCREG_DBGBVR10_EL1 },
985 { MiscRegNum64(2, 0, 0, 10, 5), MISCREG_DBGBCR10_EL1 },
986 { MiscRegNum64(2, 0, 0, 10, 6), MISCREG_DBGWVR10_EL1 },
987 { MiscRegNum64(2, 0, 0, 10, 7), MISCREG_DBGWCR10_EL1 },
988 { MiscRegNum64(2, 0, 0, 11, 4), MISCREG_DBGBVR11_EL1 },
989 { MiscRegNum64(2, 0, 0, 11, 5), MISCREG_DBGBCR11_EL1 },
990 { MiscRegNum64(2, 0, 0, 11, 6), MISCREG_DBGWVR11_EL1 },
991 { MiscRegNum64(2, 0, 0, 11, 7), MISCREG_DBGWCR11_EL1 },
992 { MiscRegNum64(2, 0, 0, 12, 4), MISCREG_DBGBVR12_EL1 },
993 { MiscRegNum64(2, 0, 0, 12, 5), MISCREG_DBGBCR12_EL1 },
994 { MiscRegNum64(2, 0, 0, 12, 6), MISCREG_DBGWVR12_EL1 },
995 { MiscRegNum64(2, 0, 0, 12, 7), MISCREG_DBGWCR12_EL1 },
996 { MiscRegNum64(2, 0, 0, 13, 4), MISCREG_DBGBVR13_EL1 },
997 { MiscRegNum64(2, 0, 0, 13, 5), MISCREG_DBGBCR13_EL1 },
998 { MiscRegNum64(2, 0, 0, 13, 6), MISCREG_DBGWVR13_EL1 },
999 { MiscRegNum64(2, 0, 0, 13, 7), MISCREG_DBGWCR13_EL1 },
1000 { MiscRegNum64(2, 0, 0, 14, 4), MISCREG_DBGBVR14_EL1 },
1001 { MiscRegNum64(2, 0, 0, 14, 5), MISCREG_DBGBCR14_EL1 },
1002 { MiscRegNum64(2, 0, 0, 14, 6), MISCREG_DBGWVR14_EL1 },
1003 { MiscRegNum64(2, 0, 0, 14, 7), MISCREG_DBGWCR14_EL1 },
1004 { MiscRegNum64(2, 0, 0, 15, 4), MISCREG_DBGBVR15_EL1 },
1005 { MiscRegNum64(2, 0, 0, 15, 5), MISCREG_DBGBCR15_EL1 },
1006 { MiscRegNum64(2, 0, 0, 15, 6), MISCREG_DBGWVR15_EL1 },
1007 { MiscRegNum64(2, 0, 0, 15, 7), MISCREG_DBGWCR15_EL1 },
1008 { MiscRegNum64(2, 0, 1, 0, 0), MISCREG_MDRAR_EL1 },
1009 { MiscRegNum64(2, 0, 1, 0, 4), MISCREG_OSLAR_EL1 },
1010 { MiscRegNum64(2, 0, 1, 1, 4), MISCREG_OSLSR_EL1 },
1011 { MiscRegNum64(2, 0, 1, 3, 4), MISCREG_OSDLR_EL1 },
1012 { MiscRegNum64(2, 0, 1, 4, 4), MISCREG_DBGPRCR_EL1 },
1013 { MiscRegNum64(2, 0, 7, 8, 6), MISCREG_DBGCLAIMSET_EL1 },
1014 { MiscRegNum64(2, 0, 7, 9, 6), MISCREG_DBGCLAIMCLR_EL1 },
1015 { MiscRegNum64(2, 0, 7, 14, 6), MISCREG_DBGAUTHSTATUS_EL1 },
1016 { MiscRegNum64(2, 2, 0, 0, 0), MISCREG_TEECR32_EL1 },
1017 { MiscRegNum64(2, 2, 1, 0, 0), MISCREG_TEEHBR32_EL1 },
1018 { MiscRegNum64(2, 3, 0, 1, 0), MISCREG_MDCCSR_EL0 },
1019 { MiscRegNum64(2, 3, 0, 4, 0), MISCREG_MDDTR_EL0 },
1020 { MiscRegNum64(2, 3, 0, 5, 0), MISCREG_MDDTRRX_EL0 },
1021 { MiscRegNum64(2, 4, 0, 7, 0), MISCREG_DBGVCR32_EL2 },
1022 { MiscRegNum64(3, 0, 0, 0, 0), MISCREG_MIDR_EL1 },
1023 { MiscRegNum64(3, 0, 0, 0, 5), MISCREG_MPIDR_EL1 },
1024 { MiscRegNum64(3, 0, 0, 0, 6), MISCREG_REVIDR_EL1 },
1025 { MiscRegNum64(3, 0, 0, 1, 0), MISCREG_ID_PFR0_EL1 },
1026 { MiscRegNum64(3, 0, 0, 1, 1), MISCREG_ID_PFR1_EL1 },
1027 { MiscRegNum64(3, 0, 0, 1, 2), MISCREG_ID_DFR0_EL1 },
1028 { MiscRegNum64(3, 0, 0, 1, 3), MISCREG_ID_AFR0_EL1 },
1029 { MiscRegNum64(3, 0, 0, 1, 4), MISCREG_ID_MMFR0_EL1 },
1030 { MiscRegNum64(3, 0, 0, 1, 5), MISCREG_ID_MMFR1_EL1 },
1031 { MiscRegNum64(3, 0, 0, 1, 6), MISCREG_ID_MMFR2_EL1 },
1032 { MiscRegNum64(3, 0, 0, 1, 7), MISCREG_ID_MMFR3_EL1 },
1033 { MiscRegNum64(3, 0, 0, 2, 0), MISCREG_ID_ISAR0_EL1 },
1034 { MiscRegNum64(3, 0, 0, 2, 1), MISCREG_ID_ISAR1_EL1 },
1035 { MiscRegNum64(3, 0, 0, 2, 2), MISCREG_ID_ISAR2_EL1 },
1036 { MiscRegNum64(3, 0, 0, 2, 3), MISCREG_ID_ISAR3_EL1 },
1037 { MiscRegNum64(3, 0, 0, 2, 4), MISCREG_ID_ISAR4_EL1 },
1038 { MiscRegNum64(3, 0, 0, 2, 5), MISCREG_ID_ISAR5_EL1 },
1039 { MiscRegNum64(3, 0, 0, 2, 6), MISCREG_ID_MMFR4_EL1 },
1040 { MiscRegNum64(3, 0, 0, 2, 7), MISCREG_ID_ISAR6_EL1 },
1041 { MiscRegNum64(3, 0, 0, 3, 0), MISCREG_MVFR0_EL1 },
1042 { MiscRegNum64(3, 0, 0, 3, 1), MISCREG_MVFR1_EL1 },
1043 { MiscRegNum64(3, 0, 0, 3, 2), MISCREG_MVFR2_EL1 },
1044 { MiscRegNum64(3, 0, 0, 3, 3), MISCREG_RAZ },
1045 { MiscRegNum64(3, 0, 0, 3, 4), MISCREG_RAZ },
1046 { MiscRegNum64(3, 0, 0, 3, 5), MISCREG_RAZ },
1047 { MiscRegNum64(3, 0, 0, 3, 6), MISCREG_RAZ },
1048 { MiscRegNum64(3, 0, 0, 3, 7), MISCREG_RAZ },
1049 { MiscRegNum64(3, 0, 0, 4, 0), MISCREG_ID_AA64PFR0_EL1 },
1050 { MiscRegNum64(3, 0, 0, 4, 1), MISCREG_ID_AA64PFR1_EL1 },
1051 { MiscRegNum64(3, 0, 0, 4, 2), MISCREG_RAZ },
1052 { MiscRegNum64(3, 0, 0, 4, 3), MISCREG_RAZ },
1053 { MiscRegNum64(3, 0, 0, 4, 4), MISCREG_ID_AA64ZFR0_EL1 },
1054 { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_ID_AA64SMFR0_EL1 },
1055 { MiscRegNum64(3, 0, 0, 4, 6), MISCREG_RAZ },
1056 { MiscRegNum64(3, 0, 0, 4, 7), MISCREG_RAZ },
1057 { MiscRegNum64(3, 0, 0, 5, 0), MISCREG_ID_AA64DFR0_EL1 },
1058 { MiscRegNum64(3, 0, 0, 5, 1), MISCREG_ID_AA64DFR1_EL1 },
1059 { MiscRegNum64(3, 0, 0, 5, 2), MISCREG_RAZ },
1060 { MiscRegNum64(3, 0, 0, 5, 3), MISCREG_RAZ },
1061 { MiscRegNum64(3, 0, 0, 5, 4), MISCREG_ID_AA64AFR0_EL1 },
1062 { MiscRegNum64(3, 0, 0, 5, 5), MISCREG_ID_AA64AFR1_EL1 },
1063 { MiscRegNum64(3, 0, 0, 5, 6), MISCREG_RAZ },
1064 { MiscRegNum64(3, 0, 0, 5, 7), MISCREG_RAZ },
1065 { MiscRegNum64(3, 0, 0, 6, 0), MISCREG_ID_AA64ISAR0_EL1 },
1066 { MiscRegNum64(3, 0, 0, 6, 1), MISCREG_ID_AA64ISAR1_EL1 },
1067 { MiscRegNum64(3, 0, 0, 6, 2), MISCREG_RAZ },
1068 { MiscRegNum64(3, 0, 0, 6, 3), MISCREG_RAZ },
1069 { MiscRegNum64(3, 0, 0, 6, 4), MISCREG_RAZ },
1070 { MiscRegNum64(3, 0, 0, 6, 5), MISCREG_RAZ },
1071 { MiscRegNum64(3, 0, 0, 6, 6), MISCREG_RAZ },
1072 { MiscRegNum64(3, 0, 0, 6, 7), MISCREG_RAZ },
1073 { MiscRegNum64(3, 0, 0, 7, 0), MISCREG_ID_AA64MMFR0_EL1 },
1074 { MiscRegNum64(3, 0, 0, 7, 1), MISCREG_ID_AA64MMFR1_EL1 },
1075 { MiscRegNum64(3, 0, 0, 7, 2), MISCREG_ID_AA64MMFR2_EL1 },
1076 { MiscRegNum64(3, 0, 0, 7, 3), MISCREG_ID_AA64MMFR3_EL1 },
1077 { MiscRegNum64(3, 0, 0, 7, 4), MISCREG_RAZ },
1078 { MiscRegNum64(3, 0, 0, 7, 5), MISCREG_RAZ },
1079 { MiscRegNum64(3, 0, 0, 7, 6), MISCREG_RAZ },
1080 { MiscRegNum64(3, 0, 0, 7, 7), MISCREG_RAZ },
1081 { MiscRegNum64(3, 0, 1, 0, 0), MISCREG_SCTLR_EL1 },
1082 { MiscRegNum64(3, 0, 1, 0, 1), MISCREG_ACTLR_EL1 },
1083 { MiscRegNum64(3, 0, 1, 0, 2), MISCREG_CPACR_EL1 },
1084 { MiscRegNum64(3, 0, 1, 0, 3), MISCREG_SCTLR2_EL1 },
1085 { MiscRegNum64(3, 0, 1, 2, 0), MISCREG_ZCR_EL1 },
1086 { MiscRegNum64(3, 0, 1, 2, 4), MISCREG_SMPRI_EL1 },
1087 { MiscRegNum64(3, 0, 1, 2, 6), MISCREG_SMCR_EL1 },
1088 { MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
1089 { MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
1090 { MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
1091 { MiscRegNum64(3, 0, 2, 0, 3), MISCREG_TCR2_EL1 },
1092 { MiscRegNum64(3, 0, 2, 1, 0), MISCREG_APIAKeyLo_EL1 },
1093 { MiscRegNum64(3, 0, 2, 1, 1), MISCREG_APIAKeyHi_EL1 },
1094 { MiscRegNum64(3, 0, 2, 1, 2), MISCREG_APIBKeyLo_EL1 },
1095 { MiscRegNum64(3, 0, 2, 1, 3), MISCREG_APIBKeyHi_EL1 },
1096 { MiscRegNum64(3, 0, 2, 2, 0), MISCREG_APDAKeyLo_EL1 },
1097 { MiscRegNum64(3, 0, 2, 2, 1), MISCREG_APDAKeyHi_EL1 },
1098 { MiscRegNum64(3, 0, 2, 2, 2), MISCREG_APDBKeyLo_EL1 },
1099 { MiscRegNum64(3, 0, 2, 2, 3), MISCREG_APDBKeyHi_EL1 },
1100 { MiscRegNum64(3, 0, 2, 3, 0), MISCREG_APGAKeyLo_EL1 },
1101 { MiscRegNum64(3, 0, 2, 3, 1), MISCREG_APGAKeyHi_EL1 },
1102 { MiscRegNum64(3, 0, 4, 0, 0), MISCREG_SPSR_EL1 },
1103 { MiscRegNum64(3, 0, 4, 0, 1), MISCREG_ELR_EL1 },
1104 { MiscRegNum64(3, 0, 4, 1, 0), MISCREG_SP_EL0 },
1105 { MiscRegNum64(3, 0, 4, 2, 0), MISCREG_SPSEL },
1106 { MiscRegNum64(3, 0, 4, 2, 2), MISCREG_CURRENTEL },
1107 { MiscRegNum64(3, 0, 4, 2, 3), MISCREG_PAN },
1108 { MiscRegNum64(3, 0, 4, 2, 4), MISCREG_UAO },
1109 { MiscRegNum64(3, 0, 4, 6, 0), MISCREG_ICC_PMR_EL1 },
1110 { MiscRegNum64(3, 0, 5, 1, 0), MISCREG_AFSR0_EL1 },
1111 { MiscRegNum64(3, 0, 5, 1, 1), MISCREG_AFSR1_EL1 },
1112 { MiscRegNum64(3, 0, 5, 2, 0), MISCREG_ESR_EL1 },
1113 { MiscRegNum64(3, 0, 5, 3, 0), MISCREG_ERRIDR_EL1 },
1114 { MiscRegNum64(3, 0, 5, 3, 1), MISCREG_ERRSELR_EL1 },
1115 { MiscRegNum64(3, 0, 5, 4, 0), MISCREG_ERXFR_EL1 },
1116 { MiscRegNum64(3, 0, 5, 4, 1), MISCREG_ERXCTLR_EL1 },
1117 { MiscRegNum64(3, 0, 5, 4, 2), MISCREG_ERXSTATUS_EL1 },
1118 { MiscRegNum64(3, 0, 5, 4, 3), MISCREG_ERXADDR_EL1 },
1119 { MiscRegNum64(3, 0, 5, 5, 0), MISCREG_ERXMISC0_EL1 },
1120 { MiscRegNum64(3, 0, 5, 5, 1), MISCREG_ERXMISC1_EL1 },
1121 { MiscRegNum64(3, 0, 6, 0, 0), MISCREG_FAR_EL1 },
1122 { MiscRegNum64(3, 0, 7, 4, 0), MISCREG_PAR_EL1 },
1123 { MiscRegNum64(3, 0, 9, 14, 1), MISCREG_PMINTENSET_EL1 },
1124 { MiscRegNum64(3, 0, 9, 14, 2), MISCREG_PMINTENCLR_EL1 },
1125 { MiscRegNum64(3, 0, 10, 2, 0), MISCREG_MAIR_EL1 },
1126 { MiscRegNum64(3, 0, 10, 3, 0), MISCREG_AMAIR_EL1 },
1127 { MiscRegNum64(3, 0, 10, 4, 4), MISCREG_MPAMIDR_EL1 },
1128 { MiscRegNum64(3, 0, 10, 5, 0), MISCREG_MPAM1_EL1 },
1129 { MiscRegNum64(3, 0, 10, 5, 1), MISCREG_MPAM0_EL1 },
1130 { MiscRegNum64(3, 0, 10, 5, 3), MISCREG_MPAMSM_EL1 },
1131 { MiscRegNum64(3, 0, 12, 0, 0), MISCREG_VBAR_EL1 },
1132 { MiscRegNum64(3, 0, 12, 0, 1), MISCREG_RVBAR_EL1 },
1133 { MiscRegNum64(3, 0, 12, 1, 0), MISCREG_ISR_EL1 },
1134 { MiscRegNum64(3, 0, 12, 1, 1), MISCREG_DISR_EL1 },
1135 { MiscRegNum64(3, 0, 12, 8, 0), MISCREG_ICC_IAR0_EL1 },
1136 { MiscRegNum64(3, 0, 12, 8, 1), MISCREG_ICC_EOIR0_EL1 },
1137 { MiscRegNum64(3, 0, 12, 8, 2), MISCREG_ICC_HPPIR0_EL1 },
1138 { MiscRegNum64(3, 0, 12, 8, 3), MISCREG_ICC_BPR0_EL1 },
1139 { MiscRegNum64(3, 0, 12, 8, 4), MISCREG_ICC_AP0R0_EL1 },
1140 { MiscRegNum64(3, 0, 12, 8, 5), MISCREG_ICC_AP0R1_EL1 },
1141 { MiscRegNum64(3, 0, 12, 8, 6), MISCREG_ICC_AP0R2_EL1 },
1142 { MiscRegNum64(3, 0, 12, 8, 7), MISCREG_ICC_AP0R3_EL1 },
1143 { MiscRegNum64(3, 0, 12, 9, 0), MISCREG_ICC_AP1R0_EL1 },
1144 { MiscRegNum64(3, 0, 12, 9, 1), MISCREG_ICC_AP1R1_EL1 },
1145 { MiscRegNum64(3, 0, 12, 9, 2), MISCREG_ICC_AP1R2_EL1 },
1146 { MiscRegNum64(3, 0, 12, 9, 3), MISCREG_ICC_AP1R3_EL1 },
1147 { MiscRegNum64(3, 0, 12, 11, 1), MISCREG_ICC_DIR_EL1 },
1148 { MiscRegNum64(3, 0, 12, 11, 3), MISCREG_ICC_RPR_EL1 },
1149 { MiscRegNum64(3, 0, 12, 11, 5), MISCREG_ICC_SGI1R_EL1 },
1150 { MiscRegNum64(3, 0, 12, 11, 6), MISCREG_ICC_ASGI1R_EL1 },
1151 { MiscRegNum64(3, 0, 12, 11, 7), MISCREG_ICC_SGI0R_EL1 },
1152 { MiscRegNum64(3, 0, 12, 12, 0), MISCREG_ICC_IAR1_EL1 },
1153 { MiscRegNum64(3, 0, 12, 12, 1), MISCREG_ICC_EOIR1_EL1 },
1154 { MiscRegNum64(3, 0, 12, 12, 2), MISCREG_ICC_HPPIR1_EL1 },
1155 { MiscRegNum64(3, 0, 12, 12, 3), MISCREG_ICC_BPR1_EL1 },
1156 { MiscRegNum64(3, 0, 12, 12, 4), MISCREG_ICC_CTLR_EL1 },
1157 { MiscRegNum64(3, 0, 12, 12, 5), MISCREG_ICC_SRE_EL1 },
1158 { MiscRegNum64(3, 0, 12, 12, 6), MISCREG_ICC_IGRPEN0_EL1 },
1159 { MiscRegNum64(3, 0, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL1 },
1160 { MiscRegNum64(3, 0, 13, 0, 1), MISCREG_CONTEXTIDR_EL1 },
1161 { MiscRegNum64(3, 0, 13, 0, 4), MISCREG_TPIDR_EL1 },
1162 { MiscRegNum64(3, 0, 14, 1, 0), MISCREG_CNTKCTL_EL1 },
1163 { MiscRegNum64(3, 0, 15, 0, 0), MISCREG_IL1DATA0_EL1 },
1164 { MiscRegNum64(3, 0, 15, 0, 1), MISCREG_IL1DATA1_EL1 },
1165 { MiscRegNum64(3, 0, 15, 0, 2), MISCREG_IL1DATA2_EL1 },
1166 { MiscRegNum64(3, 0, 15, 0, 3), MISCREG_IL1DATA3_EL1 },
1167 { MiscRegNum64(3, 0, 15, 1, 0), MISCREG_DL1DATA0_EL1 },
1168 { MiscRegNum64(3, 0, 15, 1, 1), MISCREG_DL1DATA1_EL1 },
1169 { MiscRegNum64(3, 0, 15, 1, 2), MISCREG_DL1DATA2_EL1 },
1170 { MiscRegNum64(3, 0, 15, 1, 3), MISCREG_DL1DATA3_EL1 },
1171 { MiscRegNum64(3, 0, 15, 1, 4), MISCREG_DL1DATA4_EL1 },
1172 { MiscRegNum64(3, 1, 0, 0, 0), MISCREG_CCSIDR_EL1 },
1173 { MiscRegNum64(3, 1, 0, 0, 1), MISCREG_CLIDR_EL1 },
1174 { MiscRegNum64(3, 1, 0, 0, 6), MISCREG_SMIDR_EL1 },
1175 { MiscRegNum64(3, 1, 0, 0, 7), MISCREG_AIDR_EL1 },
1176 { MiscRegNum64(3, 1, 11, 0, 2), MISCREG_L2CTLR_EL1 },
1177 { MiscRegNum64(3, 1, 11, 0, 3), MISCREG_L2ECTLR_EL1 },
1178 { MiscRegNum64(3, 1, 15, 0, 0), MISCREG_L2ACTLR_EL1 },
1179 { MiscRegNum64(3, 1, 15, 2, 0), MISCREG_CPUACTLR_EL1 },
1180 { MiscRegNum64(3, 1, 15, 2, 1), MISCREG_CPUECTLR_EL1 },
1181 { MiscRegNum64(3, 1, 15, 2, 2), MISCREG_CPUMERRSR_EL1 },
1182 { MiscRegNum64(3, 1, 15, 2, 3), MISCREG_L2MERRSR_EL1 },
1183 { MiscRegNum64(3, 1, 15, 3, 0), MISCREG_CBAR_EL1 },
1184 { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
1185 { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
1186 { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
1187 { MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
1188 { MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
1189 { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
1190 { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
1191 { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
1192 { MiscRegNum64(3, 3, 4, 4, 0), MISCREG_FPCR },
1193 { MiscRegNum64(3, 3, 4, 4, 1), MISCREG_FPSR },
1194 { MiscRegNum64(3, 3, 4, 5, 0), MISCREG_DSPSR_EL0 },
1195 { MiscRegNum64(3, 3, 4, 5, 1), MISCREG_DLR_EL0 },
1196 { MiscRegNum64(3, 3, 9, 12, 0), MISCREG_PMCR_EL0 },
1197 { MiscRegNum64(3, 3, 9, 12, 1), MISCREG_PMCNTENSET_EL0 },
1198 { MiscRegNum64(3, 3, 9, 12, 2), MISCREG_PMCNTENCLR_EL0 },
1199 { MiscRegNum64(3, 3, 9, 12, 3), MISCREG_PMOVSCLR_EL0 },
1200 { MiscRegNum64(3, 3, 9, 12, 4), MISCREG_PMSWINC_EL0 },
1201 { MiscRegNum64(3, 3, 9, 12, 5), MISCREG_PMSELR_EL0 },
1202 { MiscRegNum64(3, 3, 9, 12, 6), MISCREG_PMCEID0_EL0 },
1203 { MiscRegNum64(3, 3, 9, 12, 7), MISCREG_PMCEID1_EL0 },
1204 { MiscRegNum64(3, 3, 9, 13, 0), MISCREG_PMCCNTR_EL0 },
1205 { MiscRegNum64(3, 3, 9, 13, 1), MISCREG_PMXEVTYPER_EL0 },
1206 { MiscRegNum64(3, 3, 9, 13, 2), MISCREG_PMXEVCNTR_EL0 },
1207 { MiscRegNum64(3, 3, 9, 14, 0), MISCREG_PMUSERENR_EL0 },
1208 { MiscRegNum64(3, 3, 9, 14, 3), MISCREG_PMOVSSET_EL0 },
1209 { MiscRegNum64(3, 3, 13, 0, 2), MISCREG_TPIDR_EL0 },
1210 { MiscRegNum64(3, 3, 13, 0, 3), MISCREG_TPIDRRO_EL0 },
1211 { MiscRegNum64(3, 3, 13, 0, 5), MISCREG_TPIDR2_EL0 },
1212 { MiscRegNum64(3, 3, 14, 0, 0), MISCREG_CNTFRQ_EL0 },
1213 { MiscRegNum64(3, 3, 14, 0, 1), MISCREG_CNTPCT_EL0 },
1214 { MiscRegNum64(3, 3, 14, 0, 2), MISCREG_CNTVCT_EL0 },
1215 { MiscRegNum64(3, 3, 14, 2, 0), MISCREG_CNTP_TVAL_EL0 },
1216 { MiscRegNum64(3, 3, 14, 2, 1), MISCREG_CNTP_CTL_EL0 },
1217 { MiscRegNum64(3, 3, 14, 2, 2), MISCREG_CNTP_CVAL_EL0 },
1218 { MiscRegNum64(3, 3, 14, 3, 0), MISCREG_CNTV_TVAL_EL0 },
1219 { MiscRegNum64(3, 3, 14, 3, 1), MISCREG_CNTV_CTL_EL0 },
1220 { MiscRegNum64(3, 3, 14, 3, 2), MISCREG_CNTV_CVAL_EL0 },
1221 { MiscRegNum64(3, 3, 14, 8, 0), MISCREG_PMEVCNTR0_EL0 },
1222 { MiscRegNum64(3, 3, 14, 8, 1), MISCREG_PMEVCNTR1_EL0 },
1223 { MiscRegNum64(3, 3, 14, 8, 2), MISCREG_PMEVCNTR2_EL0 },
1224 { MiscRegNum64(3, 3, 14, 8, 3), MISCREG_PMEVCNTR3_EL0 },
1225 { MiscRegNum64(3, 3, 14, 8, 4), MISCREG_PMEVCNTR4_EL0 },
1226 { MiscRegNum64(3, 3, 14, 8, 5), MISCREG_PMEVCNTR5_EL0 },
1227 { MiscRegNum64(3, 3, 14, 12, 0), MISCREG_PMEVTYPER0_EL0 },
1228 { MiscRegNum64(3, 3, 14, 12, 1), MISCREG_PMEVTYPER1_EL0 },
1229 { MiscRegNum64(3, 3, 14, 12, 2), MISCREG_PMEVTYPER2_EL0 },
1230 { MiscRegNum64(3, 3, 14, 12, 3), MISCREG_PMEVTYPER3_EL0 },
1231 { MiscRegNum64(3, 3, 14, 12, 4), MISCREG_PMEVTYPER4_EL0 },
1232 { MiscRegNum64(3, 3, 14, 12, 5), MISCREG_PMEVTYPER5_EL0 },
1233 { MiscRegNum64(3, 3, 14, 15, 7), MISCREG_PMCCFILTR_EL0 },
1234 { MiscRegNum64(3, 4, 0, 0, 0), MISCREG_VPIDR_EL2 },
1235 { MiscRegNum64(3, 4, 0, 0, 5), MISCREG_VMPIDR_EL2 },
1236 { MiscRegNum64(3, 4, 1, 0, 0), MISCREG_SCTLR_EL2 },
1237 { MiscRegNum64(3, 4, 1, 0, 1), MISCREG_ACTLR_EL2 },
1238 { MiscRegNum64(3, 4, 1, 0, 3), MISCREG_SCTLR2_EL2 },
1239 { MiscRegNum64(3, 4, 1, 1, 0), MISCREG_HCR_EL2 },
1240 { MiscRegNum64(3, 4, 1, 1, 1), MISCREG_MDCR_EL2 },
1241 { MiscRegNum64(3, 4, 1, 1, 2), MISCREG_CPTR_EL2 },
1242 { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
1243 { MiscRegNum64(3, 4, 1, 1, 4), MISCREG_HFGRTR_EL2 },
1244 { MiscRegNum64(3, 4, 1, 1, 5), MISCREG_HFGWTR_EL2 },
1245 { MiscRegNum64(3, 4, 1, 1, 6), MISCREG_HFGITR_EL2 },
1246 { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
1247 { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
1248 { MiscRegNum64(3, 4, 1, 2, 2), MISCREG_HCRX_EL2 },
1249 { MiscRegNum64(3, 4, 1, 2, 5), MISCREG_SMPRIMAP_EL2 },
1250 { MiscRegNum64(3, 4, 1, 2, 6), MISCREG_SMCR_EL2 },
1251 { MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
1252 { MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
1253 { MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
1254 { MiscRegNum64(3, 4, 2, 0, 3), MISCREG_TCR2_EL2 },
1255 { MiscRegNum64(3, 4, 2, 1, 0), MISCREG_VTTBR_EL2 },
1256 { MiscRegNum64(3, 4, 2, 1, 2), MISCREG_VTCR_EL2 },
1257 { MiscRegNum64(3, 4, 2, 6, 0), MISCREG_VSTTBR_EL2 },
1258 { MiscRegNum64(3, 4, 2, 6, 2), MISCREG_VSTCR_EL2 },
1259 { MiscRegNum64(3, 4, 3, 0, 0), MISCREG_DACR32_EL2 },
1260 { MiscRegNum64(3, 4, 3, 1, 4), MISCREG_HDFGRTR_EL2 },
1261 { MiscRegNum64(3, 4, 3, 1, 5), MISCREG_HDFGWTR_EL2 },
1262 { MiscRegNum64(3, 4, 3, 1, 6), MISCREG_HAFGRTR_EL2 },
1263 { MiscRegNum64(3, 4, 4, 0, 0), MISCREG_SPSR_EL2 },
1264 { MiscRegNum64(3, 4, 4, 0, 1), MISCREG_ELR_EL2 },
1265 { MiscRegNum64(3, 4, 4, 1, 0), MISCREG_SP_EL1 },
1266 { MiscRegNum64(3, 4, 4, 3, 0), MISCREG_SPSR_IRQ_AA64 },
1267 { MiscRegNum64(3, 4, 4, 3, 1), MISCREG_SPSR_ABT_AA64 },
1268 { MiscRegNum64(3, 4, 4, 3, 2), MISCREG_SPSR_UND_AA64 },
1269 { MiscRegNum64(3, 4, 4, 3, 3), MISCREG_SPSR_FIQ_AA64 },
1270 { MiscRegNum64(3, 4, 5, 0, 1), MISCREG_IFSR32_EL2 },
1271 { MiscRegNum64(3, 4, 5, 1, 0), MISCREG_AFSR0_EL2 },
1272 { MiscRegNum64(3, 4, 5, 1, 1), MISCREG_AFSR1_EL2 },
1273 { MiscRegNum64(3, 4, 5, 2, 0), MISCREG_ESR_EL2 },
1274 { MiscRegNum64(3, 4, 5, 2, 3), MISCREG_VSESR_EL2 },
1275 { MiscRegNum64(3, 4, 5, 3, 0), MISCREG_FPEXC32_EL2 },
1276 { MiscRegNum64(3, 4, 6, 0, 0), MISCREG_FAR_EL2 },
1277 { MiscRegNum64(3, 4, 6, 0, 4), MISCREG_HPFAR_EL2 },
1278 { MiscRegNum64(3, 4, 10, 2, 0), MISCREG_MAIR_EL2 },
1279 { MiscRegNum64(3, 4, 10, 3, 0), MISCREG_AMAIR_EL2 },
1280 { MiscRegNum64(3, 4, 10, 4, 0), MISCREG_MPAMHCR_EL2 },
1281 { MiscRegNum64(3, 4, 10, 4, 1), MISCREG_MPAMVPMV_EL2 },
1282 { MiscRegNum64(3, 4, 10, 5, 0), MISCREG_MPAM2_EL2 },
1283 { MiscRegNum64(3, 4, 10, 6, 0), MISCREG_MPAMVPM0_EL2 },
1284 { MiscRegNum64(3, 4, 10, 6, 1), MISCREG_MPAMVPM1_EL2 },
1285 { MiscRegNum64(3, 4, 10, 6, 2), MISCREG_MPAMVPM2_EL2 },
1286 { MiscRegNum64(3, 4, 10, 6, 3), MISCREG_MPAMVPM3_EL2 },
1287 { MiscRegNum64(3, 4, 10, 6, 4), MISCREG_MPAMVPM4_EL2 },
1288 { MiscRegNum64(3, 4, 10, 6, 5), MISCREG_MPAMVPM5_EL2 },
1289 { MiscRegNum64(3, 4, 10, 6, 6), MISCREG_MPAMVPM6_EL2 },
1290 { MiscRegNum64(3, 4, 10, 6, 7), MISCREG_MPAMVPM7_EL2 },
1291 { MiscRegNum64(3, 4, 12, 0, 0), MISCREG_VBAR_EL2 },
1292 { MiscRegNum64(3, 4, 12, 0, 1), MISCREG_RVBAR_EL2 },
1293 { MiscRegNum64(3, 4, 12, 1, 1), MISCREG_VDISR_EL2 },
1294 { MiscRegNum64(3, 4, 12, 8, 0), MISCREG_ICH_AP0R0_EL2 },
1295 { MiscRegNum64(3, 4, 12, 8, 1), MISCREG_ICH_AP0R1_EL2 },
1296 { MiscRegNum64(3, 4, 12, 8, 2), MISCREG_ICH_AP0R2_EL2 },
1297 { MiscRegNum64(3, 4, 12, 8, 3), MISCREG_ICH_AP0R3_EL2 },
1298 { MiscRegNum64(3, 4, 12, 9, 0), MISCREG_ICH_AP1R0_EL2 },
1299 { MiscRegNum64(3, 4, 12, 9, 1), MISCREG_ICH_AP1R1_EL2 },
1300 { MiscRegNum64(3, 4, 12, 9, 2), MISCREG_ICH_AP1R2_EL2 },
1301 { MiscRegNum64(3, 4, 12, 9, 3), MISCREG_ICH_AP1R3_EL2 },
1302 { MiscRegNum64(3, 4, 12, 9, 5), MISCREG_ICC_SRE_EL2 },
1303 { MiscRegNum64(3, 4, 12, 11, 0), MISCREG_ICH_HCR_EL2 },
1304 { MiscRegNum64(3, 4, 12, 11, 1), MISCREG_ICH_VTR_EL2 },
1305 { MiscRegNum64(3, 4, 12, 11, 2), MISCREG_ICH_MISR_EL2 },
1306 { MiscRegNum64(3, 4, 12, 11, 3), MISCREG_ICH_EISR_EL2 },
1307 { MiscRegNum64(3, 4, 12, 11, 5), MISCREG_ICH_ELRSR_EL2 },
1308 { MiscRegNum64(3, 4, 12, 11, 7), MISCREG_ICH_VMCR_EL2 },
1309 { MiscRegNum64(3, 4, 12, 12, 0), MISCREG_ICH_LR0_EL2 },
1310 { MiscRegNum64(3, 4, 12, 12, 1), MISCREG_ICH_LR1_EL2 },
1311 { MiscRegNum64(3, 4, 12, 12, 2), MISCREG_ICH_LR2_EL2 },
1312 { MiscRegNum64(3, 4, 12, 12, 3), MISCREG_ICH_LR3_EL2 },
1313 { MiscRegNum64(3, 4, 12, 12, 4), MISCREG_ICH_LR4_EL2 },
1314 { MiscRegNum64(3, 4, 12, 12, 5), MISCREG_ICH_LR5_EL2 },
1315 { MiscRegNum64(3, 4, 12, 12, 6), MISCREG_ICH_LR6_EL2 },
1316 { MiscRegNum64(3, 4, 12, 12, 7), MISCREG_ICH_LR7_EL2 },
1317 { MiscRegNum64(3, 4, 12, 13, 0), MISCREG_ICH_LR8_EL2 },
1318 { MiscRegNum64(3, 4, 12, 13, 1), MISCREG_ICH_LR9_EL2 },
1319 { MiscRegNum64(3, 4, 12, 13, 2), MISCREG_ICH_LR10_EL2 },
1320 { MiscRegNum64(3, 4, 12, 13, 3), MISCREG_ICH_LR11_EL2 },
1321 { MiscRegNum64(3, 4, 12, 13, 4), MISCREG_ICH_LR12_EL2 },
1322 { MiscRegNum64(3, 4, 12, 13, 5), MISCREG_ICH_LR13_EL2 },
1323 { MiscRegNum64(3, 4, 12, 13, 6), MISCREG_ICH_LR14_EL2 },
1324 { MiscRegNum64(3, 4, 12, 13, 7), MISCREG_ICH_LR15_EL2 },
1325 { MiscRegNum64(3, 4, 13, 0, 1), MISCREG_CONTEXTIDR_EL2 },
1326 { MiscRegNum64(3, 4, 13, 0, 2), MISCREG_TPIDR_EL2 },
1327 { MiscRegNum64(3, 4, 14, 0, 3), MISCREG_CNTVOFF_EL2 },
1328 { MiscRegNum64(3, 4, 14, 1, 0), MISCREG_CNTHCTL_EL2 },
1329 { MiscRegNum64(3, 4, 14, 2, 0), MISCREG_CNTHP_TVAL_EL2 },
1330 { MiscRegNum64(3, 4, 14, 2, 1), MISCREG_CNTHP_CTL_EL2 },
1331 { MiscRegNum64(3, 4, 14, 2, 2), MISCREG_CNTHP_CVAL_EL2 },
1332 { MiscRegNum64(3, 4, 14, 3, 0), MISCREG_CNTHV_TVAL_EL2 },
1333 { MiscRegNum64(3, 4, 14, 3, 1), MISCREG_CNTHV_CTL_EL2 },
1334 { MiscRegNum64(3, 4, 14, 3, 2), MISCREG_CNTHV_CVAL_EL2 },
1335 { MiscRegNum64(3, 4, 14, 4, 0), MISCREG_CNTHVS_TVAL_EL2 },
1336 { MiscRegNum64(3, 4, 14, 4, 1), MISCREG_CNTHVS_CTL_EL2 },
1337 { MiscRegNum64(3, 4, 14, 4, 2), MISCREG_CNTHVS_CVAL_EL2 },
1338 { MiscRegNum64(3, 4, 14, 5, 0), MISCREG_CNTHPS_TVAL_EL2 },
1339 { MiscRegNum64(3, 4, 14, 5, 1), MISCREG_CNTHPS_CTL_EL2 },
1340 { MiscRegNum64(3, 4, 14, 5, 2), MISCREG_CNTHPS_CVAL_EL2 },
1341 { MiscRegNum64(3, 5, 1, 0, 0), MISCREG_SCTLR_EL12 },
1342 { MiscRegNum64(3, 5, 1, 0, 2), MISCREG_CPACR_EL12 },
1343 { MiscRegNum64(3, 5, 1, 0, 3), MISCREG_SCTLR2_EL12 },
1344 { MiscRegNum64(3, 5, 1, 2, 0), MISCREG_ZCR_EL12 },
1345 { MiscRegNum64(3, 5, 1, 2, 6), MISCREG_SMCR_EL12 },
1346 { MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
1347 { MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
1348 { MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
1349 { MiscRegNum64(3, 5, 2, 0, 3), MISCREG_TCR2_EL12 },
1350 { MiscRegNum64(3, 5, 4, 0, 0), MISCREG_SPSR_EL12 },
1351 { MiscRegNum64(3, 5, 4, 0, 1), MISCREG_ELR_EL12 },
1352 { MiscRegNum64(3, 5, 5, 1, 0), MISCREG_AFSR0_EL12 },
1353 { MiscRegNum64(3, 5, 5, 1, 1), MISCREG_AFSR1_EL12 },
1354 { MiscRegNum64(3, 5, 5, 2, 0), MISCREG_ESR_EL12 },
1355 { MiscRegNum64(3, 5, 6, 0, 0), MISCREG_FAR_EL12 },
1356 { MiscRegNum64(3, 5, 10, 2, 0), MISCREG_MAIR_EL12 },
1357 { MiscRegNum64(3, 5, 10, 3, 0), MISCREG_AMAIR_EL12 },
1358 { MiscRegNum64(3, 5, 10, 5, 0), MISCREG_MPAM1_EL12 },
1359 { MiscRegNum64(3, 5, 12, 0, 0), MISCREG_VBAR_EL12 },
1360 { MiscRegNum64(3, 5, 13, 0, 1), MISCREG_CONTEXTIDR_EL12 },
1361 { MiscRegNum64(3, 5, 14, 1, 0), MISCREG_CNTKCTL_EL12 },
1362 { MiscRegNum64(3, 5, 14, 2, 0), MISCREG_CNTP_TVAL_EL02 },
1363 { MiscRegNum64(3, 5, 14, 2, 1), MISCREG_CNTP_CTL_EL02 },
1364 { MiscRegNum64(3, 5, 14, 2, 2), MISCREG_CNTP_CVAL_EL02 },
1365 { MiscRegNum64(3, 5, 14, 3, 0), MISCREG_CNTV_TVAL_EL02 },
1366 { MiscRegNum64(3, 5, 14, 3, 1), MISCREG_CNTV_CTL_EL02 },
1367 { MiscRegNum64(3, 5, 14, 3, 2), MISCREG_CNTV_CVAL_EL02 },
1368 { MiscRegNum64(3, 6, 1, 0, 0), MISCREG_SCTLR_EL3 },
1369 { MiscRegNum64(3, 6, 1, 0, 1), MISCREG_ACTLR_EL3 },
1370 { MiscRegNum64(3, 6, 1, 0, 3), MISCREG_SCTLR2_EL3 },
1371 { MiscRegNum64(3, 6, 1, 1, 0), MISCREG_SCR_EL3 },
1372 { MiscRegNum64(3, 6, 1, 1, 1), MISCREG_SDER32_EL3 },
1373 { MiscRegNum64(3, 6, 1, 1, 2), MISCREG_CPTR_EL3 },
1374 { MiscRegNum64(3, 6, 1, 2, 0), MISCREG_ZCR_EL3 },
1375 { MiscRegNum64(3, 6, 1, 2, 6), MISCREG_SMCR_EL3 },
1376 { MiscRegNum64(3, 6, 1, 3, 1), MISCREG_MDCR_EL3 },
1377 { MiscRegNum64(3, 6, 2, 0, 0), MISCREG_TTBR0_EL3 },
1378 { MiscRegNum64(3, 6, 2, 0, 2), MISCREG_TCR_EL3 },
1379 { MiscRegNum64(3, 6, 4, 0, 0), MISCREG_SPSR_EL3 },
1380 { MiscRegNum64(3, 6, 4, 0, 1), MISCREG_ELR_EL3 },
1381 { MiscRegNum64(3, 6, 4, 1, 0), MISCREG_SP_EL2 },
1382 { MiscRegNum64(3, 6, 5, 1, 0), MISCREG_AFSR0_EL3 },
1383 { MiscRegNum64(3, 6, 5, 1, 1), MISCREG_AFSR1_EL3 },
1384 { MiscRegNum64(3, 6, 5, 2, 0), MISCREG_ESR_EL3 },
1385 { MiscRegNum64(3, 6, 6, 0, 0), MISCREG_FAR_EL3 },
1386 { MiscRegNum64(3, 6, 10, 2, 0), MISCREG_MAIR_EL3 },
1387 { MiscRegNum64(3, 6, 10, 3, 0), MISCREG_AMAIR_EL3 },
1388 { MiscRegNum64(3, 6, 10, 5, 0), MISCREG_MPAM3_EL3 },
1389 { MiscRegNum64(3, 6, 12, 0, 0), MISCREG_VBAR_EL3 },
1390 { MiscRegNum64(3, 6, 12, 0, 1), MISCREG_RVBAR_EL3 },
1391 { MiscRegNum64(3, 6, 12, 0, 2), MISCREG_RMR_EL3 },
1392 { MiscRegNum64(3, 6, 12, 12, 4), MISCREG_ICC_CTLR_EL3 },
1393 { MiscRegNum64(3, 6, 12, 12, 5), MISCREG_ICC_SRE_EL3 },
1394 { MiscRegNum64(3, 6, 12, 12, 7), MISCREG_ICC_IGRPEN1_EL3 },
1395 { MiscRegNum64(3, 6, 13, 0, 2), MISCREG_TPIDR_EL3 },
1396 { MiscRegNum64(3, 7, 14, 2, 0), MISCREG_CNTPS_TVAL_EL1 },
1397 { MiscRegNum64(3, 7, 14, 2, 1), MISCREG_CNTPS_CTL_EL1 },
1398 { MiscRegNum64(3, 7, 14, 2, 2), MISCREG_CNTPS_CVAL_EL1 }
1399};
1400
1401template <bool read>
1402HFGTR
1403fgtRegister(ThreadContext *tc)
1404{
1405 if constexpr (read) {
1406 return tc->readMiscReg(MISCREG_HFGRTR_EL2);
1407 } else {
1408 return tc->readMiscReg(MISCREG_HFGWTR_EL2);
1409 }
1410}
1411
1412template <bool read>
1413HDFGTR
1414fgtDebugRegister(ThreadContext *tc)
1415{
1416 if constexpr (read) {
1417 return tc->readMiscReg(MISCREG_HDFGRTR_EL2);
1418 } else {
1419 return tc->readMiscReg(MISCREG_HDFGWTR_EL2);
1420 }
1421}
1422
1429template<bool read, auto r_bitfield>
1430Fault
1431faultFgtEL0(const MiscRegLUTEntry &entry,
1432 ThreadContext *tc, const MiscRegOp64 &inst)
1433{
1434 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1435 const bool in_host = EL2Enabled(tc) && hcr.e2h && hcr.tge;
1436 if (fgtEnabled(tc) && !in_host &&
1437 fgtRegister<read>(tc).*r_bitfield) {
1438 return inst.generateTrap(EL2);
1439 } else {
1440 return NoFault;
1441 }
1442}
1443
1450template<bool read, auto r_bitfield>
1451Fault
1452faultFgtEL1(const MiscRegLUTEntry &entry,
1453 ThreadContext *tc, const MiscRegOp64 &inst)
1454{
1455 if (fgtEnabled(tc) && fgtRegister<read>(tc).*r_bitfield) {
1456 return inst.generateTrap(EL2);
1457 } else {
1458 return NoFault;
1459 }
1460}
1461
1467template<auto r_bitfield>
1468Fault
1469faultFgtInstEL1(const MiscRegLUTEntry &entry,
1470 ThreadContext *tc, const MiscRegOp64 &inst)
1471{
1472 if (fgtEnabled(tc) &&
1473 static_cast<HFGITR>(tc->readMiscReg(MISCREG_HFGITR_EL2)).*r_bitfield) {
1474 return inst.generateTrap(EL2);
1475 } else {
1476 return NoFault;
1477 }
1478}
1479
1486template<auto r_bitfield>
1487Fault
1488faultFgtTlbiNxsEL1(const MiscRegLUTEntry &entry,
1489 ThreadContext *tc, const MiscRegOp64 &inst)
1490{
1491 if (HaveExt(tc, ArmExtension::FEAT_HCX)) {
1492 const HCRX hcrx = tc->readMiscReg(MISCREG_HCRX_EL2);
1493 if (auto fault = faultFgtInstEL1<r_bitfield>(entry, tc, inst);
1494 fault != NoFault && (!isHcrxEL2Enabled(tc) || !hcrx.fgtnxs)) {
1495 return fault;
1496 } else {
1497 return NoFault;
1498 }
1499 } else {
1500 return NoFault;
1501 }
1502}
1503
1510template<bool read, auto r_bitfield>
1511Fault
1512faultFgtDebugEL1(const MiscRegLUTEntry &entry,
1513 ThreadContext *tc, const MiscRegOp64 &inst)
1514{
1515 if (fgtEnabled(tc) && fgtDebugRegister<read>(tc).*r_bitfield) {
1516 return inst.generateTrap(EL2);
1517 } else {
1518 return NoFault;
1519 }
1520}
1521
1527template <auto g_bitfield>
1528Fault
1529faultHcrEL1(const MiscRegLUTEntry &entry,
1530 ThreadContext *tc, const MiscRegOp64 &inst)
1531{
1532 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1533 if (EL2Enabled(tc) && hcr.*g_bitfield) {
1534 return inst.generateTrap(EL2);
1535 } else {
1536 return NoFault;
1537 }
1538}
1539
1547template<bool read, auto g_bitfield, auto r_bitfield>
1548Fault
1549faultHcrFgtEL0(const MiscRegLUTEntry &entry,
1550 ThreadContext *tc, const MiscRegOp64 &inst)
1551{
1552 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1553 const bool in_host = EL2Enabled(tc) && hcr.e2h && hcr.tge;
1554
1555 if (EL2Enabled(tc) && !in_host && hcr.*g_bitfield) {
1556 return inst.generateTrap(EL2);
1557 } else if (auto fault = faultFgtEL0<read, r_bitfield>(entry, tc, inst);
1558 fault != NoFault) {
1559 return fault;
1560 } else {
1561 return NoFault;
1562 }
1563}
1564
1572template<bool read, auto g_bitfield, auto r_bitfield>
1573Fault
1574faultHcrFgtEL1(const MiscRegLUTEntry &entry,
1575 ThreadContext *tc, const MiscRegOp64 &inst)
1576{
1577 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1578
1579 if (EL2Enabled(tc) && hcr.*g_bitfield) {
1580 return inst.generateTrap(EL2);
1581 } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
1582 fault != NoFault) {
1583 return fault;
1584 } else {
1585 return NoFault;
1586 }
1587}
1588
1595template<auto g_bitfield, auto r_bitfield>
1596Fault
1597faultHcrFgtInstEL1(const MiscRegLUTEntry &entry,
1598 ThreadContext *tc, const MiscRegOp64 &inst)
1599{
1600 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1601
1602 if (EL2Enabled(tc) && hcr.*g_bitfield) {
1603 return inst.generateTrap(EL2);
1604 } else if (auto fault = faultFgtInstEL1<r_bitfield>(entry, tc, inst);
1605 fault != NoFault) {
1606 return fault;
1607 } else {
1608 return NoFault;
1609 }
1610}
1611
1619template<auto g_bitfield, auto r_bitfield>
1620Fault
1621faultTlbiNxsEL1(const MiscRegLUTEntry &entry,
1622 ThreadContext *tc, const MiscRegOp64 &inst)
1623{
1624 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1625
1626 if (EL2Enabled(tc) && hcr.*g_bitfield) {
1627 return inst.generateTrap(EL2);
1628 } else if (auto fault = faultFgtTlbiNxsEL1<r_bitfield>(entry, tc, inst);
1629 fault != NoFault) {
1630 return fault;
1631 } else {
1632 return NoFault;
1633 }
1634}
1635
1636Fault
1637faultSpEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1638 const MiscRegOp64 &inst)
1639{
1640 if (tc->readMiscReg(MISCREG_SPSEL) == 0)
1641 return inst.undefined();
1642 else
1643 return NoFault;
1644}
1645
1646Fault
1647faultDaif(const MiscRegLUTEntry &entry, ThreadContext *tc,
1648 const MiscRegOp64 &inst)
1649{
1650 const bool el2_enabled = EL2Enabled(tc);
1651 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1652 const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1653 if ((el2_enabled && hcr.e2h && hcr.tge) || sctlr.uma == 0) {
1654 if (el2_enabled && hcr.tge) {
1655 return inst.generateTrap(EL2);
1656 } else {
1657 return inst.generateTrap(EL1);
1658 }
1659 } else {
1660 return NoFault;
1661 }
1662}
1663
1664Fault
1665faultDczvaEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1666 const MiscRegOp64 &inst)
1667{
1668 if (!FullSystem)
1669 return NoFault;
1670
1671 const SCTLR sctlr = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1);
1672 const SCTLR sctlr2 = tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2);
1673 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1674
1675 const bool el2_enabled = EL2Enabled(tc);
1676 const bool in_host = hcr.e2h && hcr.tge;
1677 if (!(el2_enabled && in_host) && !sctlr.dze) {
1678 if (el2_enabled && hcr.tge) {
1679 return inst.generateTrap(EL2);
1680 } else {
1681 return inst.generateTrap(EL1);
1682 }
1683 } else if (el2_enabled && !in_host && hcr.tdz) {
1684 return inst.generateTrap(EL2);
1685 } else if (el2_enabled && in_host && !sctlr2.dze) {
1686 return inst.generateTrap(EL2);
1687 } else {
1688 return NoFault;
1689 }
1690}
1691
1692Fault
1693faultCvacEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1694 const MiscRegOp64 &inst)
1695{
1696 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1697 const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1698 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1699
1700 const bool el2_enabled = EL2Enabled(tc);
1701 const bool in_host = hcr.e2h && hcr.tge;
1702 if (!(el2_enabled && in_host) && !sctlr.uci) {
1703 if (el2_enabled && hcr.tge) {
1704 return inst.generateTrap(EL2);
1705 } else {
1706 return inst.generateTrap(EL1);
1707 }
1708 } else if (el2_enabled && !in_host && hcr.tpc) {
1709 return inst.generateTrap(EL2);
1710 } else if (el2_enabled && in_host && !sctlr2.uci) {
1711 return inst.generateTrap(EL2);
1712 } else {
1713 return NoFault;
1714 }
1715}
1716
1717Fault
1718faultFpcrEL0(const MiscRegLUTEntry &entry, ThreadContext *tc,
1719 const MiscRegOp64 &inst)
1720{
1721 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1722 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1723 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1724
1725 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1726 const bool el2_enabled = EL2Enabled(tc);
1727 const bool in_host = hcr.e2h && hcr.tge;
1728 if (!(el2_enabled && in_host) && cpacr.fpen != 0b11) {
1729 if (el2_enabled && hcr.tge) {
1730 return inst.generateTrap(EL2, ExceptionClass::UNKNOWN, inst.iss());
1731 } else {
1732 return inst.generateTrap(EL1,
1733 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1734 }
1735 } else if (el2_enabled && in_host && cptr_el2.fpen != 0b11) {
1736 return inst.generateTrap(EL2,
1737 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1738 } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1739 return inst.generateTrap(EL2,
1740 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1741 } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1742 return inst.generateTrap(EL2,
1743 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1744 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1745 return inst.generateTrap(EL3,
1746 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1747 } else {
1748 return NoFault;
1749 }
1750}
1751
1752Fault
1753faultFpcrEL1(const MiscRegLUTEntry &entry, ThreadContext *tc,
1754 const MiscRegOp64 &inst)
1755{
1756 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
1757 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1758 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1759
1760 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1761 const bool el2_enabled = EL2Enabled(tc);
1762 if ((cpacr.fpen & 0b1) == 0b0) {
1763 return inst.generateTrap(EL1,
1764 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1765 } else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
1766 return inst.generateTrap(EL2,
1767 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1768 } else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1769 return inst.generateTrap(EL2,
1770 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1771 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1772 return inst.generateTrap(EL3,
1773 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1774 } else {
1775 return NoFault;
1776 }
1777}
1778
1779Fault
1780faultFpcrEL2(const MiscRegLUTEntry &entry, ThreadContext *tc,
1781 const MiscRegOp64 &inst)
1782{
1783 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
1784 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1785
1786 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1787 if (!hcr.e2h && cptr_el2.tfp) {
1788 return inst.generateTrap(EL2,
1789 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1790 } else if (hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
1791 return inst.generateTrap(EL2,
1792 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1793 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
1794 return inst.generateTrap(EL3,
1795 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1796 } else {
1797 return NoFault;
1798 }
1799}
1800
1801Fault
1802faultFpcrEL3(const MiscRegLUTEntry &entry,
1803 ThreadContext *tc, const MiscRegOp64 &inst)
1804{
1805 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
1806 if (cptr_el3.tfp) {
1807 return inst.generateTrap(EL3,
1808 ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
1809 } else {
1810 return NoFault;
1811 }
1812}
1813
1814Fault
1815faultPouEL0(const MiscRegLUTEntry &entry,
1816 ThreadContext *tc, const MiscRegOp64 &inst)
1817{
1818 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1819 const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1820 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1821
1822 const bool el2_enabled = EL2Enabled(tc);
1823 const bool in_host = hcr.e2h && hcr.tge;
1824 if (!(el2_enabled && in_host) && !sctlr.uci) {
1825 if (el2_enabled && hcr.tge) {
1826 return inst.generateTrap(EL2);
1827 } else {
1828 return inst.generateTrap(EL1);
1829 }
1830 } else if (el2_enabled && !in_host && hcr.tpu) {
1831 return inst.generateTrap(EL2);
1832 } else if (el2_enabled && !in_host &&
1833 HaveExt(tc, ArmExtension::FEAT_EVT) && hcr.tocu) {
1834 return inst.generateTrap(EL2);
1835 } else if (el2_enabled && in_host && !sctlr2.uci) {
1836 return inst.generateTrap(EL2);
1837 } else {
1838 return NoFault;
1839 }
1840}
1841
1842template <auto bitfield>
1843Fault
1844faultPouEL1(const MiscRegLUTEntry &entry,
1845 ThreadContext *tc, const MiscRegOp64 &inst)
1846{
1847 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1848 const bool el2_enabled = EL2Enabled(tc);
1849 if (el2_enabled && hcr.tpu) {
1850 return inst.generateTrap(EL2);
1851 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1852 hcr.tocu) {
1853 return inst.generateTrap(EL2);
1854 } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
1855 fault != NoFault) {
1856 return fault;
1857 } else {
1858 return NoFault;
1859 }
1860}
1861
1862template <auto bitfield>
1863Fault
1864faultPouIsEL1(const MiscRegLUTEntry &entry,
1865 ThreadContext *tc, const MiscRegOp64 &inst)
1866{
1867 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1868 const bool el2_enabled = EL2Enabled(tc);
1869 if (el2_enabled && hcr.tpu) {
1870 return inst.generateTrap(EL2);
1871 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
1872 hcr.ticab) {
1873 return inst.generateTrap(EL2);
1874 } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
1875 fault != NoFault) {
1876 return fault;
1877 } else {
1878 return NoFault;
1879 }
1880}
1881
1882Fault
1883faultCtrEL0(const MiscRegLUTEntry &entry,
1884 ThreadContext *tc, const MiscRegOp64 &inst)
1885{
1886 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1887 const SCTLR sctlr2 = tc->readMiscReg(MISCREG_SCTLR_EL2);
1888 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1889
1890 const bool el2_enabled = EL2Enabled(tc);
1891 const bool in_host = hcr.e2h && hcr.tge;
1892 if (!(el2_enabled && in_host) && !sctlr.uct) {
1893 if (el2_enabled && hcr.tge) {
1894 return inst.generateTrap(EL2);
1895 } else {
1896 return inst.generateTrap(EL1);
1897 }
1898 } else if (auto fault = faultHcrFgtEL0<
1899 true, &HCR::tid2, &HFGTR::ctrEL0>(entry, tc, inst);
1900 fault != NoFault) {
1901 return fault;
1902 } else if (el2_enabled && in_host && !sctlr2.uct) {
1903 return inst.generateTrap(EL2);
1904 } else {
1905 return NoFault;
1906 }
1907}
1908
1909Fault
1910faultMdccsrEL0(const MiscRegLUTEntry &entry,
1911 ThreadContext *tc, const MiscRegOp64 &inst)
1912{
1913 const DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
1914 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1915 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1916
1917 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1918 const bool el2_enabled = EL2Enabled(tc);
1919 if (mdscr.tdcc) {
1920 if (el2_enabled && hcr.tge) {
1921 return inst.generateTrap(EL2);
1922 } else {
1923 return inst.generateTrap(EL1);
1924 }
1925 } else if (el2_enabled && mdcr_el2.tdcc) {
1926 return inst.generateTrap(EL2);
1927 } else if (el2_enabled && (hcr.tge || (mdcr_el2.tde || mdcr_el2.tda))) {
1928 return inst.generateTrap(EL2);
1929 } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1930 return inst.generateTrap(EL3);
1931 } else {
1932 return NoFault;
1933 }
1934}
1935
1936Fault
1937faultMdccsrEL1(const MiscRegLUTEntry &entry,
1938 ThreadContext *tc, const MiscRegOp64 &inst)
1939{
1940 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1941 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1942
1943 const bool el2_enabled = EL2Enabled(tc);
1944 if (el2_enabled && mdcr_el2.tdcc) {
1945 return inst.generateTrap(EL2);
1946 } else if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1947 return inst.generateTrap(EL2);
1948 } else if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1949 return inst.generateTrap(EL3);
1950 } else {
1951 return NoFault;
1952 }
1953}
1954
1955Fault
1956faultMdccsrEL2(const MiscRegLUTEntry &entry,
1957 ThreadContext *tc, const MiscRegOp64 &inst)
1958{
1959 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1960 if (ArmSystem::haveEL(tc, EL3) && (mdcr_el3.tdcc || mdcr_el3.tda)) {
1961 return inst.generateTrap(EL3);
1962 } else {
1963 return NoFault;
1964 }
1965}
1966
1967Fault
1968faultDebugEL1(const MiscRegLUTEntry &entry,
1969 ThreadContext *tc, const MiscRegOp64 &inst)
1970{
1971 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
1972 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1973
1974 const bool el2_enabled = EL2Enabled(tc);
1975 if (el2_enabled && (mdcr_el2.tde || mdcr_el2.tda)) {
1976 return inst.generateTrap(EL2);
1977 } else if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1978 return inst.generateTrap(EL3);
1979 } else {
1980 return NoFault;
1981 }
1982}
1983
1984Fault
1985faultDebugEL2(const MiscRegLUTEntry &entry,
1986 ThreadContext *tc, const MiscRegOp64 &inst)
1987{
1988 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
1989 if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tda) {
1990 return inst.generateTrap(EL3);
1991 } else {
1992 return NoFault;
1993 }
1994}
1995
1996template<bool read, auto r_bitfield>
1997Fault
1998faultDebugWithFgtEL1(const MiscRegLUTEntry &entry,
1999 ThreadContext *tc, const MiscRegOp64 &inst)
2000{
2001 if (auto fault = faultFgtDebugEL1<read, r_bitfield>(entry, tc, inst);
2002 fault != NoFault) {
2003 return fault;
2004 } else {
2005 return faultDebugEL1(entry, tc, inst);
2006 }
2007}
2008
2009template<bool read, auto r_bitfield>
2010Fault
2011faultDebugOsEL1(const MiscRegLUTEntry &entry,
2012 ThreadContext *tc, const MiscRegOp64 &inst)
2013{
2014 const HDCR mdcr_el2 = tc->readMiscReg(MISCREG_MDCR_EL2);
2015 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
2016
2017 if (auto fault = faultFgtDebugEL1<read, r_bitfield>(entry, tc, inst);
2018 fault != NoFault) {
2019 return fault;
2020 } else if (EL2Enabled(tc) && (mdcr_el2.tde || mdcr_el2.tdosa)) {
2021 return inst.generateTrap(EL2);
2022 } else if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tdosa) {
2023 return inst.generateTrap(EL3);
2024 } else {
2025 return NoFault;
2026 }
2027}
2028
2029Fault
2030faultDebugOsEL2(const MiscRegLUTEntry &entry,
2031 ThreadContext *tc, const MiscRegOp64 &inst)
2032{
2033 const HDCR mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
2034 if (ArmSystem::haveEL(tc, EL3) && mdcr_el3.tdosa) {
2035 return inst.generateTrap(EL3);
2036 } else {
2037 return NoFault;
2038 }
2039}
2040
2041Fault
2042faultHcrxEL2(const MiscRegLUTEntry &entry,
2043 ThreadContext *tc, const MiscRegOp64 &inst)
2044{
2045 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2046 if (ArmSystem::haveEL(tc, EL3) && !scr.hxen) {
2047 return inst.generateTrap(EL3);
2048 } else {
2049 return NoFault;
2050 }
2051}
2052
2053Fault
2054faultZcrEL1(const MiscRegLUTEntry &entry,
2055 ThreadContext *tc, const MiscRegOp64 &inst)
2056{
2057 const CPACR cpacr_el1 = tc->readMiscReg(MISCREG_CPACR_EL1);
2058 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2059 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2060
2061 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2062 const bool el2_enabled = EL2Enabled(tc);
2063 if (!(cpacr_el1.zen & 0x1)) {
2064 return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SVE, 0);
2065 } else if (el2_enabled && !hcr.e2h && cptr_el2.tz) {
2066 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
2067 } else if (el2_enabled && hcr.e2h && !(cptr_el2.zen & 0x1)) {
2068 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
2069 } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
2070 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
2071 } else {
2072 return NoFault;
2073 }
2074}
2075
2076Fault
2077faultZcrEL2(const MiscRegLUTEntry &entry,
2078 ThreadContext *tc, const MiscRegOp64 &inst)
2079{
2080 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2081 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2082
2083 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2084 if (!hcr.e2h && cptr_el2.tz) {
2085 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
2086 } else if (hcr.e2h && !(cptr_el2.zen & 0x1)) {
2087 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
2088 } else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
2089 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
2090 } else {
2091 return NoFault;
2092 }
2093}
2094
2095Fault
2096faultZcrEL3(const MiscRegLUTEntry &entry,
2097 ThreadContext *tc, const MiscRegOp64 &inst)
2098{
2099 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2100 if (!cptr_el3.ez) {
2101 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
2102 } else {
2103 return NoFault;
2104 }
2105}
2106
2107Fault
2108faultGicv3(const MiscRegLUTEntry &entry,
2109 ThreadContext *tc, const MiscRegOp64 &inst)
2110{
2111 auto gic = static_cast<ArmSystem*>(tc->getSystemPtr())->getGIC();
2112 if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
2113 return inst.undefined();
2114 } else {
2115 return NoFault;
2116 }
2117}
2118
2119Fault
2120faultIccSgiEL1(const MiscRegLUTEntry &entry,
2121 ThreadContext *tc, const MiscRegOp64 &inst)
2122{
2123 if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
2124 return fault;
2125 }
2126
2127 const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
2128 tc->readMiscReg(MISCREG_ICH_HCR_EL2);
2129 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2130 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2131 if (EL2Enabled(tc) && (hcr.fmo || hcr.imo || ich_hcr.TC)) {
2132 return inst.generateTrap(EL2);
2133 } else if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
2134 return inst.generateTrap(EL3);
2135 } else {
2136 return NoFault;
2137 }
2138}
2139
2140Fault
2141faultIccSgiEL2(const MiscRegLUTEntry &entry,
2142 ThreadContext *tc, const MiscRegOp64 &inst)
2143{
2144 if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
2145 return fault;
2146 }
2147
2148 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2149 if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
2150 return inst.generateTrap(EL3);
2151 } else {
2152 return NoFault;
2153 }
2154}
2155
2156template<bool read, auto g_bitfield>
2157Fault
2158faultSctlr2EL1(const MiscRegLUTEntry &entry,
2159 ThreadContext *tc, const MiscRegOp64 &inst)
2160{
2161 if (HaveExt(tc, ArmExtension::FEAT_SCTLR2)) {
2162 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2163 const HCRX hcrx = tc->readMiscReg(MISCREG_HCRX_EL2);
2164 if (
2165 auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::sctlrEL1>
2166 (
2167 entry,
2168 tc,
2169 inst
2170 );
2171 fault != NoFault
2172 ) {
2173 return fault;
2174 } else if (
2175 EL2Enabled(tc) && (!isHcrxEL2Enabled(tc) || !hcrx.sctlr2En)
2176 ) {
2177 return inst.generateTrap(EL2);
2178 } else if (ArmSystem::haveEL(tc, EL3) && !scr.sctlr2En) {
2179 return inst.generateTrap(EL3);
2180 } else {
2181 return NoFault;
2182 }
2183 } else {
2184 return inst.undefined();
2185 }
2186}
2187
2188Fault
2189faultSctlr2EL2(const MiscRegLUTEntry &entry,
2190 ThreadContext *tc, const MiscRegOp64 &inst)
2191{
2192 if (HaveExt(tc, ArmExtension::FEAT_SCTLR2)) {
2193 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2194 if (ArmSystem::haveEL(tc, EL3) && !scr.sctlr2En) {
2195 return inst.generateTrap(EL3);
2196 } else {
2197 return NoFault;
2198 }
2199 } else {
2200 return inst.undefined();
2201 }
2202}
2203
2204Fault
2205faultSctlr2VheEL2(const MiscRegLUTEntry &entry,
2206 ThreadContext *tc, const MiscRegOp64 &inst)
2207{
2208 if (HaveExt(tc, ArmExtension::FEAT_SCTLR2)) {
2209 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2210 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2211 if (hcr.e2h) {
2212 if (ArmSystem::haveEL(tc, EL3) && !scr.sctlr2En) {
2213 return inst.generateTrap(EL3);
2214 } else {
2215 return NoFault;
2216 }
2217 } else {
2218 return inst.undefined();
2219 }
2220 } else {
2221 return inst.undefined();
2222 }
2223}
2224
2225template<bool read, auto g_bitfield>
2226Fault
2227faultTcr2EL1(const MiscRegLUTEntry &entry,
2228 ThreadContext *tc, const MiscRegOp64 &inst)
2229{
2230 if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
2231 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2232 const HCRX hcrx = tc->readMiscReg(MISCREG_HCRX_EL2);
2233 if (
2234 auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::sctlrEL1>
2235 (
2236 entry,
2237 tc,
2238 inst
2239 );
2240 fault != NoFault
2241 ) {
2242 return fault;
2243 } else if (EL2Enabled(tc) && (!isHcrxEL2Enabled(tc) || !hcrx.tcr2En)) {
2244 return inst.generateTrap(EL2);
2245 } else if (ArmSystem::haveEL(tc, EL3) && !scr.tcr2En) {
2246 return inst.generateTrap(EL3);
2247 } else {
2248 return NoFault;
2249 }
2250 } else {
2251 return inst.undefined();
2252 }
2253}
2254
2255Fault
2256faultTcr2EL2(const MiscRegLUTEntry &entry,
2257 ThreadContext *tc, const MiscRegOp64 &inst)
2258{
2259 if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
2260 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2261 if (ArmSystem::haveEL(tc, EL3) && !scr.tcr2En) {
2262 return inst.generateTrap(EL3);
2263 } else {
2264 return NoFault;
2265 }
2266 } else {
2267 return inst.undefined();
2268 }
2269}
2270
2271Fault
2272faultTcr2VheEL2(const MiscRegLUTEntry &entry,
2273 ThreadContext *tc, const MiscRegOp64 &inst)
2274{
2275 if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
2276 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2277 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2278 if (hcr.e2h) {
2279 if (ArmSystem::haveEL(tc, EL3) && !scr.tcr2En) {
2280 return inst.generateTrap(EL3);
2281 } else {
2282 return NoFault;
2283 }
2284 } else {
2285 return inst.undefined();
2286 }
2287 } else {
2288 return inst.undefined();
2289 }
2290}
2291
2292Fault
2293faultTcr2VheEL3(const MiscRegLUTEntry &entry,
2294 ThreadContext *tc, const MiscRegOp64 &inst)
2295{
2296 if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
2297 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2298 const bool el2_host = EL2Enabled(tc) && hcr.e2h;
2299 if (el2_host) {
2300 return NoFault;
2301 } else {
2302 return inst.undefined();
2303 }
2304 } else {
2305 return inst.undefined();
2306 }
2307}
2308
2309template<bool read, auto r_bitfield>
2310Fault
2311faultCpacrEL1(const MiscRegLUTEntry &entry,
2312 ThreadContext *tc, const MiscRegOp64 &inst)
2313{
2314 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2315 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2316
2317 const bool el2_enabled = EL2Enabled(tc);
2318 if (el2_enabled && cptr_el2.tcpac) {
2319 return inst.generateTrap(EL2);
2320 } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
2321 fault != NoFault) {
2322 return fault;
2323 } else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
2324 return inst.generateTrap(EL3);
2325 } else {
2326 return NoFault;
2327 }
2328}
2329
2330Fault
2331faultCpacrEL2(const MiscRegLUTEntry &entry,
2332 ThreadContext *tc, const MiscRegOp64 &inst)
2333{
2334 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2335 if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tcpac) {
2336 return inst.generateTrap(EL3);
2337 } else {
2338 return NoFault;
2339 }
2340}
2341
2342Fault
2343faultCpacrVheEL2(const MiscRegLUTEntry &entry,
2344 ThreadContext *tc, const MiscRegOp64 &inst)
2345{
2346 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2347 if (hcr.e2h) {
2348 return faultCpacrEL2(entry, tc, inst);
2349 } else {
2350 return inst.undefined();
2351 }
2352}
2353
2354template <auto bitfield>
2355Fault
2356faultTlbiOsEL1(const MiscRegLUTEntry &entry,
2357 ThreadContext *tc, const MiscRegOp64 &inst)
2358{
2359 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2360 const bool el2_enabled = EL2Enabled(tc);
2361 if (el2_enabled && hcr.ttlb) {
2362 return inst.generateTrap(EL2);
2363 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
2364 hcr.ttlbos) {
2365 return inst.generateTrap(EL2);
2366 } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
2367 fault != NoFault) {
2368 return fault;
2369 } else {
2370 return NoFault;
2371 }
2372}
2373
2374template <auto bitfield>
2375Fault
2376faultTlbiOsNxsEL1(const MiscRegLUTEntry &entry,
2377 ThreadContext *tc, const MiscRegOp64 &inst)
2378{
2379 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2380 const bool el2_enabled = EL2Enabled(tc);
2381 if (el2_enabled && hcr.ttlb) {
2382 return inst.generateTrap(EL2);
2383 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
2384 hcr.ttlbos) {
2385 return inst.generateTrap(EL2);
2386 } else if (auto fault = faultFgtTlbiNxsEL1<bitfield>(entry, tc, inst);
2387 fault != NoFault) {
2388 return fault;
2389 } else {
2390 return NoFault;
2391 }
2392}
2393
2394template <auto bitfield>
2395Fault
2396faultTlbiIsEL1(const MiscRegLUTEntry &entry,
2397 ThreadContext *tc, const MiscRegOp64 &inst)
2398{
2399 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2400 const bool el2_enabled = EL2Enabled(tc);
2401 if (el2_enabled && hcr.ttlb) {
2402 return inst.generateTrap(EL2);
2403 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
2404 hcr.ttlbis) {
2405 return inst.generateTrap(EL2);
2406 } else if (auto fault = faultFgtInstEL1<bitfield>(entry, tc, inst);
2407 fault != NoFault) {
2408 return fault;
2409 } else {
2410 return NoFault;
2411 }
2412}
2413
2414template <auto bitfield>
2415Fault
2416faultTlbiIsNxsEL1(const MiscRegLUTEntry &entry,
2417 ThreadContext *tc, const MiscRegOp64 &inst)
2418{
2419 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2420 const bool el2_enabled = EL2Enabled(tc);
2421 if (el2_enabled && hcr.ttlb) {
2422 return inst.generateTrap(EL2);
2423 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
2424 hcr.ttlbis) {
2425 return inst.generateTrap(EL2);
2426 } else if (auto fault = faultFgtTlbiNxsEL1<bitfield>(entry, tc, inst);
2427 fault != NoFault) {
2428 return fault;
2429 } else {
2430 return NoFault;
2431 }
2432}
2433
2434template <bool read, auto r_bitfield>
2435Fault
2436faultCacheEL1(const MiscRegLUTEntry &entry,
2437 ThreadContext *tc, const MiscRegOp64 &inst)
2438{
2439 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2440 const bool el2_enabled = EL2Enabled(tc);
2441 if (el2_enabled && hcr.tid2) {
2442 return inst.generateTrap(EL2);
2443 } else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
2444 hcr.tid4) {
2445 return inst.generateTrap(EL2);
2446 } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
2447 fault != NoFault) {
2448 return fault;
2449 } else {
2450 return NoFault;
2451 }
2452}
2453
2454template <bool read, auto r_bitfield>
2455Fault
2456faultPauthEL1(const MiscRegLUTEntry &entry,
2457 ThreadContext *tc, const MiscRegOp64 &inst)
2458{
2459 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2460 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2461 const bool el2_enabled = EL2Enabled(tc);
2462
2463 if (el2_enabled && !hcr.apk) {
2464 return inst.generateTrap(EL2);
2465 } else if (auto fault = faultFgtEL1<read, r_bitfield>(entry, tc, inst);
2466 fault != NoFault) {
2467 return fault;
2468 } else if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
2469 return inst.generateTrap(EL3);
2470 } else {
2471 return NoFault;
2472 }
2473}
2474
2475Fault
2476faultPauthEL2(const MiscRegLUTEntry &entry,
2477 ThreadContext *tc, const MiscRegOp64 &inst)
2478{
2479 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2480 if (ArmSystem::haveEL(tc, EL3) && !scr.apk) {
2481 return inst.generateTrap(EL3);
2482 } else {
2483 return NoFault;
2484 }
2485}
2486
2487Fault
2488faultGenericTimerEL0(const MiscRegLUTEntry &entry,
2489 ThreadContext *tc, const MiscRegOp64 &inst)
2490{
2491 const bool el2_enabled = EL2Enabled(tc);
2492 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2493 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
2494 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
2495 const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2496 if (!(in_host) && !cntkctl_el1.el0pcten && !cntkctl_el1.el0vcten) {
2497 if (el2_enabled && hcr.tge)
2498 return inst.generateTrap(EL2);
2499 else
2500 return inst.generateTrap(EL1);
2501 } else if (in_host && !cnthctl_el2.el0pcten && !cnthctl_el2.el0vcten) {
2502 return inst.generateTrap(EL2);
2503 } else {
2504 return NoFault;
2505 }
2506}
2507
2508Fault
2509faultCntpctEL0(const MiscRegLUTEntry &entry,
2510 ThreadContext *tc, const MiscRegOp64 &inst)
2511{
2512 const bool el2_enabled = EL2Enabled(tc);
2513 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2514 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
2515 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
2516 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2517 if (!(in_host) && !cntkctl_el1.el0pcten) {
2518 if (el2_enabled && hcr.tge)
2519 return inst.generateTrap(EL2);
2520 else
2521 return inst.generateTrap(EL1);
2522 } else if (el2_enabled && !hcr.e2h &&
2523 !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
2524 return inst.generateTrap(EL2);
2525 } else if (el2_enabled && hcr.e2h && !hcr.tge &&
2526 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
2527 return inst.generateTrap(EL2);
2528 } else if (in_host &&
2529 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pcten) {
2530 return inst.generateTrap(EL2);
2531 } else {
2532 return NoFault;
2533 }
2534}
2535
2536Fault
2537faultCntpctEL1(const MiscRegLUTEntry &entry,
2538 ThreadContext *tc, const MiscRegOp64 &inst)
2539{
2540 const bool el2_enabled = EL2Enabled(tc);
2541 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2542 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2543 if (el2_enabled && hcr.e2h &&
2544 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pcten) {
2545 return inst.generateTrap(EL2);
2546 } else if (el2_enabled && !hcr.e2h &&
2547 !static_cast<CNTHCTL>(cnthctl_el2).el1pcten) {
2548 return inst.generateTrap(EL2);
2549 } else {
2550 return NoFault;
2551 }
2552}
2553
2554Fault
2555faultCntvctEL0(const MiscRegLUTEntry &entry,
2556 ThreadContext *tc, const MiscRegOp64 &inst)
2557{
2558 const bool el2_enabled = EL2Enabled(tc);
2559 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2560 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
2561 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
2562 const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2563 if (!(in_host) && !cntkctl_el1.el0vcten) {
2564 if (el2_enabled && hcr.tge)
2565 return inst.generateTrap(EL2);
2566 else
2567 return inst.generateTrap(EL1);
2568 } else if (in_host && !cnthctl_el2.el0vcten) {
2569 return inst.generateTrap(EL2);
2570 } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvct) {
2571 return inst.generateTrap(EL2);
2572 } else {
2573 return NoFault;
2574 }
2575}
2576
2577Fault
2578faultCntvctEL1(const MiscRegLUTEntry &entry,
2579 ThreadContext *tc, const MiscRegOp64 &inst)
2580{
2581 const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2582 if (EL2Enabled(tc) && cnthctl_el2.el1tvct) {
2583 return inst.generateTrap(EL2);
2584 } else {
2585 return NoFault;
2586 }
2587}
2588
2589//TODO: See faultCntpctEL0
2590Fault
2591faultCntpCtlEL0(const MiscRegLUTEntry &entry,
2592 ThreadContext *tc, const MiscRegOp64 &inst)
2593{
2594 const bool el2_enabled = EL2Enabled(tc);
2595 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2596 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
2597 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
2598 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2599 if (!(in_host) && !cntkctl_el1.el0pten) {
2600 if (el2_enabled && hcr.tge)
2601 return inst.generateTrap(EL2);
2602 else
2603 return inst.generateTrap(EL1);
2604 } else if (el2_enabled && !hcr.e2h &&
2605 !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
2606 return inst.generateTrap(EL2);
2607 } else if (el2_enabled && hcr.e2h && !hcr.tge &&
2608 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
2609 return inst.generateTrap(EL2);
2610 } else if (in_host &&
2611 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el0pten) {
2612 return inst.generateTrap(EL2);
2613 } else {
2614 return NoFault;
2615 }
2616}
2617
2618Fault
2619faultCntpCtlEL1(const MiscRegLUTEntry &entry,
2620 ThreadContext *tc, const MiscRegOp64 &inst)
2621{
2622 const bool el2_enabled = EL2Enabled(tc);
2623 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2624 const RegVal cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2625 if (el2_enabled && !hcr.e2h &&
2626 !static_cast<CNTHCTL>(cnthctl_el2).el1pcen) {
2627 return inst.generateTrap(EL2);
2628 } else if (el2_enabled && hcr.e2h &&
2629 !static_cast<CNTHCTL_E2H>(cnthctl_el2).el1pten) {
2630 return inst.generateTrap(EL2);
2631 } else {
2632 return NoFault;
2633 }
2634}
2635
2636// TODO: see faultCntvctEL0
2637Fault
2638faultCntvCtlEL0(const MiscRegLUTEntry &entry,
2639 ThreadContext *tc, const MiscRegOp64 &inst)
2640{
2641 const bool el2_enabled = EL2Enabled(tc);
2642 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2643 const bool in_host = el2_enabled && hcr.e2h && hcr.tge;
2644 const CNTKCTL cntkctl_el1 = tc->readMiscReg(MISCREG_CNTKCTL_EL1);
2645 const CNTHCTL_E2H cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2646 if (!(in_host) && !cntkctl_el1.el0vten) {
2647 if (el2_enabled && hcr.tge)
2648 return inst.generateTrap(EL2);
2649 else
2650 return inst.generateTrap(EL1);
2651 } else if (in_host && !cnthctl_el2.el0vten) {
2652 return inst.generateTrap(EL2);
2653 } else if (el2_enabled && !(hcr.e2h && hcr.tge) && cnthctl_el2.el1tvt) {
2654 return inst.generateTrap(EL2);
2655 } else {
2656 return NoFault;
2657 }
2658}
2659
2660Fault
2661faultCntvCtlEL1(const MiscRegLUTEntry &entry,
2662 ThreadContext *tc, const MiscRegOp64 &inst)
2663{
2664 const CNTHCTL cnthctl_el2 = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
2665 if (EL2Enabled(tc) && cnthctl_el2.el1tvt) {
2666 return inst.generateTrap(EL2);
2667 } else {
2668 return NoFault;
2669 }
2670}
2671
2672Fault
2673faultCntpsCtlEL1(const MiscRegLUTEntry &entry,
2674 ThreadContext *tc, const MiscRegOp64 &inst)
2675{
2676 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2677 if (ArmSystem::haveEL(tc, EL3) && !scr.ns) {
2678 if (scr.eel2)
2679 return inst.undefined();
2680 else if (!scr.st)
2681 return inst.generateTrap(EL3);
2682 else
2683 return NoFault;
2684 } else {
2685 return inst.undefined();
2686 }
2687}
2688
2689Fault
2690faultUnimplemented(const MiscRegLUTEntry &entry,
2691 ThreadContext *tc, const MiscRegOp64 &inst)
2692{
2693 if (entry.info[MISCREG_WARN_NOT_FAIL]) {
2694 return NoFault;
2695 } else {
2696 return inst.undefined();
2697 }
2698}
2699
2700Fault
2701faultImpdefUnimplEL1(const MiscRegLUTEntry &entry,
2702 ThreadContext *tc, const MiscRegOp64 &inst)
2703{
2704 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2705 if (EL2Enabled(tc) && hcr.tidcp) {
2706 return inst.generateTrap(EL2);
2707 } else {
2708 return faultUnimplemented(entry, tc, inst);
2709 }
2710}
2711
2712Fault
2713faultEsm(const MiscRegLUTEntry &entry,
2714 ThreadContext *tc, const MiscRegOp64 &inst)
2715{
2716 const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
2717 if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.esm) {
2718 return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SME, 0);
2719 } else {
2720 return NoFault;
2721 }
2722}
2723
2724Fault
2725faultTsmSmen(const MiscRegLUTEntry &entry,
2726 ThreadContext *tc, const MiscRegOp64 &inst)
2727{
2728 const HCR hcr_el2 = tc->readMiscReg(MISCREG_HCR_EL2);
2729 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2730 const bool el2_enabled = EL2Enabled(tc);
2731 if (el2_enabled && !hcr_el2.e2h && cptr_el2.tsm) {
2732 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2733 } else if (el2_enabled && hcr_el2.e2h && !(cptr_el2.smen & 0b1)) {
2734 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2735 } else {
2736 return faultEsm(entry, tc, inst);
2737 }
2738}
2739
2740Fault
2741faultSmenEL1(const MiscRegLUTEntry &entry,
2742 ThreadContext *tc, const MiscRegOp64 &inst)
2743{
2744 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
2745 if (!(cpacr.smen & 0b1)) {
2746 return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
2747 } else {
2748 return faultTsmSmen(entry, tc, inst);
2749 }
2750}
2751
2752Fault
2753faultSmenEL0(const MiscRegLUTEntry &entry,
2754 ThreadContext *tc, const MiscRegOp64 &inst)
2755{
2756 const bool el2_enabled = EL2Enabled(tc);
2757 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2758 const bool in_host = hcr.e2h && hcr.tge;
2759
2760 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
2761 const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
2762 if (!(el2_enabled && in_host) && cpacr.smen != 0b11) {
2763 if (el2_enabled && hcr.tge)
2764 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2765 else
2766 return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
2767 } else if (el2_enabled && in_host && cptr_el2.smen != 0b11) {
2768 return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
2769 } else {
2770 return faultTsmSmen(entry, tc, inst);
2771 }
2772}
2773
2774Fault
2775faultRng(const MiscRegLUTEntry &entry,
2776 ThreadContext *tc, const MiscRegOp64 &inst)
2777{
2778 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2779 if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
2780 return inst.generateTrap(EL3);
2781 } else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
2782 return inst.undefined();
2783 } else {
2784 return NoFault;
2785 }
2786}
2787
2788Fault
2789faultFgtCtrlRegs(const MiscRegLUTEntry &entry,
2790 ThreadContext *tc, const MiscRegOp64 &inst)
2791{
2792 if (HaveExt(tc, ArmExtension::FEAT_FGT)) {
2793 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
2794 if (ArmSystem::haveEL(tc, EL3) && !scr.fgten) {
2795 return inst.generateTrap(EL3);
2796 } else {
2797 return NoFault;
2798 }
2799 } else {
2800 return inst.undefined();
2801 }
2802}
2803
2804Fault
2805faultIdst(const MiscRegLUTEntry &entry,
2806 ThreadContext *tc, const MiscRegOp64 &inst)
2807{
2808 if (HaveExt(tc, ArmExtension::FEAT_IDST)) {
2809 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
2810 if (EL2Enabled(tc) && hcr.tge) {
2811 return inst.generateTrap(EL2);
2812 } else {
2813 return inst.generateTrap(EL1);
2814 }
2815 } else {
2816 return inst.undefined();
2817 }
2818}
2819
2820Fault
2821faultMpamIdrEL1(const MiscRegLUTEntry &entry,
2822 ThreadContext *tc, const MiscRegOp64 &inst)
2823{
2824 if (HaveExt(tc, ArmExtension::FEAT_MPAM)) {
2825 MPAM mpam2 = tc->readMiscReg(MISCREG_MPAM2_EL2);
2826 MPAM mpam3 = tc->readMiscReg(MISCREG_MPAM3_EL3);
2827 MPAMIDR mpamidr = tc->readMiscReg(MISCREG_MPAMIDR_EL1);
2828 MPAMHCR mpamhcr = tc->readMiscReg(MISCREG_MPAMHCR_EL2);
2829 if (ArmSystem::haveEL(tc, EL3) && mpam3.el3.trapLower) {
2830 return inst.generateTrap(EL3);
2831 } else if (EL2Enabled(tc) && mpamidr.hasHcr && mpamhcr.trapMpamIdrEL1) {
2832 return inst.generateTrap(EL2);
2833 } else if (EL2Enabled(tc) && mpamidr.hasTidr && mpam2.el2.tidr) {
2834 return inst.generateTrap(EL2);
2835 } else {
2836 return NoFault;
2837 }
2838 } else {
2839 return inst.undefined();
2840 }
2841}
2842
2843Fault
2844faultMpam0EL1(const MiscRegLUTEntry &entry,
2845 ThreadContext *tc, const MiscRegOp64 &inst)
2846{
2847 if (HaveExt(tc, ArmExtension::FEAT_MPAM)) {
2848 MPAM mpam2 = tc->readMiscReg(MISCREG_MPAM2_EL2);
2849 MPAM mpam3 = tc->readMiscReg(MISCREG_MPAM3_EL3);
2850 if (ArmSystem::haveEL(tc, EL3) && mpam3.el3.trapLower) {
2851 return inst.generateTrap(EL3);
2852 } else if (EL2Enabled(tc) && mpam2.el2.trapMpam0EL1) {
2853 return inst.generateTrap(EL2);
2854 } else {
2855 return NoFault;
2856 }
2857 } else {
2858 return inst.undefined();
2859 }
2860}
2861
2862Fault
2863faultMpam1EL1(const MiscRegLUTEntry &entry,
2864 ThreadContext *tc, const MiscRegOp64 &inst)
2865{
2866 if (HaveExt(tc, ArmExtension::FEAT_MPAM)) {
2867 MPAM mpam2 = tc->readMiscReg(MISCREG_MPAM2_EL2);
2868 MPAM mpam3 = tc->readMiscReg(MISCREG_MPAM3_EL3);
2869 if (ArmSystem::haveEL(tc, EL3) && mpam3.el3.trapLower) {
2870 return inst.generateTrap(EL3);
2871 } else if (EL2Enabled(tc) && mpam2.el2.trapMpam1EL1) {
2872 return inst.generateTrap(EL2);
2873 } else {
2874 return NoFault;
2875 }
2876 } else {
2877 return inst.undefined();
2878 }
2879}
2880
2881Fault
2882faultMpamEL2(const MiscRegLUTEntry &entry,
2883 ThreadContext *tc, const MiscRegOp64 &inst)
2884{
2885 if (HaveExt(tc, ArmExtension::FEAT_MPAM)) {
2886 MPAM mpam3 = tc->readMiscReg(MISCREG_MPAM3_EL3);
2887 if (ArmSystem::haveEL(tc, EL3) && mpam3.el3.trapLower) {
2888 return inst.generateTrap(EL3);
2889 } else {
2890 return NoFault;
2891 }
2892 } else {
2893 return inst.undefined();
2894 }
2895}
2896
2897Fault
2898faultMpam12EL2(const MiscRegLUTEntry &entry,
2899 ThreadContext *tc, const MiscRegOp64 &inst)
2900{
2901 if (ELIsInHost(tc, EL2)) {
2902 return faultMpamEL2(entry, tc, inst);
2903 } else {
2904 return inst.undefined();
2905 }
2906}
2907
2908Fault
2909faultMpamsmEL1(const MiscRegLUTEntry &entry,
2910 ThreadContext *tc, const MiscRegOp64 &inst)
2911{
2912 if (HaveExt(tc, ArmExtension::FEAT_MPAM)) {
2913 MPAM mpam2 = tc->readMiscReg(MISCREG_MPAM2_EL2);
2914 MPAM mpam3 = tc->readMiscReg(MISCREG_MPAM3_EL3);
2915 if (ArmSystem::haveEL(tc, EL3) && mpam3.el3.trapLower) {
2916 return inst.generateTrap(EL3);
2917 } else if (EL2Enabled(tc) && mpam2.el2.enMpamSm) {
2918 return inst.generateTrap(EL2);
2919 } else {
2920 return NoFault;
2921 }
2922 } else {
2923 return inst.undefined();
2924 }
2925}
2926
2927}
2928
2929MiscRegIndex
2930decodeAArch64SysReg(unsigned op0, unsigned op1,
2931 unsigned crn, unsigned crm,
2932 unsigned op2)
2933{
2934 MiscRegNum64 sys_reg(op0, op1, crn, crm, op2);
2935 return decodeAArch64SysReg(sys_reg);
2936}
2937
2938MiscRegIndex
2939decodeAArch64SysReg(const MiscRegNum64 &sys_reg)
2940{
2941 auto it = miscRegNumToIdx.find(sys_reg);
2942 if (it != miscRegNumToIdx.end()) {
2943 return it->second;
2944 } else {
2945 // Check for a pseudo register before returning MISCREG_UNKNOWN
2946 if ((sys_reg.op0 == 1 || sys_reg.op0 == 3) &&
2947 (sys_reg.crn == 11 || sys_reg.crn == 15)) {
2948 return MISCREG_IMPDEF_UNIMPL;
2949 } else {
2950 return MISCREG_UNKNOWN;
2951 }
2952 }
2953}
2954
2955std::optional<MiscRegNum64>
2956encodeAArch64SysReg(MiscRegIndex misc_reg)
2957{
2958 if (auto it = idxToMiscRegNum.find(misc_reg);
2959 it != idxToMiscRegNum.end()) {
2960 return it->second;
2961 } else {
2962 return std::nullopt;
2963 }
2964}
2965
2966Fault
2967MiscRegLUTEntry::checkFault(ThreadContext *tc,
2968 const MiscRegOp64 &inst, ExceptionLevel el)
2969{
2970 return !inst.miscRead() ? faultWrite[el](*this, tc, inst) :
2971 faultRead[el](*this, tc, inst);
2972}
2973
2974template <MiscRegInfo Sec, MiscRegInfo NonSec>
2975Fault
2976MiscRegLUTEntry::defaultFault(const MiscRegLUTEntry &entry,
2977 ThreadContext *tc, const MiscRegOp64 &inst)
2978{
2979 if (isSecureBelowEL3(tc) ? entry.info[Sec] : entry.info[NonSec]) {
2980 return NoFault;
2981 } else {
2982 return inst.undefined();
2983 }
2984}
2985
2986static Fault
2987defaultFaultE2H_EL2(const MiscRegLUTEntry &entry,
2988 ThreadContext *tc, const MiscRegOp64 &inst)
2989{
2990 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
2991 if (hcr.e2h) {
2992 return NoFault;
2993 } else {
2994 return inst.undefined();
2995 }
2996}
2997
2998static Fault
2999defaultFaultE2H_EL3(const MiscRegLUTEntry &entry,
3000 ThreadContext *tc, const MiscRegOp64 &inst)
3001{
3002 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
3003 const bool el2_host = EL2Enabled(tc) && hcr.e2h;
3004 if (el2_host) {
3005 return NoFault;
3006 } else {
3007 return inst.undefined();
3008 }
3009}
3010
3011MiscRegLUTEntryInitializer::chain
3012MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
3013{
3014 switch (FullSystem ? sys->highestEL() : EL1) {
3015 case EL0:
3016 case EL1: priv(); break;
3017 case EL2: hyp(); break;
3018 case EL3: mon(); break;
3019 }
3020 return *this;
3021}
3022
3023static CPSR
3024resetCPSR(ArmSystem *system)
3025{
3026 CPSR cpsr = 0;
3027 if (!FullSystem) {
3028 cpsr.mode = MODE_USER;
3029 } else {
3030 switch (system->highestEL()) {
3031 // Set initial EL to highest implemented EL using associated stack
3032 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
3033 // value
3034 case EL3:
3035 cpsr.mode = MODE_EL3H;
3036 break;
3037 case EL2:
3038 cpsr.mode = MODE_EL2H;
3039 break;
3040 case EL1:
3041 cpsr.mode = MODE_EL1H;
3042 break;
3043 default:
3044 panic("Invalid highest implemented exception level");
3045 break;
3046 }
3047
3048 // Initialize rest of CPSR
3049 cpsr.daif = 0xf; // Mask all interrupts
3050 cpsr.ss = 0;
3051 cpsr.il = 0;
3052 }
3053 return cpsr;
3054}
3055
3056void
3057ISA::initializeMiscRegMetadata()
3058{
3059 // the MiscReg metadata tables are shared across all instances of the
3060 // ISA object, so there's no need to initialize them multiple times.
3061 static bool completed = false;
3062 if (completed)
3063 return;
3064
3065 // This boolean variable specifies if the system is running in aarch32 at
3066 // EL3 (aarch32EL3 = true). It is false if EL3 is not implemented, or it
3067 // is running in aarch64 (aarch32EL3 = false)
3068 bool aarch32EL3 = release->has(ArmExtension::SECURITY) && !highestELIs64;
3069
3070 // Set Privileged Access Never on taking an exception to EL1 (Arm 8.1+),
3071 // unsupported
3072 bool SPAN = false;
3073
3074 // Implicit error synchronization event enable (Arm 8.2+), unsupported
3075 bool IESB = false;
3076
3077 // Load Multiple and Store Multiple Atomicity and Ordering (Arm 8.2+),
3078 // unsupported
3079 bool LSMAOE = false;
3080
3081 // No Trap Load Multiple and Store Multiple (Arm 8.2+), unsupported
3082 bool nTLSMD = false;
3083
3084 // Pointer authentication (Arm 8.3+), unsupported
3085 bool EnDA = true; // using APDAKey_EL1 key of instr addrs in ELs 0,1
3086 bool EnDB = true; // using APDBKey_EL1 key of instr addrs in ELs 0,1
3087 bool EnIA = true; // using APIAKey_EL1 key of instr addrs in ELs 0,1
3088 bool EnIB = true; // using APIBKey_EL1 key of instr addrs in ELs 0,1
3089
3090 const bool vhe_implemented = release->has(ArmExtension::FEAT_VHE);
3091 const bool sel2_implemented = release->has(ArmExtension::FEAT_SEL2);
3092
3093 const Params &p(params());
3094
3095 uint32_t midr;
3096 if (p.midr != 0x0)
3097 midr = p.midr;
3098 else if (highestELIs64)
3099 // Cortex-A57 TRM r0p0 MIDR
3100 midr = 0x410fd070;
3101 else
3102 // Cortex-A15 TRM r0p0 MIDR
3103 midr = 0x410fc0f0;
3104
3118 InitReg(MISCREG_CPSR)
3119 .reset(resetCPSR(system))
3120 .allPrivileges();
3121 InitReg(MISCREG_SPSR)
3122 .allPrivileges();
3123 InitReg(MISCREG_SPSR_FIQ)
3124 .allPrivileges();
3125 InitReg(MISCREG_SPSR_IRQ)
3126 .allPrivileges();
3127 InitReg(MISCREG_SPSR_SVC)
3128 .allPrivileges();
3129 InitReg(MISCREG_SPSR_MON)
3130 .allPrivileges();
3131 InitReg(MISCREG_SPSR_ABT)
3132 .allPrivileges();
3133 InitReg(MISCREG_SPSR_HYP)
3134 .allPrivileges();
3135 InitReg(MISCREG_SPSR_UND)
3136 .allPrivileges();
3137 InitReg(MISCREG_ELR_HYP)
3138 .allPrivileges();
3139 InitReg(MISCREG_FPSID)
3140 .reset(p.fpsid)
3141 .allPrivileges();
3142 InitReg(MISCREG_FPSCR)
3143 .res0(mask(14, 13) | mask(6, 5))
3144 .allPrivileges();
3145 InitReg(MISCREG_MVFR1)
3146 .reset([] () {
3147 MVFR1 mvfr1 = 0;
3148 mvfr1.flushToZero = 1;
3149 mvfr1.defaultNaN = 1;
3150 mvfr1.advSimdLoadStore = 1;
3151 mvfr1.advSimdInteger = 1;
3152 mvfr1.advSimdSinglePrecision = 1;
3153 mvfr1.advSimdHalfPrecision = 1;
3154 mvfr1.vfpHalfPrecision = 1;
3155 return mvfr1;
3156 }())
3157 .allPrivileges();
3158 InitReg(MISCREG_MVFR0)
3159 .reset([] () {
3160 MVFR0 mvfr0 = 0;
3161 mvfr0.advSimdRegisters = 2;
3162 mvfr0.singlePrecision = 2;
3163 mvfr0.doublePrecision = 2;
3164 mvfr0.vfpExceptionTrapping = 0;
3165 mvfr0.divide = 1;
3166 mvfr0.squareRoot = 1;
3167 mvfr0.shortVectors = 1;
3168 mvfr0.roundingModes = 1;
3169 return mvfr0;
3170 }())
3171 .allPrivileges();
3172 InitReg(MISCREG_FPEXC)
3173 .allPrivileges();
3174
3175 // Helper registers
3176 InitReg(MISCREG_CPSR_MODE)
3177 .allPrivileges();
3178 InitReg(MISCREG_CPSR_Q)
3179 .allPrivileges();
3180 InitReg(MISCREG_FPSCR_EXC)
3181 .allPrivileges();
3182 InitReg(MISCREG_FPSCR_QC)
3183 .allPrivileges();
3184 InitReg(MISCREG_LOCKADDR)
3185 .allPrivileges();
3186 InitReg(MISCREG_LOCKFLAG)
3187 .allPrivileges();
3188 InitReg(MISCREG_PRRR_MAIR0)
3189 .mutex()
3190 .banked();
3191 InitReg(MISCREG_PRRR_MAIR0_NS)
3192 .mutex()
3193 .privSecure(!aarch32EL3)
3194 .bankedChild();
3195 InitReg(MISCREG_PRRR_MAIR0_S)
3196 .mutex()
3197 .bankedChild();
3198 InitReg(MISCREG_NMRR_MAIR1)
3199 .mutex()
3200 .banked();
3201 InitReg(MISCREG_NMRR_MAIR1_NS)
3202 .mutex()
3203 .privSecure(!aarch32EL3)
3204 .bankedChild();
3205 InitReg(MISCREG_NMRR_MAIR1_S)
3206 .mutex()
3207 .bankedChild();
3208 InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
3209 .mutex();
3210 InitReg(MISCREG_SEV_MAILBOX)
3211 .reset(1) // Start with an event in the mailbox
3212 .allPrivileges();
3213 InitReg(MISCREG_TLBINEEDSYNC)
3214 .allPrivileges().exceptUserMode();
3215
3216 // AArch32 CP14 registers
3217 InitReg(MISCREG_DBGDIDR)
3218 .reset(0x6 << 16) // Armv8 Debug architecture
3219 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3220 InitReg(MISCREG_DBGDSCRint)
3221 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3222 InitReg(MISCREG_DBGDCCINT)
3223 .unimplemented()
3224 .allPrivileges();
3225 InitReg(MISCREG_DBGDTRTXint)
3226 .unimplemented()
3227 .allPrivileges();
3228 InitReg(MISCREG_DBGDTRRXint)
3229 .unimplemented()
3230 .allPrivileges();
3231 InitReg(MISCREG_DBGWFAR)
3232 .unimplemented()
3233 .allPrivileges();
3234 InitReg(MISCREG_DBGVCR)
3235 .allPrivileges().exceptUserMode();
3236 InitReg(MISCREG_DBGDTRRXext)
3237 .unimplemented()
3238 .allPrivileges();
3239 InitReg(MISCREG_DBGDSCRext)
3240 .allPrivileges();
3241 InitReg(MISCREG_DBGDTRTXext)
3242 .unimplemented()
3243 .allPrivileges();
3244 InitReg(MISCREG_DBGOSECCR)
3245 .unimplemented()
3246 .allPrivileges();
3247 InitReg(MISCREG_DBGBVR0)
3248 .allPrivileges().exceptUserMode();
3249 InitReg(MISCREG_DBGBVR1)
3250 .allPrivileges().exceptUserMode();
3251 InitReg(MISCREG_DBGBVR2)
3252 .allPrivileges().exceptUserMode();
3253 InitReg(MISCREG_DBGBVR3)
3254 .allPrivileges().exceptUserMode();
3255 InitReg(MISCREG_DBGBVR4)
3256 .allPrivileges().exceptUserMode();
3257 InitReg(MISCREG_DBGBVR5)
3258 .allPrivileges().exceptUserMode();
3259 InitReg(MISCREG_DBGBVR6)
3260 .allPrivileges().exceptUserMode();
3261 InitReg(MISCREG_DBGBVR7)
3262 .allPrivileges().exceptUserMode();
3263 InitReg(MISCREG_DBGBVR8)
3264 .allPrivileges().exceptUserMode();
3265 InitReg(MISCREG_DBGBVR9)
3266 .allPrivileges().exceptUserMode();
3267 InitReg(MISCREG_DBGBVR10)
3268 .allPrivileges().exceptUserMode();
3269 InitReg(MISCREG_DBGBVR11)
3270 .allPrivileges().exceptUserMode();
3271 InitReg(MISCREG_DBGBVR12)
3272 .allPrivileges().exceptUserMode();
3273 InitReg(MISCREG_DBGBVR13)
3274 .allPrivileges().exceptUserMode();
3275 InitReg(MISCREG_DBGBVR14)
3276 .allPrivileges().exceptUserMode();
3277 InitReg(MISCREG_DBGBVR15)
3278 .allPrivileges().exceptUserMode();
3279 InitReg(MISCREG_DBGBCR0)
3280 .allPrivileges().exceptUserMode();
3281 InitReg(MISCREG_DBGBCR1)
3282 .allPrivileges().exceptUserMode();
3283 InitReg(MISCREG_DBGBCR2)
3284 .allPrivileges().exceptUserMode();
3285 InitReg(MISCREG_DBGBCR3)
3286 .allPrivileges().exceptUserMode();
3287 InitReg(MISCREG_DBGBCR4)
3288 .allPrivileges().exceptUserMode();
3289 InitReg(MISCREG_DBGBCR5)
3290 .allPrivileges().exceptUserMode();
3291 InitReg(MISCREG_DBGBCR6)
3292 .allPrivileges().exceptUserMode();
3293 InitReg(MISCREG_DBGBCR7)
3294 .allPrivileges().exceptUserMode();
3295 InitReg(MISCREG_DBGBCR8)
3296 .allPrivileges().exceptUserMode();
3297 InitReg(MISCREG_DBGBCR9)
3298 .allPrivileges().exceptUserMode();
3299 InitReg(MISCREG_DBGBCR10)
3300 .allPrivileges().exceptUserMode();
3301 InitReg(MISCREG_DBGBCR11)
3302 .allPrivileges().exceptUserMode();
3303 InitReg(MISCREG_DBGBCR12)
3304 .allPrivileges().exceptUserMode();
3305 InitReg(MISCREG_DBGBCR13)
3306 .allPrivileges().exceptUserMode();
3307 InitReg(MISCREG_DBGBCR14)
3308 .allPrivileges().exceptUserMode();
3309 InitReg(MISCREG_DBGBCR15)
3310 .allPrivileges().exceptUserMode();
3311 InitReg(MISCREG_DBGWVR0)
3312 .allPrivileges().exceptUserMode();
3313 InitReg(MISCREG_DBGWVR1)
3314 .allPrivileges().exceptUserMode();
3315 InitReg(MISCREG_DBGWVR2)
3316 .allPrivileges().exceptUserMode();
3317 InitReg(MISCREG_DBGWVR3)
3318 .allPrivileges().exceptUserMode();
3319 InitReg(MISCREG_DBGWVR4)
3320 .allPrivileges().exceptUserMode();
3321 InitReg(MISCREG_DBGWVR5)
3322 .allPrivileges().exceptUserMode();
3323 InitReg(MISCREG_DBGWVR6)
3324 .allPrivileges().exceptUserMode();
3325 InitReg(MISCREG_DBGWVR7)
3326 .allPrivileges().exceptUserMode();
3327 InitReg(MISCREG_DBGWVR8)
3328 .allPrivileges().exceptUserMode();
3329 InitReg(MISCREG_DBGWVR9)
3330 .allPrivileges().exceptUserMode();
3331 InitReg(MISCREG_DBGWVR10)
3332 .allPrivileges().exceptUserMode();
3333 InitReg(MISCREG_DBGWVR11)
3334 .allPrivileges().exceptUserMode();
3335 InitReg(MISCREG_DBGWVR12)
3336 .allPrivileges().exceptUserMode();
3337 InitReg(MISCREG_DBGWVR13)
3338 .allPrivileges().exceptUserMode();
3339 InitReg(MISCREG_DBGWVR14)
3340 .allPrivileges().exceptUserMode();
3341 InitReg(MISCREG_DBGWVR15)
3342 .allPrivileges().exceptUserMode();
3343 InitReg(MISCREG_DBGWCR0)
3344 .allPrivileges().exceptUserMode();
3345 InitReg(MISCREG_DBGWCR1)
3346 .allPrivileges().exceptUserMode();
3347 InitReg(MISCREG_DBGWCR2)
3348 .allPrivileges().exceptUserMode();
3349 InitReg(MISCREG_DBGWCR3)
3350 .allPrivileges().exceptUserMode();
3351 InitReg(MISCREG_DBGWCR4)
3352 .allPrivileges().exceptUserMode();
3353 InitReg(MISCREG_DBGWCR5)
3354 .allPrivileges().exceptUserMode();
3355 InitReg(MISCREG_DBGWCR6)
3356 .allPrivileges().exceptUserMode();
3357 InitReg(MISCREG_DBGWCR7)
3358 .allPrivileges().exceptUserMode();
3359 InitReg(MISCREG_DBGWCR8)
3360 .allPrivileges().exceptUserMode();
3361 InitReg(MISCREG_DBGWCR9)
3362 .allPrivileges().exceptUserMode();
3363 InitReg(MISCREG_DBGWCR10)
3364 .allPrivileges().exceptUserMode();
3365 InitReg(MISCREG_DBGWCR11)
3366 .allPrivileges().exceptUserMode();
3367 InitReg(MISCREG_DBGWCR12)
3368 .allPrivileges().exceptUserMode();
3369 InitReg(MISCREG_DBGWCR13)
3370 .allPrivileges().exceptUserMode();
3371 InitReg(MISCREG_DBGWCR14)
3372 .allPrivileges().exceptUserMode();
3373 InitReg(MISCREG_DBGWCR15)
3374 .allPrivileges().exceptUserMode();
3375 InitReg(MISCREG_DBGDRAR)
3376 .unimplemented()
3377 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3378 InitReg(MISCREG_DBGBXVR0)
3379 .allPrivileges().exceptUserMode();
3380 InitReg(MISCREG_DBGBXVR1)
3381 .allPrivileges().exceptUserMode();
3382 InitReg(MISCREG_DBGBXVR2)
3383 .allPrivileges().exceptUserMode();
3384 InitReg(MISCREG_DBGBXVR3)
3385 .allPrivileges().exceptUserMode();
3386 InitReg(MISCREG_DBGBXVR4)
3387 .allPrivileges().exceptUserMode();
3388 InitReg(MISCREG_DBGBXVR5)
3389 .allPrivileges().exceptUserMode();
3390 InitReg(MISCREG_DBGBXVR0)
3391 .allPrivileges().exceptUserMode();
3392 InitReg(MISCREG_DBGBXVR6)
3393 .allPrivileges().exceptUserMode();
3394 InitReg(MISCREG_DBGBXVR7)
3395 .allPrivileges().exceptUserMode();
3396 InitReg(MISCREG_DBGBXVR8)
3397 .allPrivileges().exceptUserMode();
3398 InitReg(MISCREG_DBGBXVR9)
3399 .allPrivileges().exceptUserMode();
3400 InitReg(MISCREG_DBGBXVR10)
3401 .allPrivileges().exceptUserMode();
3402 InitReg(MISCREG_DBGBXVR11)
3403 .allPrivileges().exceptUserMode();
3404 InitReg(MISCREG_DBGBXVR12)
3405 .allPrivileges().exceptUserMode();
3406 InitReg(MISCREG_DBGBXVR13)
3407 .allPrivileges().exceptUserMode();
3408 InitReg(MISCREG_DBGBXVR14)
3409 .allPrivileges().exceptUserMode();
3410 InitReg(MISCREG_DBGBXVR15)
3411 .allPrivileges().exceptUserMode();
3412 InitReg(MISCREG_DBGOSLAR)
3413 .allPrivileges().monSecureRead(0).monNonSecureRead(0);
3414 InitReg(MISCREG_DBGOSLSR)
3415 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3416 InitReg(MISCREG_DBGOSDLR)
3417 .unimplemented()
3418 .warnNotFail()
3419 .allPrivileges();
3420 InitReg(MISCREG_DBGPRCR)
3421 .unimplemented()
3422 .allPrivileges();
3423 InitReg(MISCREG_DBGDSAR)
3424 .unimplemented()
3425 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3426 InitReg(MISCREG_DBGCLAIMSET)
3427 .unimplemented()
3428 .allPrivileges();
3429 InitReg(MISCREG_DBGCLAIMCLR)
3430 .unimplemented()
3431 .allPrivileges();
3432 InitReg(MISCREG_DBGAUTHSTATUS)
3433 .unimplemented()
3434 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3435 InitReg(MISCREG_DBGDEVID2)
3436 .unimplemented()
3437 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3438 InitReg(MISCREG_DBGDEVID1)
3439 .unimplemented()
3440 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3441 InitReg(MISCREG_DBGDEVID0)
3442 .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
3443 InitReg(MISCREG_TEECR)
3444 .unimplemented()
3445 .allPrivileges();
3446 InitReg(MISCREG_JIDR)
3447 .raz() // Jazelle trivial implementation, RAZ/WI
3448 .allPrivileges();
3449 InitReg(MISCREG_TEEHBR)
3450 .allPrivileges();
3451 InitReg(MISCREG_JOSCR)
3452 .raz() // Jazelle trivial implementation, RAZ/WI
3453 .allPrivileges();
3454 InitReg(MISCREG_JMCR)
3455 .raz() // Jazelle trivial implementation, RAZ/WI
3456 .allPrivileges();
3457
3458 // AArch32 CP15 registers
3459 InitReg(MISCREG_MIDR)
3460 .reset(midr)
3461 .allPrivileges().exceptUserMode().writes(0);
3462 InitReg(MISCREG_CTR)
3463 .reset([system=p.system](){
3464 //all caches have the same line size in gem5
3465 //4 byte words in ARM
3466 unsigned line_size_words =
3467 system->cacheLineSize() / 4;
3468 unsigned log2_line_size_words = 0;
3469
3470 while (line_size_words >>= 1) {
3471 ++log2_line_size_words;
3472 }
3473
3474 CTR ctr = 0;
3475 //log2 of minimun i-cache line size (words)
3476 ctr.iCacheLineSize = log2_line_size_words;
3477 //b11 - gem5 uses pipt
3478 ctr.l1IndexPolicy = 0x3;
3479 //log2 of minimum d-cache line size (words)
3480 ctr.dCacheLineSize = log2_line_size_words;
3481 //log2 of max reservation size (words)
3482 ctr.erg = log2_line_size_words;
3483 //log2 of max writeback size (words)
3484 ctr.cwg = log2_line_size_words;
3485 //b100 - gem5 format is ARMv7
3486 ctr.format = 0x4;
3487
3488 return ctr;
3489 }())
3490 .unserialize(0)
3491 .allPrivileges().exceptUserMode().writes(0);
3492 InitReg(MISCREG_TCMTR)
3493 .raz() // No TCM's
3494 .allPrivileges().exceptUserMode().writes(0);
3495 InitReg(MISCREG_TLBTR)
3496 .reset(1) // Separate Instruction and Data TLBs
3497 .allPrivileges().exceptUserMode().writes(0);
3498 InitReg(MISCREG_MPIDR)
3499 .reset(0x80000000)
3500 .allPrivileges().exceptUserMode().writes(0);
3501 InitReg(MISCREG_REVIDR)
3502 .unimplemented()
3503 .warnNotFail()
3504 .allPrivileges().exceptUserMode().writes(0);
3505 InitReg(MISCREG_ID_PFR0)
3506 .reset(0x00000031) // !ThumbEE | !Jazelle | Thumb | ARM
3507 .allPrivileges().exceptUserMode().writes(0);
3508 InitReg(MISCREG_ID_PFR1)
3509 .reset([release=release,system=system](){
3510 // Timer | Virti | !M Profile | TrustZone | ARMv4
3511 bool have_timer = (system && system->getGenericTimer() != nullptr);
3512 return 0x00000001 |
3513 (release->has(ArmExtension::SECURITY) ?
3514 0x00000010 : 0x0) |
3515 (release->has(ArmExtension::VIRTUALIZATION) ?
3516 0x00001000 : 0x0) |
3517 (have_timer ? 0x00010000 : 0x0);
3518 }())
3519 .unserialize(0)
3520 .allPrivileges().exceptUserMode().writes(0);
3521 InitReg(MISCREG_ID_DFR0)
3522 .reset(p.pmu ? 0x03000000 : 0)
3523 .allPrivileges().exceptUserMode().writes(0);
3524 InitReg(MISCREG_ID_AFR0)
3525 .allPrivileges().exceptUserMode().writes(0);
3526 InitReg(MISCREG_ID_MMFR0)
3527 .reset([p,release=release](){
3528 RegVal mmfr0 = p.id_mmfr0;
3529 if (release->has(ArmExtension::LPAE))
3530 mmfr0 = (mmfr0 & ~0xf) | 0x5;
3531 return mmfr0;
3532 }())
3533 .allPrivileges().exceptUserMode().writes(0);
3534 InitReg(MISCREG_ID_MMFR1)
3535 .reset(p.id_mmfr1)
3536 .allPrivileges().exceptUserMode().writes(0);
3537 InitReg(MISCREG_ID_MMFR2)
3538 .reset(p.id_mmfr2)
3539 .allPrivileges().exceptUserMode().writes(0);
3540 InitReg(MISCREG_ID_MMFR3)
3541 .reset(p.id_mmfr3)
3542 .allPrivileges().exceptUserMode().writes(0);
3543 InitReg(MISCREG_ID_MMFR4)
3544 .reset(p.id_mmfr4)
3545 .allPrivileges().exceptUserMode().writes(0);
3546 InitReg(MISCREG_ID_ISAR0)
3547 .reset(p.id_isar0)
3548 .allPrivileges().exceptUserMode().writes(0);
3549 InitReg(MISCREG_ID_ISAR1)
3550 .reset(p.id_isar1)
3551 .allPrivileges().exceptUserMode().writes(0);
3552 InitReg(MISCREG_ID_ISAR2)
3553 .reset(p.id_isar2)
3554 .allPrivileges().exceptUserMode().writes(0);
3555 InitReg(MISCREG_ID_ISAR3)
3556 .reset(p.id_isar3)
3557 .allPrivileges().exceptUserMode().writes(0);
3558 InitReg(MISCREG_ID_ISAR4)
3559 .reset(p.id_isar4)
3560 .allPrivileges().exceptUserMode().writes(0);
3561 InitReg(MISCREG_ID_ISAR5)
3562 .reset([p,release=release] () {
3563 ISAR5 isar5 = p.id_isar5;
3564 isar5.crc32 = release->has(ArmExtension::FEAT_CRC32) ? 0x1 : 0x0;
3565 isar5.sha2 = release->has(ArmExtension::FEAT_SHA256) ? 0x1 : 0x0;
3566 isar5.sha1 = release->has(ArmExtension::FEAT_SHA1) ? 0x1 : 0x0;
3567 isar5.aes = release->has(ArmExtension::FEAT_PMULL) ?
3568 0x2 : release->has(ArmExtension::FEAT_AES) ?
3569 0x1 : 0x0;
3570 isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
3571 isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
3572 return isar5;
3573 }())
3574 .allPrivileges().exceptUserMode().writes(0);
3575 InitReg(MISCREG_ID_ISAR6)
3576 .reset([p,release=release] () {
3577 ISAR6 isar6 = p.id_isar6;
3578 isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
3579 return isar6;
3580 }())
3581 .allPrivileges().exceptUserMode().writes(0);
3582 InitReg(MISCREG_CCSIDR)
3583 .allPrivileges().exceptUserMode().writes(0);
3584 InitReg(MISCREG_CLIDR)
3585 .allPrivileges().exceptUserMode().writes(0);
3586 InitReg(MISCREG_AIDR)
3587 .raz() // AUX ID set to 0
3588 .allPrivileges().exceptUserMode().writes(0);
3589 InitReg(MISCREG_CSSELR)
3590 .banked();
3591 InitReg(MISCREG_CSSELR_NS)
3592 .bankedChild()
3593 .privSecure(!aarch32EL3)
3594 .nonSecure().exceptUserMode();
3595 InitReg(MISCREG_CSSELR_S)
3596 .bankedChild()
3597 .secure().exceptUserMode();
3598 InitReg(MISCREG_VPIDR)
3599 .reset(midr)
3600 .hyp().monNonSecure();
3601 InitReg(MISCREG_VMPIDR)
3602 .res1(mask(31, 31))
3603 .hyp().monNonSecure();
3604 InitReg(MISCREG_SCTLR)
3605 .banked()
3606 // readMiscRegNoEffect() uses this metadata
3607 // despite using children (below) as backing store
3608 .res0(0x8d22c600)
3609 .res1(0x00400800 | (SPAN ? 0 : 0x800000)
3610 | (LSMAOE ? 0 : 0x10)
3611 | (nTLSMD ? 0 : 0x8));
3612
3613 auto sctlr_reset = [aarch64=highestELIs64] ()
3614 {
3615 SCTLR sctlr = 0;
3616 if (aarch64) {
3617 sctlr.afe = 1;
3618 sctlr.tre = 1;
3619 sctlr.span = 1;
3620 sctlr.uwxn = 1;
3621 sctlr.ntwe = 1;
3622 sctlr.ntwi = 1;
3623 sctlr.cp15ben = 1;
3624 sctlr.sa0 = 1;
3625 } else {
3626 sctlr.u = 1;
3627 sctlr.xp = 1;
3628 sctlr.uci = 1;
3629 sctlr.dze = 1;
3630 sctlr.rao2 = 1;
3631 sctlr.rao3 = 1;
3632 sctlr.rao4 = 0xf;
3633 }
3634 return sctlr;
3635 }();
3636 InitReg(MISCREG_SCTLR_NS)
3637 .reset(sctlr_reset)
3638 .bankedChild()
3639 .privSecure(!aarch32EL3)
3640 .nonSecure().exceptUserMode();
3641 InitReg(MISCREG_SCTLR_S)
3642 .reset(sctlr_reset)
3643 .bankedChild()
3644 .secure().exceptUserMode();
3645 InitReg(MISCREG_ACTLR)
3646 .banked();
3647 InitReg(MISCREG_ACTLR_NS)
3648 .bankedChild()
3649 .privSecure(!aarch32EL3)
3650 .nonSecure().exceptUserMode();
3651 InitReg(MISCREG_ACTLR_S)
3652 .bankedChild()
3653 .secure().exceptUserMode();
3654 InitReg(MISCREG_CPACR)
3655 .allPrivileges().exceptUserMode();
3656 InitReg(MISCREG_SDCR)
3657 .mon();
3658 InitReg(MISCREG_SCR)
3659 .reset(release->has(ArmExtension::SECURITY) ? 0 : 1)
3660 .mon().secure().exceptUserMode()
3661 .res0(0xff40) // [31:16], [6]
3662 .res1(0x0030); // [5:4]
3663 InitReg(MISCREG_SDER)
3664 .mon();
3665 InitReg(MISCREG_NSACR)
3666 .allPrivileges().hypWrite(0).privNonSecureWrite(0).exceptUserMode();
3667 InitReg(MISCREG_HSCTLR)
3668 .reset(0x30c50830)
3669 .hyp().monNonSecure()
3670 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
3671 | (IESB ? 0 : 0x200000)
3672 | (EnDA ? 0 : 0x8000000)
3673 | (EnIB ? 0 : 0x40000000)
3674 | (EnIA ? 0 : 0x80000000))
3675 .res1(0x30c50830);
3676 InitReg(MISCREG_HACTLR)
3677 .hyp().monNonSecure();
3678 InitReg(MISCREG_HCR)
3679 .hyp().monNonSecure()
3680 .res0(release->has(ArmExtension::VIRTUALIZATION) ?
3681 0x90000000 : mask(31, 0));
3682 InitReg(MISCREG_HCR2)
3683 .hyp().monNonSecure()
3684 .res0(release->has(ArmExtension::VIRTUALIZATION) ?
3685 0xffa9ff8c : mask(31, 0));
3686 InitReg(MISCREG_HDCR)
3687 .hyp().monNonSecure();
3688 InitReg(MISCREG_HCPTR)
3689 .res0(mask(29, 21) | mask(19, 16) | mask(14, 14))
3690 .res1(mask(13, 12) | mask(9, 0))
3691 .hyp().monNonSecure();
3692 InitReg(MISCREG_HSTR)
3693 .hyp().monNonSecure();
3694 InitReg(MISCREG_HACR)
3695 .unimplemented()
3696 .warnNotFail()
3697 .hyp().monNonSecure();
3698 InitReg(MISCREG_TTBR0)
3699 .banked();
3700 InitReg(MISCREG_TTBR0_NS)
3701 .bankedChild()
3702 .privSecure(!aarch32EL3)
3703 .nonSecure().exceptUserMode();
3704 InitReg(MISCREG_TTBR0_S)
3705 .bankedChild()
3706 .secure().exceptUserMode();
3707 InitReg(MISCREG_TTBR1)
3708 .banked();
3709 InitReg(MISCREG_TTBR1_NS)
3710 .bankedChild()
3711 .privSecure(!aarch32EL3)
3712 .nonSecure().exceptUserMode();
3713 InitReg(MISCREG_TTBR1_S)
3714 .bankedChild()
3715 .secure().exceptUserMode();
3716 InitReg(MISCREG_TTBCR)
3717 .banked();
3718 InitReg(MISCREG_TTBCR_NS)
3719 .bankedChild()
3720 .privSecure(!aarch32EL3)
3721 .nonSecure().exceptUserMode();
3722 InitReg(MISCREG_TTBCR_S)
3723 .bankedChild()
3724 .secure().exceptUserMode();
3725 InitReg(MISCREG_HTCR)
3726 .hyp().monNonSecure();
3727 InitReg(MISCREG_VTCR)
3728 .hyp().monNonSecure();
3729 InitReg(MISCREG_DACR)
3730 .banked();
3731 InitReg(MISCREG_DACR_NS)
3732 .bankedChild()
3733 .privSecure(!aarch32EL3)
3734 .nonSecure().exceptUserMode();
3735 InitReg(MISCREG_DACR_S)
3736 .bankedChild()
3737 .secure().exceptUserMode();
3738 InitReg(MISCREG_DFSR)
3739 .banked()
3740 .res0(mask(31, 14) | mask(8, 8));
3741 InitReg(MISCREG_DFSR_NS)
3742 .bankedChild()
3743 .privSecure(!aarch32EL3)
3744 .nonSecure().exceptUserMode();
3745 InitReg(MISCREG_DFSR_S)
3746 .bankedChild()
3747 .secure().exceptUserMode();
3748 InitReg(MISCREG_IFSR)
3749 .banked()
3750 .res0(mask(31, 13) | mask(11, 11) | mask(8, 6));
3751 InitReg(MISCREG_IFSR_NS)
3752 .bankedChild()
3753 .privSecure(!aarch32EL3)
3754 .nonSecure().exceptUserMode();
3755 InitReg(MISCREG_IFSR_S)
3756 .bankedChild()
3757 .secure().exceptUserMode();
3758 InitReg(MISCREG_ADFSR)
3759 .unimplemented()
3760 .warnNotFail()
3761 .banked();
3762 InitReg(MISCREG_ADFSR_NS)
3763 .unimplemented()
3764 .warnNotFail()
3765 .bankedChild()
3766 .privSecure(!aarch32EL3)
3767 .nonSecure().exceptUserMode();
3768 InitReg(MISCREG_ADFSR_S)
3769 .unimplemented()
3770 .warnNotFail()
3771 .bankedChild()
3772 .secure().exceptUserMode();
3773 InitReg(MISCREG_AIFSR)
3774 .unimplemented()
3775 .warnNotFail()
3776 .banked();
3777 InitReg(MISCREG_AIFSR_NS)
3778 .unimplemented()
3779 .warnNotFail()
3780 .bankedChild()
3781 .privSecure(!aarch32EL3)
3782 .nonSecure().exceptUserMode();
3783 InitReg(MISCREG_AIFSR_S)
3784 .unimplemented()
3785 .warnNotFail()
3786 .bankedChild()
3787 .secure().exceptUserMode();
3788 InitReg(MISCREG_HADFSR)
3789 .hyp().monNonSecure();
3790 InitReg(MISCREG_HAIFSR)
3791 .hyp().monNonSecure();
3792 InitReg(MISCREG_HSR)
3793 .hyp().monNonSecure();
3794 InitReg(MISCREG_DFAR)
3795 .banked();
3796 InitReg(MISCREG_DFAR_NS)
3797 .bankedChild()
3798 .privSecure(!aarch32EL3)
3799 .nonSecure().exceptUserMode();
3800 InitReg(MISCREG_DFAR_S)
3801 .bankedChild()
3802 .secure().exceptUserMode();
3803 InitReg(MISCREG_IFAR)
3804 .banked();
3805 InitReg(MISCREG_IFAR_NS)
3806 .bankedChild()
3807 .privSecure(!aarch32EL3)
3808 .nonSecure().exceptUserMode();
3809 InitReg(MISCREG_IFAR_S)
3810 .bankedChild()
3811 .secure().exceptUserMode();
3812 InitReg(MISCREG_HDFAR)
3813 .hyp().monNonSecure();
3814 InitReg(MISCREG_HIFAR)
3815 .hyp().monNonSecure();
3816 InitReg(MISCREG_HPFAR)
3817 .hyp().monNonSecure();
3818 InitReg(MISCREG_ICIALLUIS)
3819 .unimplemented()
3820 .warnNotFail()
3821 .writes(1).exceptUserMode();
3822 InitReg(MISCREG_BPIALLIS)
3823 .unimplemented()
3824 .warnNotFail()
3825 .writes(1).exceptUserMode();
3826 InitReg(MISCREG_PAR)
3827 .banked();
3828 InitReg(MISCREG_PAR_NS)
3829 .bankedChild()
3830 .privSecure(!aarch32EL3)
3831 .nonSecure().exceptUserMode();
3832 InitReg(MISCREG_PAR_S)
3833 .bankedChild()
3834 .secure().exceptUserMode();
3835 InitReg(MISCREG_ICIALLU)
3836 .writes(1).exceptUserMode();
3837 InitReg(MISCREG_ICIMVAU)
3838 .unimplemented()
3839 .warnNotFail()
3840 .writes(1).exceptUserMode();
3841 InitReg(MISCREG_CP15ISB)
3842 .writes(1);
3843 InitReg(MISCREG_BPIALL)
3844 .unimplemented()
3845 .warnNotFail()
3846 .writes(1).exceptUserMode();
3847 InitReg(MISCREG_BPIMVA)
3848 .unimplemented()
3849 .warnNotFail()
3850 .writes(1).exceptUserMode();
3851 InitReg(MISCREG_DCIMVAC)
3852 .unimplemented()
3853 .warnNotFail()
3854 .writes(1).exceptUserMode();
3855 InitReg(MISCREG_DCISW)
3856 .unimplemented()
3857 .warnNotFail()
3858 .writes(1).exceptUserMode();
3859 InitReg(MISCREG_ATS1CPR)
3860 .writes(1).exceptUserMode();
3861 InitReg(MISCREG_ATS1CPW)
3862 .writes(1).exceptUserMode();
3863 InitReg(MISCREG_ATS1CUR)
3864 .writes(1).exceptUserMode();
3865 InitReg(MISCREG_ATS1CUW)
3866 .writes(1).exceptUserMode();
3867 InitReg(MISCREG_ATS12NSOPR)
3868 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3869 InitReg(MISCREG_ATS12NSOPW)
3870 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3871 InitReg(MISCREG_ATS12NSOUR)
3872 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3873 InitReg(MISCREG_ATS12NSOUW)
3874 .privSecureWrite().hypWrite().monSecureWrite().monNonSecureWrite();
3875 InitReg(MISCREG_DCCMVAC)
3876 .writes(1).exceptUserMode();
3877 InitReg(MISCREG_DCCSW)
3878 .unimplemented()
3879 .warnNotFail()
3880 .writes(1).exceptUserMode();
3881 InitReg(MISCREG_CP15DSB)
3882 .writes(1);
3883 InitReg(MISCREG_CP15DMB)
3884 .writes(1);
3885 InitReg(MISCREG_DCCMVAU)
3886 .unimplemented()
3887 .warnNotFail()
3888 .writes(1).exceptUserMode();
3889 InitReg(MISCREG_DCCIMVAC)
3890 .unimplemented()
3891 .warnNotFail()
3892 .writes(1).exceptUserMode();
3893 InitReg(MISCREG_DCCISW)
3894 .unimplemented()
3895 .warnNotFail()
3896 .writes(1).exceptUserMode();
3897 InitReg(MISCREG_ATS1HR)
3898 .monNonSecureWrite().hypWrite();
3899 InitReg(MISCREG_ATS1HW)
3900 .monNonSecureWrite().hypWrite();
3901 InitReg(MISCREG_TLBIALLIS)
3902 .writes(1).exceptUserMode();
3903 InitReg(MISCREG_TLBIMVAIS)
3904 .writes(1).exceptUserMode();
3905 InitReg(MISCREG_TLBIASIDIS)
3906 .writes(1).exceptUserMode();
3907 InitReg(MISCREG_TLBIMVAAIS)
3908 .writes(1).exceptUserMode();
3909 InitReg(MISCREG_TLBIMVALIS)
3910 .writes(1).exceptUserMode();
3911 InitReg(MISCREG_TLBIMVAALIS)
3912 .writes(1).exceptUserMode();
3913 InitReg(MISCREG_ITLBIALL)
3914 .writes(1).exceptUserMode();
3915 InitReg(MISCREG_ITLBIMVA)
3916 .writes(1).exceptUserMode();
3917 InitReg(MISCREG_ITLBIASID)
3918 .writes(1).exceptUserMode();
3919 InitReg(MISCREG_DTLBIALL)
3920 .writes(1).exceptUserMode();
3921 InitReg(MISCREG_DTLBIMVA)
3922 .writes(1).exceptUserMode();
3923 InitReg(MISCREG_DTLBIASID)
3924 .writes(1).exceptUserMode();
3925 InitReg(MISCREG_TLBIALL)
3926 .writes(1).exceptUserMode();
3927 InitReg(MISCREG_TLBIMVA)
3928 .writes(1).exceptUserMode();
3929 InitReg(MISCREG_TLBIASID)
3930 .writes(1).exceptUserMode();
3931 InitReg(MISCREG_TLBIMVAA)
3932 .writes(1).exceptUserMode();
3933 InitReg(MISCREG_TLBIMVAL)
3934 .writes(1).exceptUserMode();
3935 InitReg(MISCREG_TLBIMVAAL)
3936 .writes(1).exceptUserMode();
3937 InitReg(MISCREG_TLBIIPAS2IS)
3938 .monNonSecureWrite().hypWrite();
3939 InitReg(MISCREG_TLBIIPAS2LIS)
3940 .monNonSecureWrite().hypWrite();
3941 InitReg(MISCREG_TLBIALLHIS)
3942 .monNonSecureWrite().hypWrite();
3943 InitReg(MISCREG_TLBIMVAHIS)
3944 .monNonSecureWrite().hypWrite();
3945 InitReg(MISCREG_TLBIALLNSNHIS)
3946 .monNonSecureWrite().hypWrite();
3947 InitReg(MISCREG_TLBIMVALHIS)
3948 .monNonSecureWrite().hypWrite();
3949 InitReg(MISCREG_TLBIIPAS2)
3950 .monNonSecureWrite().hypWrite();
3951 InitReg(MISCREG_TLBIIPAS2L)
3952 .monNonSecureWrite().hypWrite();
3953 InitReg(MISCREG_TLBIALLH)
3954 .monNonSecureWrite().hypWrite();
3955 InitReg(MISCREG_TLBIMVAH)
3956 .monNonSecureWrite().hypWrite();
3957 InitReg(MISCREG_TLBIALLNSNH)
3958 .monNonSecureWrite().hypWrite();
3959 InitReg(MISCREG_TLBIMVALH)
3960 .monNonSecureWrite().hypWrite();
3961 InitReg(MISCREG_PMCR)
3962 .allPrivileges();
3963 InitReg(MISCREG_PMCNTENSET)
3964 .allPrivileges();
3965 InitReg(MISCREG_PMCNTENCLR)
3966 .allPrivileges();
3967 InitReg(MISCREG_PMOVSR)
3968 .allPrivileges();
3969 InitReg(MISCREG_PMSWINC)
3970 .allPrivileges();
3971 InitReg(MISCREG_PMSELR)
3972 .allPrivileges();
3973 InitReg(MISCREG_PMCEID0)
3974 .allPrivileges();
3975 InitReg(MISCREG_PMCEID1)
3976 .allPrivileges();
3977 InitReg(MISCREG_PMCCNTR)
3978 .allPrivileges();
3979 InitReg(MISCREG_PMXEVTYPER)
3980 .allPrivileges();
3981 InitReg(MISCREG_PMEVCNTR0)
3982 .allPrivileges();
3983 InitReg(MISCREG_PMEVCNTR1)
3984 .allPrivileges();
3985 InitReg(MISCREG_PMEVCNTR2)
3986 .allPrivileges();
3987 InitReg(MISCREG_PMEVCNTR3)
3988 .allPrivileges();
3989 InitReg(MISCREG_PMEVCNTR4)
3990 .allPrivileges();
3991 InitReg(MISCREG_PMEVCNTR5)
3992 .allPrivileges();
3993 InitReg(MISCREG_PMEVTYPER0)
3994 .allPrivileges();
3995 InitReg(MISCREG_PMEVTYPER1)
3996 .allPrivileges();
3997 InitReg(MISCREG_PMEVTYPER2)
3998 .allPrivileges();
3999 InitReg(MISCREG_PMEVTYPER3)
4000 .allPrivileges();
4001 InitReg(MISCREG_PMEVTYPER4)
4002 .allPrivileges();
4003 InitReg(MISCREG_PMEVTYPER5)
4004 .allPrivileges();
4005 InitReg(MISCREG_PMCCFILTR)
4006 .allPrivileges();
4007 InitReg(MISCREG_PMXEVCNTR)
4008 .allPrivileges();
4009 InitReg(MISCREG_PMUSERENR)
4010 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0);
4011 InitReg(MISCREG_PMINTENSET)
4012 .allPrivileges().exceptUserMode();
4013 InitReg(MISCREG_PMINTENCLR)
4014 .allPrivileges().exceptUserMode();
4015 InitReg(MISCREG_PMOVSSET)
4016 .unimplemented()
4017 .allPrivileges();
4018 InitReg(MISCREG_L2CTLR)
4019 .allPrivileges().exceptUserMode();
4020 InitReg(MISCREG_L2ECTLR)
4021 .unimplemented()
4022 .allPrivileges().exceptUserMode();
4023 InitReg(MISCREG_PRRR)
4024 .banked();
4025 InitReg(MISCREG_PRRR_NS)
4026 .bankedChild()
4027 .reset(
4028 (1 << 19) | // 19
4029 (0 << 18) | // 18
4030 (0 << 17) | // 17
4031 (1 << 16) | // 16
4032 (2 << 14) | // 15:14
4033 (0 << 12) | // 13:12
4034 (2 << 10) | // 11:10
4035 (2 << 8) | // 9:8
4036 (2 << 6) | // 7:6
4037 (2 << 4) | // 5:4
4038 (1 << 2) | // 3:2
4039 0)
4040 .privSecure(!aarch32EL3)
4041 .nonSecure().exceptUserMode();
4042 InitReg(MISCREG_PRRR_S)
4043 .bankedChild()
4044 .secure().exceptUserMode();
4045 InitReg(MISCREG_MAIR0)
4046 .banked();
4047 InitReg(MISCREG_MAIR0_NS)
4048 .bankedChild()
4049 .privSecure(!aarch32EL3)
4050 .nonSecure().exceptUserMode();
4051 InitReg(MISCREG_MAIR0_S)
4052 .bankedChild()
4053 .secure().exceptUserMode();
4054 InitReg(MISCREG_NMRR)
4055 .banked();
4056 InitReg(MISCREG_NMRR_NS)
4057 .bankedChild()
4058 .reset(
4059 (1 << 30) | // 31:30
4060 (0 << 26) | // 27:26
4061 (0 << 24) | // 25:24
4062 (3 << 22) | // 23:22
4063 (2 << 20) | // 21:20
4064 (0 << 18) | // 19:18
4065 (0 << 16) | // 17:16
4066 (1 << 14) | // 15:14
4067 (0 << 12) | // 13:12
4068 (2 << 10) | // 11:10
4069 (0 << 8) | // 9:8
4070 (3 << 6) | // 7:6
4071 (2 << 4) | // 5:4
4072 (0 << 2) | // 3:2
4073 0)
4074 .privSecure(!aarch32EL3)
4075 .nonSecure().exceptUserMode();
4076 InitReg(MISCREG_NMRR_S)
4077 .bankedChild()
4078 .secure().exceptUserMode();
4079 InitReg(MISCREG_MAIR1)
4080 .banked();
4081 InitReg(MISCREG_MAIR1_NS)
4082 .bankedChild()
4083 .privSecure(!aarch32EL3)
4084 .nonSecure().exceptUserMode();
4085 InitReg(MISCREG_MAIR1_S)
4086 .bankedChild()
4087 .secure().exceptUserMode();
4088 InitReg(MISCREG_AMAIR0)
4089 .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
4090 .banked();
4091 InitReg(MISCREG_AMAIR0_NS)
4092 .bankedChild()
4093 .privSecure(!aarch32EL3)
4094 .nonSecure().exceptUserMode();
4095 InitReg(MISCREG_AMAIR0_S)
4096 .bankedChild()
4097 .secure().exceptUserMode();
4098 InitReg(MISCREG_AMAIR1)
4099 .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
4100 .banked();
4101 InitReg(MISCREG_AMAIR1_NS)
4102 .bankedChild()
4103 .privSecure(!aarch32EL3)
4104 .nonSecure().exceptUserMode();
4105 InitReg(MISCREG_AMAIR1_S)
4106 .bankedChild()
4107 .secure().exceptUserMode();
4108 InitReg(MISCREG_HMAIR0)
4109 .hyp().monNonSecure();
4110 InitReg(MISCREG_HMAIR1)
4111 .hyp().monNonSecure();
4112 InitReg(MISCREG_HAMAIR0)
4113 .unimplemented()
4114 .warnNotFail()
4115 .hyp().monNonSecure();
4116 InitReg(MISCREG_HAMAIR1)
4117 .unimplemented()
4118 .warnNotFail()
4119 .hyp().monNonSecure();
4120 InitReg(MISCREG_VBAR)
4121 .banked();
4122 InitReg(MISCREG_VBAR_NS)
4123 .bankedChild()
4124 .privSecure(!aarch32EL3)
4125 .nonSecure().exceptUserMode();
4126 InitReg(MISCREG_VBAR_S)
4127 .bankedChild()
4128 .secure().exceptUserMode();
4129 InitReg(MISCREG_MVBAR)
4130 .reset(FullSystem ? system->resetAddr() : 0)
4131 .mon().secure()
4132 .hypRead(FullSystem && system->highestEL() == EL2)
4133 .privRead(FullSystem && system->highestEL() == EL1)
4134 .exceptUserMode();
4135 InitReg(MISCREG_RMR)
4136 .unimplemented()
4137 .mon().secure().exceptUserMode();
4138 InitReg(MISCREG_ISR)
4139 .allPrivileges().exceptUserMode().writes(0);
4140 InitReg(MISCREG_HVBAR)
4141 .hyp().monNonSecure()
4142 .res0(0x1f);
4143 InitReg(MISCREG_FCSEIDR)
4144 .unimplemented()
4145 .warnNotFail()
4146 .allPrivileges().exceptUserMode();
4147 InitReg(MISCREG_CONTEXTIDR)
4148 .banked();
4149 InitReg(MISCREG_CONTEXTIDR_NS)
4150 .bankedChild()
4151 .privSecure(!aarch32EL3)
4152 .nonSecure().exceptUserMode();
4153 InitReg(MISCREG_CONTEXTIDR_S)
4154 .bankedChild()
4155 .secure().exceptUserMode();
4156 InitReg(MISCREG_TPIDRURW)
4157 .banked();
4158 InitReg(MISCREG_TPIDRURW_NS)
4159 .bankedChild()
4160 .allPrivileges()
4161 .privSecure(!aarch32EL3)
4162 .monSecure(0);
4163 InitReg(MISCREG_TPIDRURW_S)
4164 .bankedChild()
4165 .secure();
4166 InitReg(MISCREG_TPIDRURO)
4167 .banked();
4168 InitReg(MISCREG_TPIDRURO_NS)
4169 .bankedChild()
4170 .allPrivileges()
4171 .userNonSecureWrite(0).userSecureRead(1)
4172 .privSecure(!aarch32EL3)
4173 .monSecure(0);
4174 InitReg(MISCREG_TPIDRURO_S)
4175 .bankedChild()
4176 .secure().userSecureWrite(0);
4177 InitReg(MISCREG_TPIDRPRW)
4178 .banked();
4179 InitReg(MISCREG_TPIDRPRW_NS)
4180 .bankedChild()
4181 .nonSecure().exceptUserMode()
4182 .privSecure(!aarch32EL3);
4183 InitReg(MISCREG_TPIDRPRW_S)
4184 .bankedChild()
4185 .secure().exceptUserMode();
4186 InitReg(MISCREG_HTPIDR)
4187 .hyp().monNonSecure();
4188 // BEGIN Generic Timer (AArch32)
4189 InitReg(MISCREG_CNTFRQ)
4190 .reads(1)
4191 .highest(system)
4192 .privSecureWrite(aarch32EL3);
4193 InitReg(MISCREG_CNTPCT)
4194 .unverifiable()
4195 .reads(1);
4196 InitReg(MISCREG_CNTVCT)
4197 .unverifiable()
4198 .reads(1);
4199 InitReg(MISCREG_CNTP_CTL)
4200 .banked();
4201 InitReg(MISCREG_CNTP_CTL_NS)
4202 .bankedChild()
4203 .nonSecure()
4204 .privSecure(!aarch32EL3)
4205 .userSecureRead(!aarch32EL3)
4206 .userSecureWrite(!aarch32EL3)
4207 .res0(0xfffffff8);
4208 InitReg(MISCREG_CNTP_CTL_S)
4209 .bankedChild()
4210 .secure()
4211 .privSecure(aarch32EL3)
4212 .res0(0xfffffff8);
4213 InitReg(MISCREG_CNTP_CVAL)
4214 .banked();
4215 InitReg(MISCREG_CNTP_CVAL_NS)
4216 .bankedChild()
4217 .nonSecure()
4218 .privSecure(!aarch32EL3)
4219 .userSecureRead(!aarch32EL3)
4220 .userSecureWrite(!aarch32EL3);
4221 InitReg(MISCREG_CNTP_CVAL_S)
4222 .bankedChild()
4223 .secure()
4224 .privSecure(aarch32EL3);
4225 InitReg(MISCREG_CNTP_TVAL)
4226 .banked();
4227 InitReg(MISCREG_CNTP_TVAL_NS)
4228 .bankedChild()
4229 .nonSecure()
4230 .privSecure(!aarch32EL3)
4231 .userSecureRead(!aarch32EL3)
4232 .userSecureWrite(!aarch32EL3);
4233 InitReg(MISCREG_CNTP_TVAL_S)
4234 .bankedChild()
4235 .secure()
4236 .privSecure(aarch32EL3);
4237 InitReg(MISCREG_CNTV_CTL)
4238 .allPrivileges()
4239 .res0(0xfffffff8);
4240 InitReg(MISCREG_CNTV_CVAL)
4241 .allPrivileges();
4242 InitReg(MISCREG_CNTV_TVAL)
4243 .allPrivileges();
4244 InitReg(MISCREG_CNTKCTL)
4245 .allPrivileges()
4246 .exceptUserMode()
4247 .res0(0xfffdfc00);
4248 InitReg(MISCREG_CNTHCTL)
4249 .monNonSecure()
4250 .hyp()
4251 .res0(0xfffdff00);
4252 InitReg(MISCREG_CNTHP_CTL)
4253 .monNonSecure()
4254 .hyp()
4255 .res0(0xfffffff8);
4256 InitReg(MISCREG_CNTHP_CVAL)
4257 .monNonSecure()
4258 .hyp();
4259 InitReg(MISCREG_CNTHP_TVAL)
4260 .monNonSecure()
4261 .hyp();
4262 InitReg(MISCREG_CNTVOFF)
4263 .monNonSecure()
4264 .hyp();
4265 // END Generic Timer (AArch32)
4266 InitReg(MISCREG_IL1DATA0)
4267 .unimplemented()
4268 .allPrivileges().exceptUserMode();
4269 InitReg(MISCREG_IL1DATA1)
4270 .unimplemented()
4271 .allPrivileges().exceptUserMode();
4272 InitReg(MISCREG_IL1DATA2)
4273 .unimplemented()
4274 .allPrivileges().exceptUserMode();
4275 InitReg(MISCREG_IL1DATA3)
4276 .unimplemented()
4277 .allPrivileges().exceptUserMode();
4278 InitReg(MISCREG_DL1DATA0)
4279 .unimplemented()
4280 .allPrivileges().exceptUserMode();
4281 InitReg(MISCREG_DL1DATA1)
4282 .unimplemented()
4283 .allPrivileges().exceptUserMode();
4284 InitReg(MISCREG_DL1DATA2)
4285 .unimplemented()
4286 .allPrivileges().exceptUserMode();
4287 InitReg(MISCREG_DL1DATA3)
4288 .unimplemented()
4289 .allPrivileges().exceptUserMode();
4290 InitReg(MISCREG_DL1DATA4)
4291 .unimplemented()
4292 .allPrivileges().exceptUserMode();
4293 InitReg(MISCREG_RAMINDEX)
4294 .unimplemented()
4295 .writes(1).exceptUserMode();
4296 InitReg(MISCREG_L2ACTLR)
4297 .unimplemented()
4298 .allPrivileges().exceptUserMode();
4299 InitReg(MISCREG_CBAR)
4300 .unimplemented()
4301 .allPrivileges().exceptUserMode().writes(0);
4302 InitReg(MISCREG_HTTBR)
4303 .hyp().monNonSecure();
4304 InitReg(MISCREG_VTTBR)
4305 .hyp().monNonSecure();
4306 InitReg(MISCREG_CPUMERRSR)
4307 .unimplemented()
4308 .allPrivileges().exceptUserMode();
4309 InitReg(MISCREG_L2MERRSR)
4310 .unimplemented()
4311 .warnNotFail()
4312 .allPrivileges().exceptUserMode();
4313
4314 // AArch64 registers (Op0=2);
4315 InitReg(MISCREG_MDCCINT_EL1)
4316 .fault(EL1, faultMdccsrEL1)
4317 .fault(EL2, faultMdccsrEL2)
4318 .allPrivileges().exceptUserMode();
4319 InitReg(MISCREG_OSDTRRX_EL1)
4320 .allPrivileges().exceptUserMode()
4321 .mapsTo(MISCREG_DBGDTRRXext);
4322 InitReg(MISCREG_MDSCR_EL1)
4323 .allPrivileges().exceptUserMode()
4324 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::mdscrEL1>)
4325 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::mdscrEL1>)
4326 .fault(EL2, faultDebugEL2)
4327 .mapsTo(MISCREG_DBGDSCRext);
4328 InitReg(MISCREG_OSDTRTX_EL1)
4329 .allPrivileges().exceptUserMode()
4330 .mapsTo(MISCREG_DBGDTRTXext);
4331 InitReg(MISCREG_OSECCR_EL1)
4332 .allPrivileges().exceptUserMode()
4333 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::oseccrEL1>)
4334 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::oseccrEL1>)
4335 .fault(EL2, faultDebugEL2)
4336 .mapsTo(MISCREG_DBGOSECCR);
4337 InitReg(MISCREG_DBGBVR0_EL1)
4338 .allPrivileges().exceptUserMode()
4339 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4340 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4341 .fault(EL2, faultDebugEL2)
4342 .mapsTo(MISCREG_DBGBVR0, MISCREG_DBGBXVR0);
4343 InitReg(MISCREG_DBGBVR1_EL1)
4344 .allPrivileges().exceptUserMode()
4345 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4346 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4347 .fault(EL2, faultDebugEL2)
4348 .mapsTo(MISCREG_DBGBVR1, MISCREG_DBGBXVR1);
4349 InitReg(MISCREG_DBGBVR2_EL1)
4350 .allPrivileges().exceptUserMode()
4351 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4352 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4353 .fault(EL2, faultDebugEL2)
4354 .mapsTo(MISCREG_DBGBVR2, MISCREG_DBGBXVR2);
4355 InitReg(MISCREG_DBGBVR3_EL1)
4356 .allPrivileges().exceptUserMode()
4357 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4358 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4359 .fault(EL2, faultDebugEL2)
4360 .mapsTo(MISCREG_DBGBVR3, MISCREG_DBGBXVR3);
4361 InitReg(MISCREG_DBGBVR4_EL1)
4362 .allPrivileges().exceptUserMode()
4363 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4364 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4365 .fault(EL2, faultDebugEL2)
4366 .mapsTo(MISCREG_DBGBVR4, MISCREG_DBGBXVR4);
4367 InitReg(MISCREG_DBGBVR5_EL1)
4368 .allPrivileges().exceptUserMode()
4369 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4370 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4371 .fault(EL2, faultDebugEL2)
4372 .mapsTo(MISCREG_DBGBVR5, MISCREG_DBGBXVR5);
4373 InitReg(MISCREG_DBGBVR6_EL1)
4374 .allPrivileges().exceptUserMode()
4375 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4376 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4377 .fault(EL2, faultDebugEL2)
4378 .mapsTo(MISCREG_DBGBVR6, MISCREG_DBGBXVR6);
4379 InitReg(MISCREG_DBGBVR7_EL1)
4380 .allPrivileges().exceptUserMode()
4381 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4382 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4383 .fault(EL2, faultDebugEL2)
4384 .mapsTo(MISCREG_DBGBVR7, MISCREG_DBGBXVR7);
4385 InitReg(MISCREG_DBGBVR8_EL1)
4386 .allPrivileges().exceptUserMode()
4387 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4388 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4389 .fault(EL2, faultDebugEL2)
4390 .mapsTo(MISCREG_DBGBVR8, MISCREG_DBGBXVR8);
4391 InitReg(MISCREG_DBGBVR9_EL1)
4392 .allPrivileges().exceptUserMode()
4393 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4394 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4395 .fault(EL2, faultDebugEL2)
4396 .mapsTo(MISCREG_DBGBVR9, MISCREG_DBGBXVR9);
4397 InitReg(MISCREG_DBGBVR10_EL1)
4398 .allPrivileges().exceptUserMode()
4399 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4400 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4401 .fault(EL2, faultDebugEL2)
4402 .mapsTo(MISCREG_DBGBVR10, MISCREG_DBGBXVR10);
4403 InitReg(MISCREG_DBGBVR11_EL1)
4404 .allPrivileges().exceptUserMode()
4405 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4406 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4407 .fault(EL2, faultDebugEL2)
4408 .mapsTo(MISCREG_DBGBVR11, MISCREG_DBGBXVR11);
4409 InitReg(MISCREG_DBGBVR12_EL1)
4410 .allPrivileges().exceptUserMode()
4411 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4412 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4413 .fault(EL2, faultDebugEL2)
4414 .mapsTo(MISCREG_DBGBVR12, MISCREG_DBGBXVR12);
4415 InitReg(MISCREG_DBGBVR13_EL1)
4416 .allPrivileges().exceptUserMode()
4417 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4418 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4419 .fault(EL2, faultDebugEL2)
4420 .mapsTo(MISCREG_DBGBVR13, MISCREG_DBGBXVR13);
4421 InitReg(MISCREG_DBGBVR14_EL1)
4422 .allPrivileges().exceptUserMode()
4423 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4424 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4425 .fault(EL2, faultDebugEL2)
4426 .mapsTo(MISCREG_DBGBVR14, MISCREG_DBGBXVR14);
4427 InitReg(MISCREG_DBGBVR15_EL1)
4428 .allPrivileges().exceptUserMode()
4429 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbvrnEL1>)
4430 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbvrnEL1>)
4431 .fault(EL2, faultDebugEL2)
4432 .mapsTo(MISCREG_DBGBVR15, MISCREG_DBGBXVR15);
4433 InitReg(MISCREG_DBGBCR0_EL1)
4434 .allPrivileges().exceptUserMode()
4435 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4436 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4437 .fault(EL2, faultDebugEL2)
4438 .mapsTo(MISCREG_DBGBCR0);
4439 InitReg(MISCREG_DBGBCR1_EL1)
4440 .allPrivileges().exceptUserMode()
4441 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4442 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4443 .fault(EL2, faultDebugEL2)
4444 .mapsTo(MISCREG_DBGBCR1);
4445 InitReg(MISCREG_DBGBCR2_EL1)
4446 .allPrivileges().exceptUserMode()
4447 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4448 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4449 .fault(EL2, faultDebugEL2)
4450 .mapsTo(MISCREG_DBGBCR2);
4451 InitReg(MISCREG_DBGBCR3_EL1)
4452 .allPrivileges().exceptUserMode()
4453 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4454 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4455 .fault(EL2, faultDebugEL2)
4456 .mapsTo(MISCREG_DBGBCR3);
4457 InitReg(MISCREG_DBGBCR4_EL1)
4458 .allPrivileges().exceptUserMode()
4459 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4460 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4461 .fault(EL2, faultDebugEL2)
4462 .mapsTo(MISCREG_DBGBCR4);
4463 InitReg(MISCREG_DBGBCR5_EL1)
4464 .allPrivileges().exceptUserMode()
4465 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4466 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4467 .fault(EL2, faultDebugEL2)
4468 .mapsTo(MISCREG_DBGBCR5);
4469 InitReg(MISCREG_DBGBCR6_EL1)
4470 .allPrivileges().exceptUserMode()
4471 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4472 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4473 .fault(EL2, faultDebugEL2)
4474 .mapsTo(MISCREG_DBGBCR6);
4475 InitReg(MISCREG_DBGBCR7_EL1)
4476 .allPrivileges().exceptUserMode()
4477 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4478 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4479 .fault(EL2, faultDebugEL2)
4480 .mapsTo(MISCREG_DBGBCR7);
4481 InitReg(MISCREG_DBGBCR8_EL1)
4482 .allPrivileges().exceptUserMode()
4483 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4484 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4485 .fault(EL2, faultDebugEL2)
4486 .mapsTo(MISCREG_DBGBCR8);
4487 InitReg(MISCREG_DBGBCR9_EL1)
4488 .allPrivileges().exceptUserMode()
4489 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4490 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4491 .fault(EL2, faultDebugEL2)
4492 .mapsTo(MISCREG_DBGBCR9);
4493 InitReg(MISCREG_DBGBCR10_EL1)
4494 .allPrivileges().exceptUserMode()
4495 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4496 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4497 .fault(EL2, faultDebugEL2)
4498 .mapsTo(MISCREG_DBGBCR10);
4499 InitReg(MISCREG_DBGBCR11_EL1)
4500 .allPrivileges().exceptUserMode()
4501 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4502 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4503 .fault(EL2, faultDebugEL2)
4504 .mapsTo(MISCREG_DBGBCR11);
4505 InitReg(MISCREG_DBGBCR12_EL1)
4506 .allPrivileges().exceptUserMode()
4507 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4508 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4509 .fault(EL2, faultDebugEL2)
4510 .mapsTo(MISCREG_DBGBCR12);
4511 InitReg(MISCREG_DBGBCR13_EL1)
4512 .allPrivileges().exceptUserMode()
4513 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4514 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4515 .fault(EL2, faultDebugEL2)
4516 .mapsTo(MISCREG_DBGBCR13);
4517 InitReg(MISCREG_DBGBCR14_EL1)
4518 .allPrivileges().exceptUserMode()
4519 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4520 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4521 .fault(EL2, faultDebugEL2)
4522 .mapsTo(MISCREG_DBGBCR14);
4523 InitReg(MISCREG_DBGBCR15_EL1)
4524 .allPrivileges().exceptUserMode()
4525 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgbcrnEL1>)
4526 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgbcrnEL1>)
4527 .fault(EL2, faultDebugEL2)
4528 .mapsTo(MISCREG_DBGBCR15);
4529 InitReg(MISCREG_DBGWVR0_EL1)
4530 .allPrivileges().exceptUserMode()
4531 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4532 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4533 .fault(EL2, faultDebugEL2)
4534 .mapsTo(MISCREG_DBGWVR0);
4535 InitReg(MISCREG_DBGWVR1_EL1)
4536 .allPrivileges().exceptUserMode()
4537 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4538 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4539 .fault(EL2, faultDebugEL2)
4540 .mapsTo(MISCREG_DBGWVR1);
4541 InitReg(MISCREG_DBGWVR2_EL1)
4542 .allPrivileges().exceptUserMode()
4543 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4544 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4545 .fault(EL2, faultDebugEL2)
4546 .mapsTo(MISCREG_DBGWVR2);
4547 InitReg(MISCREG_DBGWVR3_EL1)
4548 .allPrivileges().exceptUserMode()
4549 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4550 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4551 .fault(EL2, faultDebugEL2)
4552 .mapsTo(MISCREG_DBGWVR3);
4553 InitReg(MISCREG_DBGWVR4_EL1)
4554 .allPrivileges().exceptUserMode()
4555 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4556 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4557 .fault(EL2, faultDebugEL2)
4558 .mapsTo(MISCREG_DBGWVR4);
4559 InitReg(MISCREG_DBGWVR5_EL1)
4560 .allPrivileges().exceptUserMode()
4561 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4562 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4563 .fault(EL2, faultDebugEL2)
4564 .mapsTo(MISCREG_DBGWVR5);
4565 InitReg(MISCREG_DBGWVR6_EL1)
4566 .allPrivileges().exceptUserMode()
4567 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4568 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4569 .fault(EL2, faultDebugEL2)
4570 .mapsTo(MISCREG_DBGWVR6);
4571 InitReg(MISCREG_DBGWVR7_EL1)
4572 .allPrivileges().exceptUserMode()
4573 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4574 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4575 .fault(EL2, faultDebugEL2)
4576 .mapsTo(MISCREG_DBGWVR7);
4577 InitReg(MISCREG_DBGWVR8_EL1)
4578 .allPrivileges().exceptUserMode()
4579 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4580 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4581 .fault(EL2, faultDebugEL2)
4582 .mapsTo(MISCREG_DBGWVR8);
4583 InitReg(MISCREG_DBGWVR9_EL1)
4584 .allPrivileges().exceptUserMode()
4585 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4586 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4587 .fault(EL2, faultDebugEL2)
4588 .mapsTo(MISCREG_DBGWVR9);
4589 InitReg(MISCREG_DBGWVR10_EL1)
4590 .allPrivileges().exceptUserMode()
4591 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4592 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4593 .fault(EL2, faultDebugEL2)
4594 .mapsTo(MISCREG_DBGWVR10);
4595 InitReg(MISCREG_DBGWVR11_EL1)
4596 .allPrivileges().exceptUserMode()
4597 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4598 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4599 .fault(EL2, faultDebugEL2)
4600 .mapsTo(MISCREG_DBGWVR11);
4601 InitReg(MISCREG_DBGWVR12_EL1)
4602 .allPrivileges().exceptUserMode()
4603 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4604 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4605 .fault(EL2, faultDebugEL2)
4606 .mapsTo(MISCREG_DBGWVR12);
4607 InitReg(MISCREG_DBGWVR13_EL1)
4608 .allPrivileges().exceptUserMode()
4609 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4610 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4611 .fault(EL2, faultDebugEL2)
4612 .mapsTo(MISCREG_DBGWVR13);
4613 InitReg(MISCREG_DBGWVR14_EL1)
4614 .allPrivileges().exceptUserMode()
4615 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4616 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4617 .fault(EL2, faultDebugEL2)
4618 .mapsTo(MISCREG_DBGWVR14);
4619 InitReg(MISCREG_DBGWVR15_EL1)
4620 .allPrivileges().exceptUserMode()
4621 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwvrnEL1>)
4622 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwvrnEL1>)
4623 .fault(EL2, faultDebugEL2)
4624 .mapsTo(MISCREG_DBGWVR15);
4625 InitReg(MISCREG_DBGWCR0_EL1)
4626 .allPrivileges().exceptUserMode()
4627 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4628 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4629 .fault(EL2, faultDebugEL2)
4630 .mapsTo(MISCREG_DBGWCR0);
4631 InitReg(MISCREG_DBGWCR1_EL1)
4632 .allPrivileges().exceptUserMode()
4633 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4634 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4635 .fault(EL2, faultDebugEL2)
4636 .mapsTo(MISCREG_DBGWCR1);
4637 InitReg(MISCREG_DBGWCR2_EL1)
4638 .allPrivileges().exceptUserMode()
4639 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4640 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4641 .fault(EL2, faultDebugEL2)
4642 .mapsTo(MISCREG_DBGWCR2);
4643 InitReg(MISCREG_DBGWCR3_EL1)
4644 .allPrivileges().exceptUserMode()
4645 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4646 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4647 .fault(EL2, faultDebugEL2)
4648 .mapsTo(MISCREG_DBGWCR3);
4649 InitReg(MISCREG_DBGWCR4_EL1)
4650 .allPrivileges().exceptUserMode()
4651 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4652 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4653 .fault(EL2, faultDebugEL2)
4654 .mapsTo(MISCREG_DBGWCR4);
4655 InitReg(MISCREG_DBGWCR5_EL1)
4656 .allPrivileges().exceptUserMode()
4657 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4658 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4659 .fault(EL2, faultDebugEL2)
4660 .mapsTo(MISCREG_DBGWCR5);
4661 InitReg(MISCREG_DBGWCR6_EL1)
4662 .allPrivileges().exceptUserMode()
4663 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4664 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4665 .fault(EL2, faultDebugEL2)
4666 .mapsTo(MISCREG_DBGWCR6);
4667 InitReg(MISCREG_DBGWCR7_EL1)
4668 .allPrivileges().exceptUserMode()
4669 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4670 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4671 .fault(EL2, faultDebugEL2)
4672 .mapsTo(MISCREG_DBGWCR7);
4673 InitReg(MISCREG_DBGWCR8_EL1)
4674 .allPrivileges().exceptUserMode()
4675 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4676 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4677 .fault(EL2, faultDebugEL2)
4678 .mapsTo(MISCREG_DBGWCR8);
4679 InitReg(MISCREG_DBGWCR9_EL1)
4680 .allPrivileges().exceptUserMode()
4681 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4682 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4683 .fault(EL2, faultDebugEL2)
4684 .mapsTo(MISCREG_DBGWCR9);
4685 InitReg(MISCREG_DBGWCR10_EL1)
4686 .allPrivileges().exceptUserMode()
4687 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4688 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4689 .fault(EL2, faultDebugEL2)
4690 .mapsTo(MISCREG_DBGWCR10);
4691 InitReg(MISCREG_DBGWCR11_EL1)
4692 .allPrivileges().exceptUserMode()
4693 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4694 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4695 .fault(EL2, faultDebugEL2)
4696 .mapsTo(MISCREG_DBGWCR11);
4697 InitReg(MISCREG_DBGWCR12_EL1)
4698 .allPrivileges().exceptUserMode()
4699 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4700 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4701 .fault(EL2, faultDebugEL2)
4702 .mapsTo(MISCREG_DBGWCR12);
4703 InitReg(MISCREG_DBGWCR13_EL1)
4704 .allPrivileges().exceptUserMode()
4705 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4706 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4707 .fault(EL2, faultDebugEL2)
4708 .mapsTo(MISCREG_DBGWCR13);
4709 InitReg(MISCREG_DBGWCR14_EL1)
4710 .allPrivileges().exceptUserMode()
4711 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4712 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4713 .fault(EL2, faultDebugEL2)
4714 .mapsTo(MISCREG_DBGWCR14);
4715 InitReg(MISCREG_DBGWCR15_EL1)
4716 .allPrivileges().exceptUserMode()
4717 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgwcrnEL1>)
4718 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgwcrnEL1>)
4719 .fault(EL2, faultDebugEL2)
4720 .mapsTo(MISCREG_DBGWCR15);
4721 InitReg(MISCREG_MDCCSR_EL0)
4722 .allPrivileges().writes(0)
4723 .faultRead(EL0, faultMdccsrEL0)
4724 .faultRead(EL1, faultMdccsrEL1)
4725 .faultRead(EL2, faultMdccsrEL2)
4726 .mapsTo(MISCREG_DBGDSCRint);
4727 InitReg(MISCREG_MDDTR_EL0)
4728 .allPrivileges();
4729 InitReg(MISCREG_MDDTRTX_EL0)
4730 .allPrivileges();
4731 InitReg(MISCREG_MDDTRRX_EL0)
4732 .allPrivileges();
4733 InitReg(MISCREG_DBGVCR32_EL2)
4734 .hyp().mon()
4735 .fault(EL2, faultDebugEL2)
4736 .mapsTo(MISCREG_DBGVCR);
4737 InitReg(MISCREG_MDRAR_EL1)
4738 .allPrivileges().exceptUserMode().writes(0)
4739 .faultRead(EL1, faultDebugEL1)
4740 .faultRead(EL2, faultDebugEL2)
4741 .mapsTo(MISCREG_DBGDRAR);
4742 InitReg(MISCREG_OSLAR_EL1)
4743 .allPrivileges().exceptUserMode().reads(0)
4744 .faultWrite(EL1, faultDebugOsEL1<false, &HDFGTR::oslarEL1>)
4745 .faultWrite(EL2, faultDebugOsEL2)
4746 .mapsTo(MISCREG_DBGOSLAR);
4747 InitReg(MISCREG_OSLSR_EL1)
4748 .allPrivileges().exceptUserMode().writes(0)
4749 .faultRead(EL1, faultDebugOsEL1<true, &HDFGTR::oslsrEL1>)
4750 .faultRead(EL2, faultDebugOsEL2)
4751 .mapsTo(MISCREG_DBGOSLSR);
4752 InitReg(MISCREG_OSDLR_EL1)
4753 .allPrivileges().exceptUserMode()
4754 .faultRead(EL1, faultDebugOsEL1<true, &HDFGTR::osdlrEL1>)
4755 .faultWrite(EL1, faultDebugOsEL1<false, &HDFGTR::osdlrEL1>)
4756 .fault(EL2, faultDebugOsEL2)
4757 .mapsTo(MISCREG_DBGOSDLR);
4758 InitReg(MISCREG_DBGPRCR_EL1)
4759 .allPrivileges().exceptUserMode()
4760 .faultRead(EL1, faultDebugOsEL1<true, &HDFGTR::dbgprcrEL1>)
4761 .faultWrite(EL1, faultDebugOsEL1<false, &HDFGTR::dbgprcrEL1>)
4762 .fault(EL2, faultDebugOsEL2)
4763 .mapsTo(MISCREG_DBGPRCR);
4764 InitReg(MISCREG_DBGCLAIMSET_EL1)
4765 .allPrivileges().exceptUserMode()
4766 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgclaim>)
4767 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgclaim>)
4768 .fault(EL2, faultDebugEL2)
4769 .mapsTo(MISCREG_DBGCLAIMSET);
4770 InitReg(MISCREG_DBGCLAIMCLR_EL1)
4771 .allPrivileges().exceptUserMode()
4772 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgclaim>)
4773 .faultWrite(EL1, faultDebugWithFgtEL1<false, &HDFGTR::dbgclaim>)
4774 .fault(EL2, faultDebugEL2)
4775 .mapsTo(MISCREG_DBGCLAIMCLR);
4776 InitReg(MISCREG_DBGAUTHSTATUS_EL1)
4777 .allPrivileges().exceptUserMode().writes(0)
4778 .faultRead(EL1, faultDebugWithFgtEL1<true, &HDFGTR::dbgauthstatusEL1>)
4779 .faultRead(EL2, faultDebugEL2)
4780 .mapsTo(MISCREG_DBGAUTHSTATUS);
4781 InitReg(MISCREG_TEECR32_EL1);
4782 InitReg(MISCREG_TEEHBR32_EL1);
4783
4784 // AArch64 registers (Op0=1,3);
4785 InitReg(MISCREG_MIDR_EL1)
4786 .allPrivileges().exceptUserMode().writes(0)
4787 .faultRead(EL0, faultIdst)
4788 .faultRead(EL1, faultFgtEL1<true, &HFGTR::midrEL1>)
4789 .mapsTo(MISCREG_MIDR);
4790 InitReg(MISCREG_MPIDR_EL1)
4791 .allPrivileges().exceptUserMode().writes(0)
4792 .faultRead(EL0, faultIdst)
4793 .faultRead(EL1, faultFgtEL1<true, &HFGTR::mpidrEL1>)
4794 .mapsTo(MISCREG_MPIDR);
4795 InitReg(MISCREG_REVIDR_EL1)
4796 .faultRead(EL0, faultIdst)
4797 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::tid1, &HFGTR::revidrEL1>)
4798 .allPrivileges().exceptUserMode().writes(0);
4799 InitReg(MISCREG_ID_PFR0_EL1)
4800 .allPrivileges().exceptUserMode().writes(0)
4801 .faultRead(EL0, faultIdst)
4802 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4803 .mapsTo(MISCREG_ID_PFR0);
4804 InitReg(MISCREG_ID_PFR1_EL1)
4805 .allPrivileges().exceptUserMode().writes(0)
4806 .faultRead(EL0, faultIdst)
4807 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4808 .mapsTo(MISCREG_ID_PFR1);
4809 InitReg(MISCREG_ID_DFR0_EL1)
4810 .allPrivileges().exceptUserMode().writes(0)
4811 .faultRead(EL0, faultIdst)
4812 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4813 .mapsTo(MISCREG_ID_DFR0);
4814 InitReg(MISCREG_ID_AFR0_EL1)
4815 .allPrivileges().exceptUserMode().writes(0)
4816 .faultRead(EL0, faultIdst)
4817 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4818 .mapsTo(MISCREG_ID_AFR0);
4819 InitReg(MISCREG_ID_MMFR0_EL1)
4820 .allPrivileges().exceptUserMode().writes(0)
4821 .faultRead(EL0, faultIdst)
4822 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4823 .mapsTo(MISCREG_ID_MMFR0);
4824 InitReg(MISCREG_ID_MMFR1_EL1)
4825 .allPrivileges().exceptUserMode().writes(0)
4826 .faultRead(EL0, faultIdst)
4827 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4828 .mapsTo(MISCREG_ID_MMFR1);
4829 InitReg(MISCREG_ID_MMFR2_EL1)
4830 .allPrivileges().exceptUserMode().writes(0)
4831 .faultRead(EL0, faultIdst)
4832 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4833 .mapsTo(MISCREG_ID_MMFR2);
4834 InitReg(MISCREG_ID_MMFR3_EL1)
4835 .allPrivileges().exceptUserMode().writes(0)
4836 .faultRead(EL0, faultIdst)
4837 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4838 .mapsTo(MISCREG_ID_MMFR3);
4839 InitReg(MISCREG_ID_MMFR4_EL1)
4840 .allPrivileges().exceptUserMode().writes(0)
4841 .faultRead(EL0, faultIdst)
4842 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4843 .mapsTo(MISCREG_ID_MMFR4);
4844 InitReg(MISCREG_ID_ISAR0_EL1)
4845 .allPrivileges().exceptUserMode().writes(0)
4846 .faultRead(EL0, faultIdst)
4847 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4848 .mapsTo(MISCREG_ID_ISAR0);
4849 InitReg(MISCREG_ID_ISAR1_EL1)
4850 .allPrivileges().exceptUserMode().writes(0)
4851 .faultRead(EL0, faultIdst)
4852 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4853 .mapsTo(MISCREG_ID_ISAR1);
4854 InitReg(MISCREG_ID_ISAR2_EL1)
4855 .allPrivileges().exceptUserMode().writes(0)
4856 .faultRead(EL0, faultIdst)
4857 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4858 .mapsTo(MISCREG_ID_ISAR2);
4859 InitReg(MISCREG_ID_ISAR3_EL1)
4860 .allPrivileges().exceptUserMode().writes(0)
4861 .faultRead(EL0, faultIdst)
4862 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4863 .mapsTo(MISCREG_ID_ISAR3);
4864 InitReg(MISCREG_ID_ISAR4_EL1)
4865 .allPrivileges().exceptUserMode().writes(0)
4866 .faultRead(EL0, faultIdst)
4867 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4868 .mapsTo(MISCREG_ID_ISAR4);
4869 InitReg(MISCREG_ID_ISAR5_EL1)
4870 .allPrivileges().exceptUserMode().writes(0)
4871 .faultRead(EL0, faultIdst)
4872 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4873 .mapsTo(MISCREG_ID_ISAR5);
4874 InitReg(MISCREG_ID_ISAR6_EL1)
4875 .allPrivileges().exceptUserMode().writes(0)
4876 .faultRead(EL0, faultIdst)
4877 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4878 .mapsTo(MISCREG_ID_ISAR6);
4879 InitReg(MISCREG_MVFR0_EL1)
4880 .faultRead(EL0, faultIdst)
4881 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4882 .allPrivileges().exceptUserMode().writes(0)
4883 .mapsTo(MISCREG_MVFR0);
4884 InitReg(MISCREG_MVFR1_EL1)
4885 .faultRead(EL0, faultIdst)
4886 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4887 .allPrivileges().exceptUserMode().writes(0)
4888 .mapsTo(MISCREG_MVFR1);
4889 InitReg(MISCREG_MVFR2_EL1)
4890 .faultRead(EL0, faultIdst)
4891 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4892 .allPrivileges().exceptUserMode().writes(0);
4893 InitReg(MISCREG_ID_AA64PFR0_EL1)
4894 .reset([this,release=release,tc=tc](){
4895 AA64PFR0 pfr0_el1 = 0;
4896 pfr0_el1.el0 = 0x2;
4897 pfr0_el1.el1 = 0x2;
4898 pfr0_el1.el2 = release->has(ArmExtension::VIRTUALIZATION)
4899 ? 0x2 : 0x0;
4900 pfr0_el1.el3 = release->has(ArmExtension::SECURITY) ? 0x2 : 0x0;
4901 pfr0_el1.sve = release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0;
4902 pfr0_el1.sel2 = release->has(ArmExtension::FEAT_SEL2) ? 0x1 : 0x0;
4903 // See MPAM frac in MISCREG_ID_AA64PFR1_EL1. Currently supporting
4904 // MPAMv0p1
4905 pfr0_el1.mpam = 0x0;
4906 pfr0_el1.gic = FullSystem && getGICv3CPUInterface(tc) ? 0x1 : 0;
4907 return pfr0_el1;
4908 }())
4909 .unserialize(0)
4910 .faultRead(EL0, faultIdst)
4911 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4912 .allPrivileges().writes(0);
4913 InitReg(MISCREG_ID_AA64PFR1_EL1)
4914 .reset([release=release](){
4915 AA64PFR1 pfr1_el1 = 0;
4916 pfr1_el1.sme = release->has(ArmExtension::FEAT_SME) ? 0x1 : 0x0;
4917 pfr1_el1.mpamFrac = release->has(ArmExtension::FEAT_MPAM) ?
4918 0x1 : 0x0;
4919 return pfr1_el1;
4920 }())
4921 .unserialize(0)
4922 .faultRead(EL0, faultIdst)
4923 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4924 .allPrivileges().writes(0);
4925 InitReg(MISCREG_ID_AA64DFR0_EL1)
4926 .reset([p](){
4927 AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
4928 dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
4929 return dfr0_el1;
4930 }())
4931 .faultRead(EL0, faultIdst)
4932 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4933 .allPrivileges().writes(0);
4934 InitReg(MISCREG_ID_AA64DFR1_EL1)
4935 .reset(p.id_aa64dfr1_el1)
4936 .faultRead(EL0, faultIdst)
4937 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4938 .allPrivileges().writes(0);
4939 InitReg(MISCREG_ID_AA64AFR0_EL1)
4940 .reset(p.id_aa64afr0_el1)
4941 .faultRead(EL0, faultIdst)
4942 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4943 .allPrivileges().writes(0);
4944 InitReg(MISCREG_ID_AA64AFR1_EL1)
4945 .reset(p.id_aa64afr1_el1)
4946 .faultRead(EL0, faultIdst)
4947 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4948 .allPrivileges().writes(0);
4949 InitReg(MISCREG_ID_AA64ISAR0_EL1)
4950 .reset([p,release=release](){
4951 AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
4952 isar0_el1.crc32 = release->has(ArmExtension::FEAT_CRC32) ? 0x1 : 0x0;
4953 isar0_el1.sha2 = release->has(ArmExtension::FEAT_SHA256) ? 0x1 : 0x0;
4954 isar0_el1.sha1 = release->has(ArmExtension::FEAT_SHA1) ? 0x1 : 0x0;
4955 isar0_el1.aes = release->has(ArmExtension::FEAT_PMULL) ?
4956 0x2 : release->has(ArmExtension::FEAT_AES) ?
4957 0x1 : 0x0;
4958 isar0_el1.dp = release->has(ArmExtension::FEAT_DOTPROD) ? 0x1 : 0x0;
4959 isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 : 0x0;
4960 isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
4961 isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
4962 isar0_el1.tlb = release->has(ArmExtension::FEAT_TLBIRANGE) ?
4963 0x2 : release->has(ArmExtension::FEAT_TLBIOS) ?
4964 0x1 : 0x0;
4965 isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
4966 0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
4967 0x1 : 0x0;
4968 isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 : 0x0;
4969 return isar0_el1;
4970 }())
4971 .faultRead(EL0, faultIdst)
4972 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4973 .allPrivileges().writes(0);
4974 InitReg(MISCREG_ID_AA64ISAR1_EL1)
4975 .reset([p,release=release](){
4976 AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
4977 isar1_el1.xs = release->has(ArmExtension::FEAT_XS) ? 0x1 : 0x0;
4978 isar1_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 0x1 : 0x0;
4979 isar1_el1.apa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0;
4980 isar1_el1.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
4981 isar1_el1.fcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
4982 isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 : 0x0;
4983 return isar1_el1;
4984 }())
4985 .faultRead(EL0, faultIdst)
4986 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4987 .allPrivileges().writes(0);
4988 InitReg(MISCREG_ID_AA64MMFR0_EL1)
4989 .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
4990 AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
4991 mmfr0_el1.asidbits = asidbits ? 0x2 : 0x0;
4992 mmfr0_el1.parange = encodePhysAddrRange64(parange);
4993 return mmfr0_el1;
4994 }())
4995 .faultRead(EL0, faultIdst)
4996 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
4997 .allPrivileges().writes(0);
4998 InitReg(MISCREG_ID_AA64MMFR1_EL1)
4999 .reset([p,release=release](){
5000 AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
5001 mmfr1_el1.vmidbits =
5002 release->has(ArmExtension::FEAT_VMID16) ? 0x2 : 0x0;
5003 mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
5004 mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 : 0x0;
5005 mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
5006 mmfr1_el1.hcx = release->has(ArmExtension::FEAT_HCX) ? 0x1 : 0x0;
5007 return mmfr1_el1;
5008 }())
5009 .faultRead(EL0, faultIdst)
5010 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
5011 .allPrivileges().writes(0);
5012 InitReg(MISCREG_ID_AA64MMFR2_EL1)
5013 .reset([p,release=release](){
5014 AA64MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
5015 mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
5016 mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0;
5017 mmfr2_el1.st = release->has(ArmExtension::FEAT_TTST) ? 0x1 : 0x0;
5018 mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 : 0x0;
5019 mmfr2_el1.evt = release->has(ArmExtension::FEAT_EVT) ? 0x2 : 0x0;
5020 return mmfr2_el1;
5021 }())
5022 .faultRead(EL0, faultIdst)
5023 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
5024 .allPrivileges().writes(0);
5025 InitReg(MISCREG_ID_AA64MMFR3_EL1)
5026 .reset([p,release=release](){
5027 AA64MMFR3 mmfr3_el1 = 0;
5028 mmfr3_el1.sctlrx =
5029 release->has(ArmExtension::FEAT_SCTLR2) ? 0x1 : 0x0;
5030 mmfr3_el1.tcrx = release->has(ArmExtension::FEAT_TCR2) ? 0x1 : 0x0;
5031 return mmfr3_el1;
5032 }())
5033 .faultRead(EL0, faultIdst)
5034 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
5035 .allPrivileges().writes(0);
5036
5037 InitReg(MISCREG_APDAKeyHi_EL1)
5038 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdaKey>)
5039 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdaKey>)
5040 .fault(EL2, faultPauthEL2)
5041 .allPrivileges().exceptUserMode();
5042 InitReg(MISCREG_APDAKeyLo_EL1)
5043 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdaKey>)
5044 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdaKey>)
5045 .fault(EL2, faultPauthEL2)
5046 .allPrivileges().exceptUserMode();
5047 InitReg(MISCREG_APDBKeyHi_EL1)
5048 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdbKey>)
5049 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdbKey>)
5050 .fault(EL2, faultPauthEL2)
5051 .allPrivileges().exceptUserMode();
5052 InitReg(MISCREG_APDBKeyLo_EL1)
5053 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apdbKey>)
5054 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apdbKey>)
5055 .fault(EL2, faultPauthEL2)
5056 .allPrivileges().exceptUserMode();
5057 InitReg(MISCREG_APGAKeyHi_EL1)
5058 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apgaKey>)
5059 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apgaKey>)
5060 .fault(EL2, faultPauthEL2)
5061 .allPrivileges().exceptUserMode();
5062 InitReg(MISCREG_APGAKeyLo_EL1)
5063 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apgaKey>)
5064 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apgaKey>)
5065 .fault(EL2, faultPauthEL2)
5066 .allPrivileges().exceptUserMode();
5067 InitReg(MISCREG_APIAKeyHi_EL1)
5068 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apiaKey>)
5069 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apiaKey>)
5070 .fault(EL2, faultPauthEL2)
5071 .allPrivileges().exceptUserMode();
5072 InitReg(MISCREG_APIAKeyLo_EL1)
5073 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apiaKey>)
5074 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apiaKey>)
5075 .fault(EL2, faultPauthEL2)
5076 .allPrivileges().exceptUserMode();
5077 InitReg(MISCREG_APIBKeyHi_EL1)
5078 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apibKey>)
5079 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apibKey>)
5080 .fault(EL2, faultPauthEL2)
5081 .allPrivileges().exceptUserMode();
5082 InitReg(MISCREG_APIBKeyLo_EL1)
5083 .faultRead(EL1, faultPauthEL1<true, &HFGTR::apibKey>)
5084 .faultWrite(EL1, faultPauthEL1<false, &HFGTR::apibKey>)
5085 .fault(EL2, faultPauthEL2)
5086 .allPrivileges().exceptUserMode();
5087
5088 InitReg(MISCREG_CCSIDR_EL1)
5089 .faultRead(EL0, faultIdst)
5090 .faultRead(EL1, faultCacheEL1<true, &HFGTR::ccsidrEL1>)
5091 .allPrivileges().writes(0);
5092 InitReg(MISCREG_CLIDR_EL1)
5093 .faultRead(EL0, faultIdst)
5094 .faultRead(EL1, faultCacheEL1<true, &HFGTR::clidrEL1>)
5095 .allPrivileges().writes(0);
5096 InitReg(MISCREG_AIDR_EL1)
5097 .faultRead(EL0, faultIdst)
5098 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::tid1, &HFGTR::aidrEL1>)
5099 .allPrivileges().writes(0);
5100 InitReg(MISCREG_CSSELR_EL1)
5101 .allPrivileges().exceptUserMode()
5102 .faultRead(EL1, faultCacheEL1<true, &HFGTR::csselrEL1>)
5103 .faultWrite(EL1, faultCacheEL1<false, &HFGTR::csselrEL1>)
5104 .mapsTo(MISCREG_CSSELR_NS);
5105 InitReg(MISCREG_CTR_EL0)
5106 .faultRead(EL0, faultCtrEL0)
5107 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::tid2, &HFGTR::ctrEL0>)
5108 .reads(1)
5109 .mapsTo(MISCREG_CTR);
5110 InitReg(MISCREG_DCZID_EL0)
5111 .reset(0x04) // DC ZVA clear 64-byte chunks
5112 .faultRead(EL0, faultFgtEL0<true, &HFGTR::dczidEL0>)
5113 .faultRead(EL1, faultFgtEL1<true, &HFGTR::dczidEL0>)
5114 .reads(1);
5115 InitReg(MISCREG_VPIDR_EL2)
5116 .hyp().mon()
5117 .mapsTo(MISCREG_VPIDR);
5118 InitReg(MISCREG_VMPIDR_EL2)
5119 .hyp().mon()
5120 .res0(mask(63, 40) | mask(29, 25))
5121 .res1(mask(31, 31))
5122 .mapsTo(MISCREG_VMPIDR);
5123 InitReg(MISCREG_SCTLR_EL1)
5124 .allPrivileges().exceptUserMode()
5125 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::sctlrEL1>)
5126 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::sctlrEL1>)
5127 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
5128 | (IESB ? 0 : 0x200000)
5129 | (EnDA ? 0 : 0x8000000)
5130 | (EnIB ? 0 : 0x40000000)
5131 | (EnIA ? 0 : 0x80000000))
5132 .res1(0x500800 | (SPAN ? 0 : 0x800000)
5133 | (nTLSMD ? 0 : 0x8000000)
5134 | (LSMAOE ? 0 : 0x10000000))
5135 .mapsTo(MISCREG_SCTLR_NS);
5136 InitReg(MISCREG_SCTLR_EL12)
5137 .fault(EL2, defaultFaultE2H_EL2)
5138 .fault(EL3, defaultFaultE2H_EL3)
5139 .res0( 0x20440 | (EnDB ? 0 : 0x2000)
5140 | (IESB ? 0 : 0x200000)
5141 | (EnDA ? 0 : 0x8000000)
5142 | (EnIB ? 0 : 0x40000000)
5143 | (EnIA ? 0 : 0x80000000))
5144 .res1(0x500800 | (SPAN ? 0 : 0x800000)
5145 | (nTLSMD ? 0 : 0x8000000)
5146 | (LSMAOE ? 0 : 0x10000000))
5147 .mapsTo(MISCREG_SCTLR_EL1);
5148 InitReg(MISCREG_SCTLR2_EL1)
5149 .allPrivileges().exceptUserMode()
5150 .faultRead(EL1, faultSctlr2EL1<true, &HCR::trvm>)
5151 .faultWrite(EL1, faultSctlr2EL1<false, &HCR::tvm>)
5152 .fault(EL2,faultSctlr2EL2);
5153 InitReg(MISCREG_SCTLR2_EL12)
5154 .fault(EL2, faultSctlr2VheEL2)
5155 .fault(EL3, defaultFaultE2H_EL3)
5156 .mapsTo(MISCREG_SCTLR2_EL1);
5157 InitReg(MISCREG_ACTLR_EL1)
5158 .allPrivileges().exceptUserMode()
5159 .fault(EL1, faultHcrEL1<&HCR::tacr>)
5160 .mapsTo(MISCREG_ACTLR_NS);
5161 InitReg(MISCREG_CPACR_EL1)
5162 .allPrivileges().exceptUserMode()
5163 .faultRead(EL1, faultCpacrEL1<true, &HFGTR::cpacrEL1>)
5164 .faultWrite(EL1, faultCpacrEL1<false, &HFGTR::cpacrEL1>)
5165 .fault(EL2, faultCpacrEL2)
5166 .mapsTo(MISCREG_CPACR);
5167 InitReg(MISCREG_CPACR_EL12)
5168 .fault(EL2, faultCpacrVheEL2)
5169 .fault(EL3, defaultFaultE2H_EL3)
5170 .mapsTo(MISCREG_CPACR_EL1);
5171 InitReg(MISCREG_SCTLR_EL2)
5172 .hyp().mon()
5173 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
5174 | (IESB ? 0 : 0x200000)
5175 | (EnDA ? 0 : 0x8000000)
5176 | (EnIB ? 0 : 0x40000000)
5177 | (EnIA ? 0 : 0x80000000))
5178 .res1(0x30c50830)
5179 .mapsTo(MISCREG_HSCTLR);
5180 InitReg(MISCREG_SCTLR2_EL2)
5181 .hyp().mon()
5182 .fault(EL2, faultSctlr2EL2);
5183 InitReg(MISCREG_ACTLR_EL2)
5184 .hyp().mon()
5185 .mapsTo(MISCREG_HACTLR);
5186 InitReg(MISCREG_HCR_EL2)
5187 .hyp().mon()
5188 .mapsTo(MISCREG_HCR, MISCREG_HCR2);
5189 InitReg(MISCREG_HCRX_EL2)
5190 .hyp().mon()
5191 .fault(EL2, faultHcrxEL2);
5192 InitReg(MISCREG_MDCR_EL2)
5193 .hyp().mon()
5194 .fault(EL2, faultDebugEL2)
5195 .mapsTo(MISCREG_HDCR);
5196 InitReg(MISCREG_CPTR_EL2)
5197 .hyp().mon()
5198 .fault(EL2, faultCpacrEL2)
5199 .mapsTo(MISCREG_HCPTR);
5200 InitReg(MISCREG_HSTR_EL2)
5201 .hyp().mon()
5202 .mapsTo(MISCREG_HSTR);
5203 InitReg(MISCREG_HACR_EL2)
5204 .hyp().mon()
5205 .mapsTo(MISCREG_HACR);
5206 InitReg(MISCREG_SCTLR_EL3)
5207 .reset(0x30c50830)
5208 .mon()
5209 .res0(0x0512c7c0 | (EnDB ? 0 : 0x2000)
5210 | (IESB ? 0 : 0x200000)
5211 | (EnDA ? 0 : 0x8000000)
5212 | (EnIB ? 0 : 0x40000000)
5213 | (EnIA ? 0 : 0x80000000))
5214 .res1(0x30c50830);
5215 InitReg(MISCREG_SCTLR2_EL3)
5216 .mon();
5217 InitReg(MISCREG_ACTLR_EL3)
5218 .mon();
5219 InitReg(MISCREG_SCR_EL3)
5220 .mon()
5221 .mapsTo(MISCREG_SCR); // NAM D7-2005
5222 InitReg(MISCREG_SDER32_EL3)
5223 .mon()
5224 .mapsTo(MISCREG_SDER);
5225 InitReg(MISCREG_CPTR_EL3)
5226 .mon();
5227 InitReg(MISCREG_MDCR_EL3)
5228 .mon()
5229 .mapsTo(MISCREG_SDCR);
5230 InitReg(MISCREG_TTBR0_EL1)
5231 .allPrivileges().exceptUserMode()
5232 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::ttbr0EL1>)
5233 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::ttbr0EL1>)
5234 .mapsTo(MISCREG_TTBR0_NS);
5235 InitReg(MISCREG_TTBR0_EL12)
5236 .fault(EL2, defaultFaultE2H_EL2)
5237 .fault(EL3, defaultFaultE2H_EL3)
5238 .mapsTo(MISCREG_TTBR0_EL1);
5239 InitReg(MISCREG_TTBR1_EL1)
5240 .allPrivileges().exceptUserMode()
5241 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::ttbr1EL1>)
5242 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::ttbr1EL1>)
5243 .mapsTo(MISCREG_TTBR1_NS);
5244 InitReg(MISCREG_TTBR1_EL12)
5245 .fault(EL2, defaultFaultE2H_EL2)
5246 .fault(EL3, defaultFaultE2H_EL3)
5247 .mapsTo(MISCREG_TTBR1_EL1);
5248 InitReg(MISCREG_TCR_EL1)
5249 .allPrivileges().exceptUserMode()
5250 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::tcrEL1>)
5251 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::tcrEL1>)
5252 .mapsTo(MISCREG_TTBCR_NS);
5253 InitReg(MISCREG_TCR_EL12)
5254 .fault(EL2, defaultFaultE2H_EL2)
5255 .fault(EL3, defaultFaultE2H_EL3)
5256 .mapsTo(MISCREG_TTBCR_NS);
5257 InitReg(MISCREG_TCR2_EL1)
5258 .allPrivileges().exceptUserMode()
5259 .faultRead(EL1, faultTcr2EL1<true, &HCR::trvm>)
5260 .faultWrite(EL1, faultTcr2EL1<false, &HCR::tvm>)
5261 .fault(EL2, faultTcr2EL2);
5262 InitReg(MISCREG_TCR2_EL12)
5263 .fault(EL2, faultTcr2VheEL2)
5264 .fault(EL3, faultTcr2VheEL3)
5265 .mapsTo(MISCREG_TCR2_EL1);
5266 InitReg(MISCREG_TTBR0_EL2)
5267 .hyp().mon()
5268 .mapsTo(MISCREG_HTTBR);
5269 InitReg(MISCREG_TTBR1_EL2)
5270 .hyp().mon();
5271 InitReg(MISCREG_TCR_EL2)
5272 .hyp().mon()
5273 .mapsTo(MISCREG_HTCR);
5274 InitReg(MISCREG_TCR2_EL2)
5275 .hyp().mon()
5276 .fault(EL2, faultTcr2EL2);
5277 InitReg(MISCREG_VTTBR_EL2)
5278 .hyp().mon()
5279 .mapsTo(MISCREG_VTTBR);
5280 InitReg(MISCREG_VTCR_EL2)
5281 .hyp().mon()
5282 .mapsTo(MISCREG_VTCR);
5283 InitReg(MISCREG_VSTTBR_EL2)
5284 .hypSecure().mon();
5285 InitReg(MISCREG_VSTCR_EL2)
5286 .hypSecure().mon();
5287 InitReg(MISCREG_TTBR0_EL3)
5288 .mon();
5289 InitReg(MISCREG_TCR_EL3)
5290 .mon();
5291 InitReg(MISCREG_DACR32_EL2)
5292 .hyp().mon()
5293 .mapsTo(MISCREG_DACR_NS);
5294 InitReg(MISCREG_SPSR_EL1)
5295 .allPrivileges().exceptUserMode()
5296 .mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
5297 InitReg(MISCREG_SPSR_EL12)
5298 .fault(EL2, defaultFaultE2H_EL2)
5299 .fault(EL3, defaultFaultE2H_EL3)
5300 .mapsTo(MISCREG_SPSR_SVC);
5301 InitReg(MISCREG_ELR_EL1)
5302 .allPrivileges().exceptUserMode();
5303 InitReg(MISCREG_ELR_EL12)
5304 .fault(EL2, defaultFaultE2H_EL2)
5305 .fault(EL3, defaultFaultE2H_EL3)
5306 .mapsTo(MISCREG_ELR_EL1);
5307 InitReg(MISCREG_SP_EL0)
5308 .allPrivileges().exceptUserMode()
5309 .fault(EL1, faultSpEL0)
5310 .fault(EL2, faultSpEL0)
5311 .fault(EL3, faultSpEL0);
5312 InitReg(MISCREG_SPSEL)
5313 .allPrivileges().exceptUserMode();
5314 InitReg(MISCREG_CURRENTEL)
5315 .allPrivileges().exceptUserMode().writes(0);
5316 InitReg(MISCREG_PAN)
5317 .allPrivileges(release->has(ArmExtension::FEAT_PAN))
5318 .exceptUserMode();
5319 InitReg(MISCREG_UAO)
5320 .allPrivileges().exceptUserMode();
5321 InitReg(MISCREG_NZCV)
5322 .allPrivileges();
5323 InitReg(MISCREG_DAIF)
5324 .allPrivileges()
5325 .fault(EL0, faultDaif);
5326 InitReg(MISCREG_FPCR)
5327 .allPrivileges()
5328 .fault(EL0, faultFpcrEL0)
5329 .fault(EL1, faultFpcrEL1)
5330 .fault(EL2, faultFpcrEL2)
5331 .fault(EL3, faultFpcrEL3);
5332 InitReg(MISCREG_FPSR)
5333 .allPrivileges()
5334 .fault(EL0, faultFpcrEL0)
5335 .fault(EL1, faultFpcrEL1)
5336 .fault(EL2, faultFpcrEL2)
5337 .fault(EL3, faultFpcrEL3);
5338 InitReg(MISCREG_DSPSR_EL0)
5339 .allPrivileges();
5340 InitReg(MISCREG_DLR_EL0)
5341 .allPrivileges();
5342 InitReg(MISCREG_SPSR_EL2)
5343 .hyp().mon()
5344 .mapsTo(MISCREG_SPSR_HYP); // NAM C5.2.18 SPSR_EL2
5345 InitReg(MISCREG_ELR_EL2)
5346 .hyp().mon();
5347 InitReg(MISCREG_SP_EL1)
5348 .hyp().mon();
5349 InitReg(MISCREG_SPSR_IRQ_AA64)
5350 .hyp().mon();
5351 InitReg(MISCREG_SPSR_ABT_AA64)
5352 .hyp().mon();
5353 InitReg(MISCREG_SPSR_UND_AA64)
5354 .hyp().mon();
5355 InitReg(MISCREG_SPSR_FIQ_AA64)
5356 .hyp().mon();
5357 InitReg(MISCREG_SPSR_EL3)
5358 .mon()
5359 .mapsTo(MISCREG_SPSR_MON); // NAM C5.2.19 SPSR_EL3
5360 InitReg(MISCREG_ELR_EL3)
5361 .mon();
5362 InitReg(MISCREG_SP_EL2)
5363 .mon();
5364 InitReg(MISCREG_AFSR0_EL1)
5365 .allPrivileges().exceptUserMode()
5366 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::afsr0EL1>)
5367 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::afsr0EL1>)
5368 .mapsTo(MISCREG_ADFSR_NS);
5369 InitReg(MISCREG_AFSR0_EL12)
5370 .fault(EL2, defaultFaultE2H_EL2)
5371 .fault(EL3, defaultFaultE2H_EL3)
5372 .mapsTo(MISCREG_ADFSR_NS);
5373 InitReg(MISCREG_AFSR1_EL1)
5374 .allPrivileges().exceptUserMode()
5375 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::afsr1EL1>)
5376 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::afsr1EL1>)
5377 .mapsTo(MISCREG_AIFSR_NS);
5378 InitReg(MISCREG_AFSR1_EL12)
5379 .fault(EL2, defaultFaultE2H_EL2)
5380 .fault(EL3, defaultFaultE2H_EL3)
5381 .mapsTo(MISCREG_AIFSR_NS);
5382 InitReg(MISCREG_ESR_EL1)
5383 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::esrEL1>)
5384 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::esrEL1>)
5385 .allPrivileges().exceptUserMode();
5386 InitReg(MISCREG_ESR_EL12)
5387 .fault(EL2, defaultFaultE2H_EL2)
5388 .fault(EL3, defaultFaultE2H_EL3)
5389 .mapsTo(MISCREG_ESR_EL1);
5390 InitReg(MISCREG_IFSR32_EL2)
5391 .hyp().mon()
5392 .mapsTo(MISCREG_IFSR_NS);
5393 InitReg(MISCREG_AFSR0_EL2)
5394 .hyp().mon()
5395 .mapsTo(MISCREG_HADFSR);
5396 InitReg(MISCREG_AFSR1_EL2)
5397 .hyp().mon()
5398 .mapsTo(MISCREG_HAIFSR);
5399 InitReg(MISCREG_ESR_EL2)
5400 .hyp().mon()
5401 .mapsTo(MISCREG_HSR);
5402 InitReg(MISCREG_FPEXC32_EL2)
5403 .fault(EL2, faultFpcrEL2)
5404 .fault(EL3, faultFpcrEL3)
5405 .mapsTo(MISCREG_FPEXC);
5406 InitReg(MISCREG_AFSR0_EL3)
5407 .mon();
5408 InitReg(MISCREG_AFSR1_EL3)
5409 .mon();
5410 InitReg(MISCREG_ESR_EL3)
5411 .mon();
5412 InitReg(MISCREG_FAR_EL1)
5413 .allPrivileges().exceptUserMode()
5414 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::farEL1>)
5415 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::farEL1>)
5416 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
5417 InitReg(MISCREG_FAR_EL12)
5418 .fault(EL2, defaultFaultE2H_EL2)
5419 .fault(EL3, defaultFaultE2H_EL3)
5420 .mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
5421 InitReg(MISCREG_FAR_EL2)
5422 .hyp().mon()
5423 .mapsTo(MISCREG_HDFAR, MISCREG_HIFAR);
5424 InitReg(MISCREG_HPFAR_EL2)
5425 .hyp().mon()
5426 .mapsTo(MISCREG_HPFAR);
5427 InitReg(MISCREG_FAR_EL3)
5428 .mon();
5429 InitReg(MISCREG_IC_IALLUIS)
5430 .warnNotFail()
5431 .faultWrite(EL1, faultPouIsEL1<&HFGITR::icialluis>)
5432 .writes(1).exceptUserMode();
5433 InitReg(MISCREG_PAR_EL1)
5434 .allPrivileges().exceptUserMode()
5435 .mapsTo(MISCREG_PAR_NS);
5436 InitReg(MISCREG_IC_IALLU)
5437 .warnNotFail()
5438 .faultWrite(EL1, faultPouEL1<&HFGITR::iciallu>)
5439 .writes(1).exceptUserMode();
5440 InitReg(MISCREG_DC_IVAC_Xt)
5441 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tpc, &HFGITR::dcivac>)
5442 .writes(1).exceptUserMode();
5443 InitReg(MISCREG_DC_ISW_Xt)
5444 .warnNotFail()
5445 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tsw, &HFGITR::dcisw>)
5446 .writes(1).exceptUserMode();
5447 InitReg(MISCREG_AT_S1E1R_Xt)
5448 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e1r>)
5449 .writes(1).exceptUserMode();
5450 InitReg(MISCREG_AT_S1E1W_Xt)
5451 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e1w>)
5452 .writes(1).exceptUserMode();
5453 InitReg(MISCREG_AT_S1E0R_Xt)
5454 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e0r>)
5455 .writes(1).exceptUserMode();
5456 InitReg(MISCREG_AT_S1E0W_Xt)
5457 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::at, &HFGITR::ats1e0w>)
5458 .writes(1).exceptUserMode();
5459 InitReg(MISCREG_DC_CSW_Xt)
5460 .warnNotFail()
5461 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tsw, &HFGITR::dccsw>)
5462 .writes(1).exceptUserMode();
5463 InitReg(MISCREG_DC_CISW_Xt)
5464 .warnNotFail()
5465 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tsw, &HFGITR::dccisw>)
5466 .writes(1).exceptUserMode();
5467 InitReg(MISCREG_DC_ZVA_Xt)
5468 .writes(1)
5469 .faultWrite(EL0, faultDczvaEL0)
5470 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tdz, &HFGITR::dczva>);
5471 InitReg(MISCREG_IC_IVAU_Xt)
5472 .faultWrite(EL0, faultPouEL0)
5473 .faultWrite(EL1, faultPouEL1<&HFGITR::icivau>)
5474 .writes(1);
5475 InitReg(MISCREG_DC_CVAC_Xt)
5476 .faultWrite(EL0, faultCvacEL0)
5477 .faultWrite(EL1, faultHcrEL1<&HCR::tpc>)
5478 .writes(1);
5479 InitReg(MISCREG_DC_CVAU_Xt)
5480 .faultWrite(EL0, faultPouEL0)
5481 .faultWrite(EL1, faultPouEL1<&HFGITR::dccvau>)
5482 .writes(1);
5483 InitReg(MISCREG_DC_CIVAC_Xt)
5484 .faultWrite(EL0, faultCvacEL0)
5485 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::tpc, &HFGITR::dccivac>)
5486 .writes(1);
5487 InitReg(MISCREG_AT_S1E2R_Xt)
5488 .monWrite().hypWrite();
5489 InitReg(MISCREG_AT_S1E2W_Xt)
5490 .monWrite().hypWrite();
5491 InitReg(MISCREG_AT_S12E1R_Xt)
5492 .hypWrite().monSecureWrite().monNonSecureWrite();
5493 InitReg(MISCREG_AT_S12E1W_Xt)
5494 .hypWrite().monSecureWrite().monNonSecureWrite();
5495 InitReg(MISCREG_AT_S12E0R_Xt)
5496 .hypWrite().monSecureWrite().monNonSecureWrite();
5497 InitReg(MISCREG_AT_S12E0W_Xt)
5498 .hypWrite().monSecureWrite().monNonSecureWrite();
5499 InitReg(MISCREG_AT_S1E3R_Xt)
5500 .monSecureWrite().monNonSecureWrite();
5501 InitReg(MISCREG_AT_S1E3W_Xt)
5502 .monSecureWrite().monNonSecureWrite();
5503 InitReg(MISCREG_TLBI_VMALLE1OS)
5504 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivmalle1os>)
5505 .writes(1).exceptUserMode();
5506 InitReg(MISCREG_TLBI_VAE1OS)
5507 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivae1os>)
5508 .writes(1).exceptUserMode();
5509 InitReg(MISCREG_TLBI_ASIDE1OS)
5510 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbiaside1os>)
5511 .writes(1).exceptUserMode();
5512 InitReg(MISCREG_TLBI_VAAE1OS)
5513 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaae1os>)
5514 .writes(1).exceptUserMode();
5515 InitReg(MISCREG_TLBI_VALE1OS)
5516 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivale1os>)
5517 .writes(1).exceptUserMode();
5518 InitReg(MISCREG_TLBI_VAALE1OS)
5519 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbivaale1os>)
5520 .writes(1).exceptUserMode();
5521 InitReg(MISCREG_TLBI_VMALLE1IS)
5522 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivmalle1is>)
5523 .writes(1).exceptUserMode();
5524 InitReg(MISCREG_TLBI_VAE1IS)
5525 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivae1is>)
5526 .writes(1).exceptUserMode();
5527 InitReg(MISCREG_TLBI_ASIDE1IS)
5528 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbiaside1is>)
5529 .writes(1).exceptUserMode();
5530 InitReg(MISCREG_TLBI_VAAE1IS)
5531 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaae1is>)
5532 .writes(1).exceptUserMode();
5533 InitReg(MISCREG_TLBI_VALE1IS)
5534 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivale1is>)
5535 .writes(1).exceptUserMode();
5536 InitReg(MISCREG_TLBI_VAALE1IS)
5537 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbivaale1is>)
5538 .writes(1).exceptUserMode();
5539 InitReg(MISCREG_TLBI_VMALLE1)
5540 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivmalle1>)
5541 .writes(1).exceptUserMode();
5542 InitReg(MISCREG_TLBI_VAE1)
5543 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivae1>)
5544 .writes(1).exceptUserMode();
5545 InitReg(MISCREG_TLBI_ASIDE1)
5546 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbiaside1>)
5547 .writes(1).exceptUserMode();
5548 InitReg(MISCREG_TLBI_VAAE1)
5549 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaae1>)
5550 .writes(1).exceptUserMode();
5551 InitReg(MISCREG_TLBI_VALE1)
5552 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivale1>)
5553 .writes(1).exceptUserMode();
5554 InitReg(MISCREG_TLBI_VAALE1)
5555 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
5556 .writes(1).exceptUserMode();
5557 InitReg(MISCREG_TLBI_IPAS2E1OS)
5558 .monWrite().hypWrite();
5559 InitReg(MISCREG_TLBI_IPAS2LE1OS)
5560 .monWrite().hypWrite();
5561 InitReg(MISCREG_TLBI_ALLE2OS)
5562 .monWrite().hypWrite();
5563 InitReg(MISCREG_TLBI_VAE2OS)
5564 .monWrite().hypWrite();
5565 InitReg(MISCREG_TLBI_ALLE1OS)
5566 .monWrite().hypWrite();
5567 InitReg(MISCREG_TLBI_VALE2OS)
5568 .monWrite().hypWrite();
5569 InitReg(MISCREG_TLBI_VMALLS12E1OS)
5570 .monWrite().hypWrite();
5571 InitReg(MISCREG_TLBI_IPAS2E1IS)
5572 .monWrite().hypWrite();
5573 InitReg(MISCREG_TLBI_IPAS2LE1IS)
5574 .monWrite().hypWrite();
5575 InitReg(MISCREG_TLBI_ALLE2IS)
5576 .monWrite().hypWrite();
5577 InitReg(MISCREG_TLBI_VAE2IS)
5578 .monWrite().hypWrite();
5579 InitReg(MISCREG_TLBI_ALLE1IS)
5580 .monWrite().hypWrite();
5581 InitReg(MISCREG_TLBI_VALE2IS)
5582 .monWrite().hypWrite();
5583 InitReg(MISCREG_TLBI_VMALLS12E1IS)
5584 .monWrite().hypWrite();
5585 InitReg(MISCREG_TLBI_IPAS2E1)
5586 .monWrite().hypWrite();
5587 InitReg(MISCREG_TLBI_IPAS2LE1)
5588 .monWrite().hypWrite();
5589 InitReg(MISCREG_TLBI_ALLE2)
5590 .monWrite().hypWrite();
5591 InitReg(MISCREG_TLBI_VAE2)
5592 .monWrite().hypWrite();
5593 InitReg(MISCREG_TLBI_ALLE1)
5594 .monWrite().hypWrite();
5595 InitReg(MISCREG_TLBI_VALE2)
5596 .monWrite().hypWrite();
5597 InitReg(MISCREG_TLBI_VMALLS12E1)
5598 .monWrite().hypWrite();
5599 InitReg(MISCREG_TLBI_ALLE3OS)
5600 .monSecureWrite().monNonSecureWrite();
5601 InitReg(MISCREG_TLBI_VAE3OS)
5602 .monSecureWrite().monNonSecureWrite();
5603 InitReg(MISCREG_TLBI_VALE3OS)
5604 .monSecureWrite().monNonSecureWrite();
5605 InitReg(MISCREG_TLBI_ALLE3IS)
5606 .monSecureWrite().monNonSecureWrite();
5607 InitReg(MISCREG_TLBI_VAE3IS)
5608 .monSecureWrite().monNonSecureWrite();
5609 InitReg(MISCREG_TLBI_VALE3IS)
5610 .monSecureWrite().monNonSecureWrite();
5611 InitReg(MISCREG_TLBI_ALLE3)
5612 .monSecureWrite().monNonSecureWrite();
5613 InitReg(MISCREG_TLBI_VAE3)
5614 .monSecureWrite().monNonSecureWrite();
5615 InitReg(MISCREG_TLBI_VALE3)
5616 .monSecureWrite().monNonSecureWrite();
5617
5618 InitReg(MISCREG_TLBI_RVAE1)
5619 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvae1>)
5620 .writes(1).exceptUserMode();
5621 InitReg(MISCREG_TLBI_RVAAE1)
5622 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaae1>)
5623 .writes(1).exceptUserMode();
5624 InitReg(MISCREG_TLBI_RVALE1)
5625 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvale1>)
5626 .writes(1).exceptUserMode();
5627 InitReg(MISCREG_TLBI_RVAALE1)
5628 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaale1>)
5629 .writes(1).exceptUserMode();
5630 InitReg(MISCREG_TLBI_RIPAS2E1)
5631 .hypWrite().monWrite();
5632 InitReg(MISCREG_TLBI_RIPAS2LE1)
5633 .hypWrite().monWrite();
5634 InitReg(MISCREG_TLBI_RVAE2)
5635 .hypWrite().monWrite();
5636 InitReg(MISCREG_TLBI_RVALE2)
5637 .hypWrite().monWrite();
5638 InitReg(MISCREG_TLBI_RVAE3)
5639 .monWrite();
5640 InitReg(MISCREG_TLBI_RVALE3)
5641 .monWrite();
5642 InitReg(MISCREG_TLBI_RVAE1IS)
5643 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvae1is>)
5644 .writes(1).exceptUserMode();
5645 InitReg(MISCREG_TLBI_RVAAE1IS)
5646 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvaae1is>)
5647 .writes(1).exceptUserMode();
5648 InitReg(MISCREG_TLBI_RVALE1IS)
5649 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvale1is>)
5650 .writes(1).exceptUserMode();
5651 InitReg(MISCREG_TLBI_RVAALE1IS)
5652 .faultWrite(EL1, faultTlbiIsEL1<&HFGITR::tlbirvaale1is>)
5653 .writes(1).exceptUserMode();
5654 InitReg(MISCREG_TLBI_RIPAS2E1IS)
5655 .hypWrite().monWrite();
5656 InitReg(MISCREG_TLBI_RIPAS2LE1IS)
5657 .hypWrite().monWrite();
5658 InitReg(MISCREG_TLBI_RVAE2IS)
5659 .hypWrite().monWrite();
5660 InitReg(MISCREG_TLBI_RVALE2IS)
5661 .hypWrite().monWrite();
5662 InitReg(MISCREG_TLBI_RVAE3IS)
5663 .monWrite();
5664 InitReg(MISCREG_TLBI_RVALE3IS)
5665 .monWrite();
5666 InitReg(MISCREG_TLBI_RVAE1OS)
5667 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvae1os>)
5668 .writes(1).exceptUserMode();
5669 InitReg(MISCREG_TLBI_RVAAE1OS)
5670 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvaae1os>)
5671 .writes(1).exceptUserMode();
5672 InitReg(MISCREG_TLBI_RVALE1OS)
5673 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvale1os>)
5674 .writes(1).exceptUserMode();
5675 InitReg(MISCREG_TLBI_RVAALE1OS)
5676 .faultWrite(EL1, faultTlbiOsEL1<&HFGITR::tlbirvaale1os>)
5677 .writes(1).exceptUserMode();
5678 InitReg(MISCREG_TLBI_RIPAS2E1OS)
5679 .hypWrite().monWrite();
5680 InitReg(MISCREG_TLBI_RIPAS2LE1OS)
5681 .hypWrite().monWrite();
5682 InitReg(MISCREG_TLBI_RVAE2OS)
5683 .hypWrite().monWrite();
5684 InitReg(MISCREG_TLBI_RVALE2OS)
5685 .hypWrite().monWrite();
5686 InitReg(MISCREG_TLBI_RVAE3OS)
5687 .monWrite();
5688 InitReg(MISCREG_TLBI_RVALE3OS)
5689 .monWrite();
5690 InitReg(MISCREG_TLBI_VMALLE1OSNXS)
5691 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbivmalle1os>)
5692 .writes(1).exceptUserMode();
5693 InitReg(MISCREG_TLBI_VAE1OSNXS)
5694 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbivae1os>)
5695 .writes(1).exceptUserMode();
5696 InitReg(MISCREG_TLBI_ASIDE1OSNXS)
5697 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbiaside1os>)
5698 .writes(1).exceptUserMode();
5699 InitReg(MISCREG_TLBI_VAAE1OSNXS)
5700 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbivaae1os>)
5701 .writes(1).exceptUserMode();
5702 InitReg(MISCREG_TLBI_VALE1OSNXS)
5703 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbivale1os>)
5704 .writes(1).exceptUserMode();
5705 InitReg(MISCREG_TLBI_VAALE1OSNXS)
5706 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbivaale1os>)
5707 .writes(1).exceptUserMode();
5708 InitReg(MISCREG_TLBI_VMALLE1ISNXS)
5709 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbivmalle1is>)
5710 .writes(1).exceptUserMode();
5711 InitReg(MISCREG_TLBI_VAE1ISNXS)
5712 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbivae1is>)
5713 .writes(1).exceptUserMode();
5714 InitReg(MISCREG_TLBI_ASIDE1ISNXS)
5715 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbiaside1is>)
5716 .writes(1).exceptUserMode();
5717 InitReg(MISCREG_TLBI_VAAE1ISNXS)
5718 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbivaae1is>)
5719 .writes(1).exceptUserMode();
5720 InitReg(MISCREG_TLBI_VALE1ISNXS)
5721 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbivale1is>)
5722 .writes(1).exceptUserMode();
5723 InitReg(MISCREG_TLBI_VAALE1ISNXS)
5724 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbivaale1is>)
5725 .writes(1).exceptUserMode();
5726 InitReg(MISCREG_TLBI_VMALLE1NXS)
5727 .faultWrite(EL1, faultTlbiNxsEL1<&HCR::ttlb, &HFGITR::tlbivmalle1>)
5728 .writes(1).exceptUserMode();
5729 InitReg(MISCREG_TLBI_VAE1NXS)
5730 .faultWrite(EL1, faultTlbiNxsEL1<&HCR::ttlb, &HFGITR::tlbivae1>)
5731 .writes(1).exceptUserMode();
5732 InitReg(MISCREG_TLBI_ASIDE1NXS)
5733 .faultWrite(EL1, faultTlbiNxsEL1<&HCR::ttlb, &HFGITR::tlbiaside1>)
5734 .writes(1).exceptUserMode();
5735 InitReg(MISCREG_TLBI_VAAE1NXS)
5736 .faultWrite(EL1, faultTlbiNxsEL1<&HCR::ttlb, &HFGITR::tlbivaae1>)
5737 .writes(1).exceptUserMode();
5738 InitReg(MISCREG_TLBI_VALE1NXS)
5739 .faultWrite(EL1, faultTlbiNxsEL1<&HCR::ttlb, &HFGITR::tlbivale1>)
5740 .writes(1).exceptUserMode();
5741 InitReg(MISCREG_TLBI_VAALE1NXS)
5742 .faultWrite(EL1, faultTlbiNxsEL1<&HCR::ttlb, &HFGITR::tlbivaale1>)
5743 .writes(1).exceptUserMode();
5744 InitReg(MISCREG_TLBI_IPAS2E1OSNXS)
5745 .hypWrite().monWrite();
5746 InitReg(MISCREG_TLBI_IPAS2LE1OSNXS)
5747 .hypWrite().monWrite();
5748 InitReg(MISCREG_TLBI_ALLE2OSNXS)
5749 .hypWrite().monWrite();
5750 InitReg(MISCREG_TLBI_VAE2OSNXS)
5751 .hypWrite().monWrite();
5752 InitReg(MISCREG_TLBI_ALLE1OSNXS)
5753 .hypWrite().monWrite();
5754 InitReg(MISCREG_TLBI_VALE2OSNXS)
5755 .hypWrite().monWrite();
5756 InitReg(MISCREG_TLBI_VMALLS12E1OSNXS)
5757 .hypWrite().monWrite();
5758 InitReg(MISCREG_TLBI_IPAS2E1ISNXS)
5759 .hypWrite().monWrite();
5760 InitReg(MISCREG_TLBI_IPAS2LE1ISNXS)
5761 .hypWrite().monWrite();
5762 InitReg(MISCREG_TLBI_ALLE2ISNXS)
5763 .hypWrite().monWrite();
5764 InitReg(MISCREG_TLBI_VAE2ISNXS)
5765 .hypWrite().monWrite();
5766 InitReg(MISCREG_TLBI_ALLE1ISNXS)
5767 .hypWrite().monWrite();
5768 InitReg(MISCREG_TLBI_VALE2ISNXS)
5769 .hypWrite().monWrite();
5770 InitReg(MISCREG_TLBI_VMALLS12E1ISNXS)
5771 .hypWrite().monWrite();
5772 InitReg(MISCREG_TLBI_IPAS2E1NXS)
5773 .hypWrite().monWrite();
5774 InitReg(MISCREG_TLBI_IPAS2LE1NXS)
5775 .hypWrite().monWrite();
5776 InitReg(MISCREG_TLBI_ALLE2NXS)
5777 .hypWrite().monWrite();
5778 InitReg(MISCREG_TLBI_VAE2NXS)
5779 .hypWrite().monWrite();
5780 InitReg(MISCREG_TLBI_ALLE1NXS)
5781 .hypWrite().monWrite();
5782 InitReg(MISCREG_TLBI_VALE2NXS)
5783 .hypWrite().monWrite();
5784 InitReg(MISCREG_TLBI_VMALLS12E1NXS)
5785 .hypWrite().monWrite();
5786 InitReg(MISCREG_TLBI_ALLE3OSNXS)
5787 .monWrite();
5788 InitReg(MISCREG_TLBI_VAE3OSNXS)
5789 .monWrite();
5790 InitReg(MISCREG_TLBI_VALE3OSNXS)
5791 .monWrite();
5792 InitReg(MISCREG_TLBI_ALLE3ISNXS)
5793 .monWrite();
5794 InitReg(MISCREG_TLBI_VAE3ISNXS)
5795 .monWrite();
5796 InitReg(MISCREG_TLBI_VALE3ISNXS)
5797 .monWrite();
5798 InitReg(MISCREG_TLBI_ALLE3NXS)
5799 .monWrite();
5800 InitReg(MISCREG_TLBI_VAE3NXS)
5801 .monWrite();
5802 InitReg(MISCREG_TLBI_VALE3NXS)
5803 .monWrite();
5804
5805 InitReg(MISCREG_TLBI_RVAE1NXS)
5806 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvae1>)
5807 .writes(1).exceptUserMode();
5808 InitReg(MISCREG_TLBI_RVAAE1NXS)
5809 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaae1>)
5810 .writes(1).exceptUserMode();
5811 InitReg(MISCREG_TLBI_RVALE1NXS)
5812 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvale1>)
5813 .writes(1).exceptUserMode();
5814 InitReg(MISCREG_TLBI_RVAALE1NXS)
5815 .faultWrite(EL1, faultHcrFgtInstEL1<&HCR::ttlb, &HFGITR::tlbirvaale1>)
5816 .writes(1).exceptUserMode();
5817 InitReg(MISCREG_TLBI_RIPAS2E1NXS)
5818 .hypWrite().monWrite();
5819 InitReg(MISCREG_TLBI_RIPAS2LE1NXS)
5820 .hypWrite().monWrite();
5821 InitReg(MISCREG_TLBI_RVAE2NXS)
5822 .hypWrite().monWrite();
5823 InitReg(MISCREG_TLBI_RVALE2NXS)
5824 .hypWrite().monWrite();
5825 InitReg(MISCREG_TLBI_RVAE3NXS)
5826 .monWrite();
5827 InitReg(MISCREG_TLBI_RVALE3NXS)
5828 .monWrite();
5829 InitReg(MISCREG_TLBI_RVAE1ISNXS)
5830 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbirvae1is>)
5831 .writes(1).exceptUserMode();
5832 InitReg(MISCREG_TLBI_RVAAE1ISNXS)
5833 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbirvaae1is>)
5834 .writes(1).exceptUserMode();
5835 InitReg(MISCREG_TLBI_RVALE1ISNXS)
5836 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbirvale1is>)
5837 .writes(1).exceptUserMode();
5838 InitReg(MISCREG_TLBI_RVAALE1ISNXS)
5839 .faultWrite(EL1, faultTlbiIsNxsEL1<&HFGITR::tlbirvaale1is>)
5840 .writes(1).exceptUserMode();
5841 InitReg(MISCREG_TLBI_RIPAS2E1ISNXS)
5842 .hypWrite().monWrite();
5843 InitReg(MISCREG_TLBI_RIPAS2LE1ISNXS)
5844 .hypWrite().monWrite();
5845 InitReg(MISCREG_TLBI_RVAE2ISNXS)
5846 .hypWrite().monWrite();
5847 InitReg(MISCREG_TLBI_RVALE2ISNXS)
5848 .hypWrite().monWrite();
5849 InitReg(MISCREG_TLBI_RVAE3ISNXS)
5850 .monWrite();
5851 InitReg(MISCREG_TLBI_RVALE3ISNXS)
5852 .monWrite();
5853 InitReg(MISCREG_TLBI_RVAE1OSNXS)
5854 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbirvae1os>)
5855 .writes(1).exceptUserMode();
5856 InitReg(MISCREG_TLBI_RVAAE1OSNXS)
5857 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbirvaae1os>)
5858 .writes(1).exceptUserMode();
5859 InitReg(MISCREG_TLBI_RVALE1OSNXS)
5860 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbirvale1os>)
5861 .writes(1).exceptUserMode();
5862 InitReg(MISCREG_TLBI_RVAALE1OSNXS)
5863 .faultWrite(EL1, faultTlbiOsNxsEL1<&HFGITR::tlbirvaale1os>)
5864 .writes(1).exceptUserMode();
5865 InitReg(MISCREG_TLBI_RIPAS2E1OSNXS)
5866 .hypWrite().monWrite();
5867 InitReg(MISCREG_TLBI_RIPAS2LE1OSNXS)
5868 .hypWrite().monWrite();
5869 InitReg(MISCREG_TLBI_RVAE2OSNXS)
5870 .hypWrite().monWrite();
5871 InitReg(MISCREG_TLBI_RVALE2OSNXS)
5872 .hypWrite().monWrite();
5873 InitReg(MISCREG_TLBI_RVAE3OSNXS)
5874 .monWrite();
5875 InitReg(MISCREG_TLBI_RVALE3OSNXS)
5876 .monWrite();
5877 InitReg(MISCREG_PMINTENSET_EL1)
5878 .allPrivileges().exceptUserMode()
5879 .mapsTo(MISCREG_PMINTENSET);
5880 InitReg(MISCREG_PMINTENCLR_EL1)
5881 .allPrivileges().exceptUserMode()
5882 .mapsTo(MISCREG_PMINTENCLR);
5883 InitReg(MISCREG_PMCR_EL0)
5884 .allPrivileges()
5885 .mapsTo(MISCREG_PMCR);
5886 InitReg(MISCREG_PMCNTENSET_EL0)
5887 .allPrivileges()
5888 .mapsTo(MISCREG_PMCNTENSET);
5889 InitReg(MISCREG_PMCNTENCLR_EL0)
5890 .allPrivileges()
5891 .mapsTo(MISCREG_PMCNTENCLR);
5892 InitReg(MISCREG_PMOVSCLR_EL0)
5893 .allPrivileges();
5894// .mapsTo(MISCREG_PMOVSCLR);
5895 InitReg(MISCREG_PMSWINC_EL0)
5896 .writes(1).user()
5897 .mapsTo(MISCREG_PMSWINC);
5898 InitReg(MISCREG_PMSELR_EL0)
5899 .allPrivileges()
5900 .mapsTo(MISCREG_PMSELR);
5901 InitReg(MISCREG_PMCEID0_EL0)
5902 .reads(1).user()
5903 .mapsTo(MISCREG_PMCEID0);
5904 InitReg(MISCREG_PMCEID1_EL0)
5905 .reads(1).user()
5906 .mapsTo(MISCREG_PMCEID1);
5907 InitReg(MISCREG_PMCCNTR_EL0)
5908 .allPrivileges()
5909 .mapsTo(MISCREG_PMCCNTR);
5910 InitReg(MISCREG_PMXEVTYPER_EL0)
5911 .allPrivileges()
5912 .mapsTo(MISCREG_PMXEVTYPER);
5913 InitReg(MISCREG_PMCCFILTR_EL0)
5914 .allPrivileges();
5915 InitReg(MISCREG_PMXEVCNTR_EL0)
5916 .allPrivileges()
5917 .mapsTo(MISCREG_PMXEVCNTR);
5918 InitReg(MISCREG_PMUSERENR_EL0)
5919 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
5920 .mapsTo(MISCREG_PMUSERENR);
5921 InitReg(MISCREG_PMOVSSET_EL0)
5922 .allPrivileges()
5923 .mapsTo(MISCREG_PMOVSSET);
5924 InitReg(MISCREG_MAIR_EL1)
5925 .allPrivileges().exceptUserMode()
5926 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::mairEL1>)
5927 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::mairEL1>)
5928 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5929 InitReg(MISCREG_MAIR_EL12)
5930 .fault(EL2, defaultFaultE2H_EL2)
5931 .fault(EL3, defaultFaultE2H_EL3)
5932 .mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
5933 InitReg(MISCREG_AMAIR_EL1)
5934 .allPrivileges().exceptUserMode()
5935 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::amairEL1>)
5936 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::amairEL1>)
5937 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5938 InitReg(MISCREG_AMAIR_EL12)
5939 .fault(EL2, defaultFaultE2H_EL2)
5940 .fault(EL3, defaultFaultE2H_EL3)
5941 .mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
5942 InitReg(MISCREG_MAIR_EL2)
5943 .hyp().mon()
5944 .mapsTo(MISCREG_HMAIR0, MISCREG_HMAIR1);
5945 InitReg(MISCREG_AMAIR_EL2)
5946 .hyp().mon()
5947 .mapsTo(MISCREG_HAMAIR0, MISCREG_HAMAIR1);
5948 InitReg(MISCREG_MAIR_EL3)
5949 .mon();
5950 InitReg(MISCREG_AMAIR_EL3)
5951 .mon();
5952 InitReg(MISCREG_L2CTLR_EL1)
5953 .allPrivileges().exceptUserMode();
5954 InitReg(MISCREG_L2ECTLR_EL1)
5955 .allPrivileges().exceptUserMode();
5956 InitReg(MISCREG_VBAR_EL1)
5957 .allPrivileges().exceptUserMode()
5958 .faultRead(EL1, faultFgtEL1<true, &HFGTR::vbarEL1>)
5959 .faultWrite(EL1, faultFgtEL1<false, &HFGTR::vbarEL1>)
5960 .mapsTo(MISCREG_VBAR_NS);
5961 InitReg(MISCREG_VBAR_EL12)
5962 .fault(EL2, defaultFaultE2H_EL2)
5963 .fault(EL3, defaultFaultE2H_EL3)
5964 .mapsTo(MISCREG_VBAR_NS);
5965 InitReg(MISCREG_RVBAR_EL1)
5966 .reset(FullSystem && system->highestEL() == EL1 ?
5967 system->resetAddr() : 0)
5968 .privRead(FullSystem && system->highestEL() == EL1);
5969 InitReg(MISCREG_ISR_EL1)
5970 .allPrivileges().exceptUserMode().writes(0);
5971 InitReg(MISCREG_VBAR_EL2)
5972 .hyp().mon()
5973 .res0(0x7ff)
5974 .mapsTo(MISCREG_HVBAR);
5975 InitReg(MISCREG_RVBAR_EL2)
5976 .reset(FullSystem && system->highestEL() == EL2 ?
5977 system->resetAddr() : 0)
5978 .hypRead(FullSystem && system->highestEL() == EL2);
5979 InitReg(MISCREG_VBAR_EL3)
5980 .mon();
5981 InitReg(MISCREG_RVBAR_EL3)
5982 .reset(FullSystem && system->highestEL() == EL3 ?
5983 system->resetAddr() : 0)
5984 .mon().writes(0);
5985 InitReg(MISCREG_RMR_EL3)
5986 .mon();
5987 InitReg(MISCREG_CONTEXTIDR_EL1)
5988 .allPrivileges().exceptUserMode()
5989 .faultRead(EL1, faultHcrFgtEL1<true, &HCR::trvm, &HFGTR::contextidrEL1>)
5990 .faultWrite(EL1, faultHcrFgtEL1<false, &HCR::tvm, &HFGTR::contextidrEL1>)
5991 .mapsTo(MISCREG_CONTEXTIDR_NS);
5992 InitReg(MISCREG_CONTEXTIDR_EL12)
5993 .fault(EL2, defaultFaultE2H_EL2)
5994 .fault(EL3, defaultFaultE2H_EL3)
5995 .mapsTo(MISCREG_CONTEXTIDR_NS);
5996 InitReg(MISCREG_TPIDR_EL1)
5997 .allPrivileges().exceptUserMode()
5998 .faultRead(EL1, faultFgtEL1<true, &HFGTR::tpidrEL1>)
5999 .faultWrite(EL1, faultFgtEL1<false, &HFGTR::tpidrEL1>)
6000 .mapsTo(MISCREG_TPIDRPRW_NS);
6001 InitReg(MISCREG_TPIDR_EL0)
6002 .allPrivileges()
6003 .faultRead(EL0, faultFgtEL0<true, &HFGTR::tpidrEL0>)
6004 .faultWrite(EL0, faultFgtEL0<false, &HFGTR::tpidrEL0>)
6005 .faultRead(EL1, faultFgtEL1<true, &HFGTR::tpidrEL0>)
6006 .faultWrite(EL1, faultFgtEL1<false, &HFGTR::tpidrEL0>)
6007 .mapsTo(MISCREG_TPIDRURW_NS);
6008 InitReg(MISCREG_TPIDRRO_EL0)
6009 .allPrivileges().userNonSecureWrite(0).userSecureWrite(0)
6010 .faultRead(EL0, faultFgtEL0<true, &HFGTR::tpidrroEL0>)
6011 .faultRead(EL1, faultFgtEL1<true, &HFGTR::tpidrroEL0>)
6012 .faultWrite(EL1, faultFgtEL1<false, &HFGTR::tpidrroEL0>)
6013 .mapsTo(MISCREG_TPIDRURO_NS);
6014 InitReg(MISCREG_TPIDR_EL2)
6015 .hyp().mon()
6016 .mapsTo(MISCREG_HTPIDR);
6017 InitReg(MISCREG_TPIDR_EL3)
6018 .mon();
6019 // BEGIN Generic Timer (AArch64)
6020 InitReg(MISCREG_CNTFRQ_EL0)
6021 .reads(1)
6022 .faultRead(EL0, faultGenericTimerEL0)
6023 .highest(system)
6024 .privSecureWrite(aarch32EL3)
6025 .mapsTo(MISCREG_CNTFRQ);
6026 InitReg(MISCREG_CNTPCT_EL0)
6027 .unverifiable()
6028 .faultRead(EL0, faultCntpctEL0)
6029 .faultRead(EL1, faultCntpctEL1)
6030 .reads(1)
6031 .mapsTo(MISCREG_CNTPCT);
6032 InitReg(MISCREG_CNTVCT_EL0)
6033 .unverifiable()
6034 .faultRead(EL0, faultCntvctEL0)
6035 .faultRead(EL1, faultCntvctEL1)
6036 .reads(1)
6037 .mapsTo(MISCREG_CNTVCT);
6038 InitReg(MISCREG_CNTP_CTL_EL0)
6039 .allPrivileges()
6040 .fault(EL0, faultCntpCtlEL0)
6041 .fault(EL1, faultCntpCtlEL1)
6042 .res0(0xfffffffffffffff8)
6043 .mapsTo(MISCREG_CNTP_CTL_NS);
6044 InitReg(MISCREG_CNTP_CVAL_EL0)
6045 .allPrivileges()
6046 .fault(EL0, faultCntpCtlEL0)
6047 .fault(EL1, faultCntpCtlEL1)
6048 .mapsTo(MISCREG_CNTP_CVAL_NS);
6049 InitReg(MISCREG_CNTP_TVAL_EL0)
6050 .allPrivileges()
6051 .fault(EL0, faultCntpCtlEL0)
6052 .fault(EL1, faultCntpCtlEL1)
6053 .res0(0xffffffff00000000)
6054 .mapsTo(MISCREG_CNTP_TVAL_NS);
6055 InitReg(MISCREG_CNTV_CTL_EL0)
6056 .allPrivileges()
6057 .fault(EL0, faultCntvCtlEL0)
6058 .fault(EL1, faultCntvCtlEL1)
6059 .res0(0xfffffffffffffff8)
6060 .mapsTo(MISCREG_CNTV_CTL);
6061 InitReg(MISCREG_CNTV_CVAL_EL0)
6062 .allPrivileges()
6063 .fault(EL0, faultCntvCtlEL0)
6064 .fault(EL1, faultCntvCtlEL1)
6065 .mapsTo(MISCREG_CNTV_CVAL);
6066 InitReg(MISCREG_CNTV_TVAL_EL0)
6067 .allPrivileges()
6068 .fault(EL0, faultCntvCtlEL0)
6069 .fault(EL1, faultCntvCtlEL1)
6070 .res0(0xffffffff00000000)
6071 .mapsTo(MISCREG_CNTV_TVAL);
6072 InitReg(MISCREG_CNTP_CTL_EL02)
6073 .fault(EL2, defaultFaultE2H_EL2)
6074 .fault(EL3, defaultFaultE2H_EL3)
6075 .res0(0xfffffffffffffff8)
6076 .mapsTo(MISCREG_CNTP_CTL_NS);
6077 InitReg(MISCREG_CNTP_CVAL_EL02)
6078 .fault(EL2, defaultFaultE2H_EL2)
6079 .fault(EL3, defaultFaultE2H_EL3)
6080 .mapsTo(MISCREG_CNTP_CVAL_NS);
6081 InitReg(MISCREG_CNTP_TVAL_EL02)
6082 .fault(EL2, defaultFaultE2H_EL2)
6083 .fault(EL3, defaultFaultE2H_EL3)
6084 .res0(0xffffffff00000000)
6085 .mapsTo(MISCREG_CNTP_TVAL_NS);
6086 InitReg(MISCREG_CNTV_CTL_EL02)
6087 .fault(EL2, defaultFaultE2H_EL2)
6088 .fault(EL3, defaultFaultE2H_EL3)
6089 .res0(0xfffffffffffffff8)
6090 .mapsTo(MISCREG_CNTV_CTL);
6091 InitReg(MISCREG_CNTV_CVAL_EL02)
6092 .fault(EL2, defaultFaultE2H_EL2)
6093 .fault(EL3, defaultFaultE2H_EL3)
6094 .mapsTo(MISCREG_CNTV_CVAL);
6095 InitReg(MISCREG_CNTV_TVAL_EL02)
6096 .fault(EL2, defaultFaultE2H_EL2)
6097 .fault(EL3, defaultFaultE2H_EL3)
6098 .res0(0xffffffff00000000)
6099 .mapsTo(MISCREG_CNTV_TVAL);
6100 InitReg(MISCREG_CNTKCTL_EL1)
6101 .allPrivileges()
6102 .exceptUserMode()
6103 .res0(0xfffffffffffdfc00)
6104 .mapsTo(MISCREG_CNTKCTL);
6105 InitReg(MISCREG_CNTKCTL_EL12)
6106 .fault(EL2, defaultFaultE2H_EL2)
6107 .fault(EL3, defaultFaultE2H_EL3)
6108 .res0(0xfffffffffffdfc00)
6109 .mapsTo(MISCREG_CNTKCTL);
6110 InitReg(MISCREG_CNTPS_CTL_EL1)
6111 .mon()
6112 .privSecure()
6113 .fault(EL1, faultCntpsCtlEL1)
6114 .res0(0xfffffffffffffff8);
6115 InitReg(MISCREG_CNTPS_CVAL_EL1)
6116 .mon()
6117 .privSecure()
6118 .fault(EL1, faultCntpsCtlEL1);
6119 InitReg(MISCREG_CNTPS_TVAL_EL1)
6120 .mon()
6121 .privSecure()
6122 .fault(EL1, faultCntpsCtlEL1)
6123 .res0(0xffffffff00000000);
6124 InitReg(MISCREG_CNTHCTL_EL2)
6125 .mon()
6126 .hyp()
6127 .res0(0xfffffffffffc0000)
6128 .mapsTo(MISCREG_CNTHCTL);
6129 InitReg(MISCREG_CNTHP_CTL_EL2)
6130 .mon()
6131 .hyp()
6132 .res0(0xfffffffffffffff8)
6133 .mapsTo(MISCREG_CNTHP_CTL);
6134 InitReg(MISCREG_CNTHP_CVAL_EL2)
6135 .mon()
6136 .hyp()
6137 .mapsTo(MISCREG_CNTHP_CVAL);
6138 InitReg(MISCREG_CNTHP_TVAL_EL2)
6139 .mon()
6140 .hyp()
6141 .res0(0xffffffff00000000)
6142 .mapsTo(MISCREG_CNTHP_TVAL);
6143 InitReg(MISCREG_CNTHPS_CTL_EL2)
6144 .mon(sel2_implemented)
6145 .hypSecure(sel2_implemented)
6146 .res0(0xfffffffffffffff8);
6147 InitReg(MISCREG_CNTHPS_CVAL_EL2)
6148 .mon(sel2_implemented)
6149 .hypSecure(sel2_implemented);
6150 InitReg(MISCREG_CNTHPS_TVAL_EL2)
6151 .mon(sel2_implemented)
6152 .hypSecure(sel2_implemented)
6153 .res0(0xffffffff00000000);
6154 InitReg(MISCREG_CNTHV_CTL_EL2)
6155 .mon(vhe_implemented)
6156 .hyp()
6157 .res0(0xfffffffffffffff8);
6158 InitReg(MISCREG_CNTHV_CVAL_EL2)
6159 .mon(vhe_implemented)
6160 .hyp(vhe_implemented);
6161 InitReg(MISCREG_CNTHV_TVAL_EL2)
6162 .mon(vhe_implemented)
6163 .hyp(vhe_implemented)
6164 .res0(0xffffffff00000000);
6165 InitReg(MISCREG_CNTHVS_CTL_EL2)
6166 .mon(vhe_implemented && sel2_implemented)
6167 .hypSecure(vhe_implemented && sel2_implemented)
6168 .res0(0xfffffffffffffff8);
6169 InitReg(MISCREG_CNTHVS_CVAL_EL2)
6170 .mon(vhe_implemented && sel2_implemented)
6171 .hypSecure(vhe_implemented && sel2_implemented);
6172 InitReg(MISCREG_CNTHVS_TVAL_EL2)
6173 .mon(vhe_implemented && sel2_implemented)
6174 .hypSecure(vhe_implemented && sel2_implemented)
6175 .res0(0xffffffff00000000);
6176 // ENDIF Armv8.1-VHE
6177 InitReg(MISCREG_CNTVOFF_EL2)
6178 .mon()
6179 .hyp()
6180 .mapsTo(MISCREG_CNTVOFF);
6181 // END Generic Timer (AArch64)
6182 InitReg(MISCREG_PMEVCNTR0_EL0)
6183 .allPrivileges()
6184 .mapsTo(MISCREG_PMEVCNTR0);
6185 InitReg(MISCREG_PMEVCNTR1_EL0)
6186 .allPrivileges()
6187 .mapsTo(MISCREG_PMEVCNTR1);
6188 InitReg(MISCREG_PMEVCNTR2_EL0)
6189 .allPrivileges()
6190 .mapsTo(MISCREG_PMEVCNTR2);
6191 InitReg(MISCREG_PMEVCNTR3_EL0)
6192 .allPrivileges()
6193 .mapsTo(MISCREG_PMEVCNTR3);
6194 InitReg(MISCREG_PMEVCNTR4_EL0)
6195 .allPrivileges()
6196 .mapsTo(MISCREG_PMEVCNTR4);
6197 InitReg(MISCREG_PMEVCNTR5_EL0)
6198 .allPrivileges()
6199 .mapsTo(MISCREG_PMEVCNTR5);
6200 InitReg(MISCREG_PMEVTYPER0_EL0)
6201 .allPrivileges()
6202 .mapsTo(MISCREG_PMEVTYPER0);
6203 InitReg(MISCREG_PMEVTYPER1_EL0)
6204 .allPrivileges()
6205 .mapsTo(MISCREG_PMEVTYPER1);
6206 InitReg(MISCREG_PMEVTYPER2_EL0)
6207 .allPrivileges()
6208 .mapsTo(MISCREG_PMEVTYPER2);
6209 InitReg(MISCREG_PMEVTYPER3_EL0)
6210 .allPrivileges()
6211 .mapsTo(MISCREG_PMEVTYPER3);
6212 InitReg(MISCREG_PMEVTYPER4_EL0)
6213 .allPrivileges()
6214 .mapsTo(MISCREG_PMEVTYPER4);
6215 InitReg(MISCREG_PMEVTYPER5_EL0)
6216 .allPrivileges()
6217 .mapsTo(MISCREG_PMEVTYPER5);
6218 InitReg(MISCREG_IL1DATA0_EL1)
6219 .allPrivileges().exceptUserMode();
6220 InitReg(MISCREG_IL1DATA1_EL1)
6221 .allPrivileges().exceptUserMode();
6222 InitReg(MISCREG_IL1DATA2_EL1)
6223 .allPrivileges().exceptUserMode();
6224 InitReg(MISCREG_IL1DATA3_EL1)
6225 .allPrivileges().exceptUserMode();
6226 InitReg(MISCREG_DL1DATA0_EL1)
6227 .allPrivileges().exceptUserMode();
6228 InitReg(MISCREG_DL1DATA1_EL1)
6229 .allPrivileges().exceptUserMode();
6230 InitReg(MISCREG_DL1DATA2_EL1)
6231 .allPrivileges().exceptUserMode();
6232 InitReg(MISCREG_DL1DATA3_EL1)
6233 .allPrivileges().exceptUserMode();
6234 InitReg(MISCREG_DL1DATA4_EL1)
6235 .allPrivileges().exceptUserMode();
6236 InitReg(MISCREG_L2ACTLR_EL1)
6237 .allPrivileges().exceptUserMode();
6238 InitReg(MISCREG_CPUACTLR_EL1)
6239 .allPrivileges().exceptUserMode();
6240 InitReg(MISCREG_CPUECTLR_EL1)
6241 .allPrivileges().exceptUserMode();
6242 InitReg(MISCREG_CPUMERRSR_EL1)
6243 .allPrivileges().exceptUserMode();
6244 InitReg(MISCREG_L2MERRSR_EL1)
6245 .warnNotFail()
6246 .fault(faultUnimplemented);
6247 InitReg(MISCREG_CBAR_EL1)
6248 .allPrivileges().exceptUserMode().writes(0);
6249 InitReg(MISCREG_CONTEXTIDR_EL2)
6250 .mon().hyp();
6251
6252 // GICv3 AArch64
6253 InitReg(MISCREG_ICC_PMR_EL1)
6254 .res0(0xffffff00) // [31:8]
6255 .allPrivileges().exceptUserMode()
6256 .mapsTo(MISCREG_ICC_PMR);
6257 InitReg(MISCREG_ICC_IAR0_EL1)
6258 .allPrivileges().exceptUserMode().writes(0)
6259 .mapsTo(MISCREG_ICC_IAR0);
6260 InitReg(MISCREG_ICC_EOIR0_EL1)
6261 .allPrivileges().exceptUserMode().reads(0)
6262 .mapsTo(MISCREG_ICC_EOIR0);
6263 InitReg(MISCREG_ICC_HPPIR0_EL1)
6264 .allPrivileges().exceptUserMode().writes(0)
6265 .mapsTo(MISCREG_ICC_HPPIR0);
6266 InitReg(MISCREG_ICC_BPR0_EL1)
6267 .res0(0xfffffff8) // [31:3]
6268 .allPrivileges().exceptUserMode()
6269 .mapsTo(MISCREG_ICC_BPR0);
6270 InitReg(MISCREG_ICC_AP0R0_EL1)
6271 .allPrivileges().exceptUserMode()
6272 .mapsTo(MISCREG_ICC_AP0R0);
6273 InitReg(MISCREG_ICC_AP0R1_EL1)
6274 .allPrivileges().exceptUserMode()
6275 .mapsTo(MISCREG_ICC_AP0R1);
6276 InitReg(MISCREG_ICC_AP0R2_EL1)
6277 .allPrivileges().exceptUserMode()
6278 .mapsTo(MISCREG_ICC_AP0R2);
6279 InitReg(MISCREG_ICC_AP0R3_EL1)
6280 .allPrivileges().exceptUserMode()
6281 .mapsTo(MISCREG_ICC_AP0R3);
6282 InitReg(MISCREG_ICC_AP1R0_EL1)
6283 .banked64()
6284 .mapsTo(MISCREG_ICC_AP1R0);
6285 InitReg(MISCREG_ICC_AP1R0_EL1_NS)
6286 .bankedChild()
6287 .allPrivileges().exceptUserMode()
6288 .mapsTo(MISCREG_ICC_AP1R0_NS);
6289 InitReg(MISCREG_ICC_AP1R0_EL1_S)
6290 .bankedChild()
6291 .allPrivileges().exceptUserMode()
6292 .mapsTo(MISCREG_ICC_AP1R0_S);
6293 InitReg(MISCREG_ICC_AP1R1_EL1)
6294 .banked64()
6295 .mapsTo(MISCREG_ICC_AP1R1);
6296 InitReg(MISCREG_ICC_AP1R1_EL1_NS)
6297 .bankedChild()
6298 .allPrivileges().exceptUserMode()
6299 .mapsTo(MISCREG_ICC_AP1R1_NS);
6300 InitReg(MISCREG_ICC_AP1R1_EL1_S)
6301 .bankedChild()
6302 .allPrivileges().exceptUserMode()
6303 .mapsTo(MISCREG_ICC_AP1R1_S);
6304 InitReg(MISCREG_ICC_AP1R2_EL1)
6305 .banked64()
6306 .mapsTo(MISCREG_ICC_AP1R2);
6307 InitReg(MISCREG_ICC_AP1R2_EL1_NS)
6308 .bankedChild()
6309 .allPrivileges().exceptUserMode()
6310 .mapsTo(MISCREG_ICC_AP1R2_NS);
6311 InitReg(MISCREG_ICC_AP1R2_EL1_S)
6312 .bankedChild()
6313 .allPrivileges().exceptUserMode()
6314 .mapsTo(MISCREG_ICC_AP1R2_S);
6315 InitReg(MISCREG_ICC_AP1R3_EL1)
6316 .banked64()
6317 .mapsTo(MISCREG_ICC_AP1R3);
6318 InitReg(MISCREG_ICC_AP1R3_EL1_NS)
6319 .bankedChild()
6320 .allPrivileges().exceptUserMode()
6321 .mapsTo(MISCREG_ICC_AP1R3_NS);
6322 InitReg(MISCREG_ICC_AP1R3_EL1_S)
6323 .bankedChild()
6324 .allPrivileges().exceptUserMode()
6325 .mapsTo(MISCREG_ICC_AP1R3_S);
6326 InitReg(MISCREG_ICC_DIR_EL1)
6327 .res0(0xFF000000) // [31:24]
6328 .allPrivileges().exceptUserMode().reads(0)
6329 .mapsTo(MISCREG_ICC_DIR);
6330 InitReg(MISCREG_ICC_RPR_EL1)
6331 .allPrivileges().exceptUserMode().writes(0)
6332 .mapsTo(MISCREG_ICC_RPR);
6333 InitReg(MISCREG_ICC_SGI1R_EL1)
6334 .allPrivileges().exceptUserMode().reads(0)
6335 .faultWrite(EL1, faultIccSgiEL1)
6336 .faultWrite(EL2, faultIccSgiEL2)
6337 .mapsTo(MISCREG_ICC_SGI1R);
6338 InitReg(MISCREG_ICC_ASGI1R_EL1)
6339 .allPrivileges().exceptUserMode().reads(0)
6340 .faultWrite(EL1, faultIccSgiEL1)
6341 .faultWrite(EL2, faultIccSgiEL2)
6342 .mapsTo(MISCREG_ICC_ASGI1R);
6343 InitReg(MISCREG_ICC_SGI0R_EL1)
6344 .allPrivileges().exceptUserMode().reads(0)
6345 .faultWrite(EL1, faultIccSgiEL1)
6346 .faultWrite(EL2, faultIccSgiEL2)
6347 .mapsTo(MISCREG_ICC_SGI0R);
6348 InitReg(MISCREG_ICC_IAR1_EL1)
6349 .allPrivileges().exceptUserMode().writes(0)
6350 .mapsTo(MISCREG_ICC_IAR1);
6351 InitReg(MISCREG_ICC_EOIR1_EL1)
6352 .res0(0xFF000000) // [31:24]
6353 .allPrivileges().exceptUserMode().reads(0)
6354 .mapsTo(MISCREG_ICC_EOIR1);
6355 InitReg(MISCREG_ICC_HPPIR1_EL1)
6356 .allPrivileges().exceptUserMode().writes(0)
6357 .mapsTo(MISCREG_ICC_HPPIR1);
6358 InitReg(MISCREG_ICC_BPR1_EL1)
6359 .banked64()
6360 .mapsTo(MISCREG_ICC_BPR1);
6361 InitReg(MISCREG_ICC_BPR1_EL1_NS)
6362 .bankedChild()
6363 .res0(0xfffffff8) // [31:3]
6364 .allPrivileges().exceptUserMode()
6365 .mapsTo(MISCREG_ICC_BPR1_NS);
6366 InitReg(MISCREG_ICC_BPR1_EL1_S)
6367 .bankedChild()
6368 .res0(0xfffffff8) // [31:3]
6369 .secure().exceptUserMode()
6370 .mapsTo(MISCREG_ICC_BPR1_S);
6371 InitReg(MISCREG_ICC_CTLR_EL1)
6372 .banked64()
6373 .mapsTo(MISCREG_ICC_CTLR);
6374 InitReg(MISCREG_ICC_CTLR_EL1_NS)
6375 .bankedChild()
6376 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
6377 .allPrivileges().exceptUserMode()
6378 .mapsTo(MISCREG_ICC_CTLR_NS);
6379 InitReg(MISCREG_ICC_CTLR_EL1_S)
6380 .bankedChild()
6381 .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2]
6382 .secure().exceptUserMode()
6383 .mapsTo(MISCREG_ICC_CTLR_S);
6384 InitReg(MISCREG_ICC_SRE_EL1)
6385 .banked()
6386 .mapsTo(MISCREG_ICC_SRE);
6387 InitReg(MISCREG_ICC_SRE_EL1_NS)
6388 .bankedChild()
6389 .res0(0xFFFFFFF8) // [31:3]
6390 .allPrivileges().exceptUserMode()
6391 .mapsTo(MISCREG_ICC_SRE_NS);
6392 InitReg(MISCREG_ICC_SRE_EL1_S)
6393 .bankedChild()
6394 .res0(0xFFFFFFF8) // [31:3]
6395 .secure().exceptUserMode()
6396 .mapsTo(MISCREG_ICC_SRE_S);
6397 InitReg(MISCREG_ICC_IGRPEN0_EL1)
6398 .res0(0xFFFFFFFE) // [31:1]
6399 .allPrivileges().exceptUserMode()
6400 .faultRead(EL1, faultFgtEL1<true, &HFGTR::iccIgrpEnEL1>)
6401 .faultWrite(EL1, faultFgtEL1<false, &HFGTR::iccIgrpEnEL1>)
6402 .mapsTo(MISCREG_ICC_IGRPEN0);
6403 InitReg(MISCREG_ICC_IGRPEN1_EL1)
6404 .banked64()
6405 .faultRead(EL1, faultFgtEL1<true, &HFGTR::iccIgrpEnEL1>)
6406 .faultWrite(EL1, faultFgtEL1<false, &HFGTR::iccIgrpEnEL1>)
6407 .mapsTo(MISCREG_ICC_IGRPEN1);
6408 InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
6409 .bankedChild()
6410 .res0(0xFFFFFFFE) // [31:1]
6411 .allPrivileges().exceptUserMode()
6412 .mapsTo(MISCREG_ICC_IGRPEN1_NS);
6413 InitReg(MISCREG_ICC_IGRPEN1_EL1_S)
6414 .bankedChild()
6415 .res0(0xFFFFFFFE) // [31:1]
6416 .secure().exceptUserMode()
6417 .mapsTo(MISCREG_ICC_IGRPEN1_S);
6418 InitReg(MISCREG_ICC_SRE_EL2)
6419 .hyp().mon()
6420 .mapsTo(MISCREG_ICC_HSRE);
6421 InitReg(MISCREG_ICC_CTLR_EL3)
6422 .mon()
6423 .mapsTo(MISCREG_ICC_MCTLR);
6424 InitReg(MISCREG_ICC_SRE_EL3)
6425 .mon()
6426 .mapsTo(MISCREG_ICC_MSRE);
6427 InitReg(MISCREG_ICC_IGRPEN1_EL3)
6428 .mon()
6429 .mapsTo(MISCREG_ICC_MGRPEN1);
6430
6431 InitReg(MISCREG_ICH_AP0R0_EL2)
6432 .hyp().mon()
6433 .mapsTo(MISCREG_ICH_AP0R0);
6434 InitReg(MISCREG_ICH_AP0R1_EL2)
6435 .hyp().mon()
6436 .mapsTo(MISCREG_ICH_AP0R1);
6437 InitReg(MISCREG_ICH_AP0R2_EL2)
6438 .hyp().mon()
6439 .mapsTo(MISCREG_ICH_AP0R2);
6440 InitReg(MISCREG_ICH_AP0R3_EL2)
6441 .hyp().mon()
6442 .mapsTo(MISCREG_ICH_AP0R3);
6443 InitReg(MISCREG_ICH_AP1R0_EL2)
6444 .hyp().mon()
6445 .mapsTo(MISCREG_ICH_AP1R0);
6446 InitReg(MISCREG_ICH_AP1R1_EL2)
6447 .hyp().mon()
6448 .mapsTo(MISCREG_ICH_AP1R1);
6449 InitReg(MISCREG_ICH_AP1R2_EL2)
6450 .hyp().mon()
6451 .mapsTo(MISCREG_ICH_AP1R2);
6452 InitReg(MISCREG_ICH_AP1R3_EL2)
6453 .hyp().mon()
6454 .mapsTo(MISCREG_ICH_AP1R3);
6455 InitReg(MISCREG_ICH_HCR_EL2)
6456 .hyp().mon()
6457 .mapsTo(MISCREG_ICH_HCR);
6458 InitReg(MISCREG_ICH_VTR_EL2)
6459 .hyp().mon().writes(0)
6460 .mapsTo(MISCREG_ICH_VTR);
6461 InitReg(MISCREG_ICH_MISR_EL2)
6462 .hyp().mon().writes(0)
6463 .mapsTo(MISCREG_ICH_MISR);
6464 InitReg(MISCREG_ICH_EISR_EL2)
6465 .hyp().mon().writes(0)
6466 .mapsTo(MISCREG_ICH_EISR);
6467 InitReg(MISCREG_ICH_ELRSR_EL2)
6468 .hyp().mon().writes(0)
6469 .mapsTo(MISCREG_ICH_ELRSR);
6470 InitReg(MISCREG_ICH_VMCR_EL2)
6471 .hyp().mon()
6472 .mapsTo(MISCREG_ICH_VMCR);
6473 InitReg(MISCREG_ICH_LR0_EL2)
6474 .hyp().mon()
6475 .mapsTo(MISCREG_ICH_LR0, MISCREG_ICH_LRC0);
6476 InitReg(MISCREG_ICH_LR1_EL2)
6477 .hyp().mon()
6478 .mapsTo(MISCREG_ICH_LR1, MISCREG_ICH_LRC1);
6479 InitReg(MISCREG_ICH_LR2_EL2)
6480 .hyp().mon()
6481 .mapsTo(MISCREG_ICH_LR2, MISCREG_ICH_LRC2);
6482 InitReg(MISCREG_ICH_LR3_EL2)
6483 .hyp().mon()
6484 .mapsTo(MISCREG_ICH_LR3, MISCREG_ICH_LRC3);
6485 InitReg(MISCREG_ICH_LR4_EL2)
6486 .hyp().mon()
6487 .mapsTo(MISCREG_ICH_LR4, MISCREG_ICH_LRC4);
6488 InitReg(MISCREG_ICH_LR5_EL2)
6489 .hyp().mon()
6490 .mapsTo(MISCREG_ICH_LR5, MISCREG_ICH_LRC5);
6491 InitReg(MISCREG_ICH_LR6_EL2)
6492 .hyp().mon()
6493 .mapsTo(MISCREG_ICH_LR6, MISCREG_ICH_LRC6);
6494 InitReg(MISCREG_ICH_LR7_EL2)
6495 .hyp().mon()
6496 .mapsTo(MISCREG_ICH_LR7, MISCREG_ICH_LRC7);
6497 InitReg(MISCREG_ICH_LR8_EL2)
6498 .hyp().mon()
6499 .mapsTo(MISCREG_ICH_LR8, MISCREG_ICH_LRC8);
6500 InitReg(MISCREG_ICH_LR9_EL2)
6501 .hyp().mon()
6502 .mapsTo(MISCREG_ICH_LR9, MISCREG_ICH_LRC9);
6503 InitReg(MISCREG_ICH_LR10_EL2)
6504 .hyp().mon()
6505 .mapsTo(MISCREG_ICH_LR10, MISCREG_ICH_LRC10);
6506 InitReg(MISCREG_ICH_LR11_EL2)
6507 .hyp().mon()
6508 .mapsTo(MISCREG_ICH_LR11, MISCREG_ICH_LRC11);
6509 InitReg(MISCREG_ICH_LR12_EL2)
6510 .hyp().mon()
6511 .mapsTo(MISCREG_ICH_LR12, MISCREG_ICH_LRC12);
6512 InitReg(MISCREG_ICH_LR13_EL2)
6513 .hyp().mon()
6514 .mapsTo(MISCREG_ICH_LR13, MISCREG_ICH_LRC13);
6515 InitReg(MISCREG_ICH_LR14_EL2)
6516 .hyp().mon()
6517 .mapsTo(MISCREG_ICH_LR14, MISCREG_ICH_LRC14);
6518 InitReg(MISCREG_ICH_LR15_EL2)
6519 .hyp().mon()
6520 .mapsTo(MISCREG_ICH_LR15, MISCREG_ICH_LRC15);
6521
6522 // GICv3 AArch32
6523 InitReg(MISCREG_ICC_AP0R0)
6524 .allPrivileges().exceptUserMode();
6525 InitReg(MISCREG_ICC_AP0R1)
6526 .allPrivileges().exceptUserMode();
6527 InitReg(MISCREG_ICC_AP0R2)
6528 .allPrivileges().exceptUserMode();
6529 InitReg(MISCREG_ICC_AP0R3)
6530 .allPrivileges().exceptUserMode();
6531 InitReg(MISCREG_ICC_AP1R0)
6532 .allPrivileges().exceptUserMode();
6533 InitReg(MISCREG_ICC_AP1R0_NS)
6534 .allPrivileges().exceptUserMode();
6535 InitReg(MISCREG_ICC_AP1R0_S)
6536 .allPrivileges().exceptUserMode();
6537 InitReg(MISCREG_ICC_AP1R1)
6538 .allPrivileges().exceptUserMode();
6539 InitReg(MISCREG_ICC_AP1R1_NS)
6540 .allPrivileges().exceptUserMode();
6541 InitReg(MISCREG_ICC_AP1R1_S)
6542 .allPrivileges().exceptUserMode();
6543 InitReg(MISCREG_ICC_AP1R2)
6544 .allPrivileges().exceptUserMode();
6545 InitReg(MISCREG_ICC_AP1R2_NS)
6546 .allPrivileges().exceptUserMode();
6547 InitReg(MISCREG_ICC_AP1R2_S)
6548 .allPrivileges().exceptUserMode();
6549 InitReg(MISCREG_ICC_AP1R3)
6550 .allPrivileges().exceptUserMode();
6551 InitReg(MISCREG_ICC_AP1R3_NS)
6552 .allPrivileges().exceptUserMode();
6553 InitReg(MISCREG_ICC_AP1R3_S)
6554 .allPrivileges().exceptUserMode();
6555 InitReg(MISCREG_ICC_ASGI1R)
6556 .allPrivileges().exceptUserMode().reads(0);
6557 InitReg(MISCREG_ICC_BPR0)
6558 .allPrivileges().exceptUserMode();
6559 InitReg(MISCREG_ICC_BPR1)
6560 .allPrivileges().exceptUserMode();
6561 InitReg(MISCREG_ICC_BPR1_NS)
6562 .allPrivileges().exceptUserMode();
6563 InitReg(MISCREG_ICC_BPR1_S)
6564 .allPrivileges().exceptUserMode();
6565 InitReg(MISCREG_ICC_CTLR)
6566 .allPrivileges().exceptUserMode();
6567 InitReg(MISCREG_ICC_CTLR_NS)
6568 .allPrivileges().exceptUserMode();
6569 InitReg(MISCREG_ICC_CTLR_S)
6570 .allPrivileges().exceptUserMode();
6571 InitReg(MISCREG_ICC_DIR)
6572 .allPrivileges().exceptUserMode().reads(0);
6573 InitReg(MISCREG_ICC_EOIR0)
6574 .allPrivileges().exceptUserMode().reads(0);
6575 InitReg(MISCREG_ICC_EOIR1)
6576 .allPrivileges().exceptUserMode().reads(0);
6577 InitReg(MISCREG_ICC_HPPIR0)
6578 .allPrivileges().exceptUserMode().writes(0);
6579 InitReg(MISCREG_ICC_HPPIR1)
6580 .allPrivileges().exceptUserMode().writes(0);
6581 InitReg(MISCREG_ICC_HSRE)
6582 .hyp().mon();
6583 InitReg(MISCREG_ICC_IAR0)
6584 .allPrivileges().exceptUserMode().writes(0);
6585 InitReg(MISCREG_ICC_IAR1)
6586 .allPrivileges().exceptUserMode().writes(0);
6587 InitReg(MISCREG_ICC_IGRPEN0)
6588 .allPrivileges().exceptUserMode();
6589 InitReg(MISCREG_ICC_IGRPEN1)
6590 .allPrivileges().exceptUserMode();
6591 InitReg(MISCREG_ICC_IGRPEN1_NS)
6592 .allPrivileges().exceptUserMode();
6593 InitReg(MISCREG_ICC_IGRPEN1_S)
6594 .allPrivileges().exceptUserMode();
6595 InitReg(MISCREG_ICC_MCTLR)
6596 .mon();
6597 InitReg(MISCREG_ICC_MGRPEN1)
6598 .mon();
6599 InitReg(MISCREG_ICC_MSRE)
6600 .mon();
6601 InitReg(MISCREG_ICC_PMR)
6602 .allPrivileges().exceptUserMode();
6603 InitReg(MISCREG_ICC_RPR)
6604 .allPrivileges().exceptUserMode().writes(0);
6605 InitReg(MISCREG_ICC_SGI0R)
6606 .allPrivileges().exceptUserMode().reads(0);
6607 InitReg(MISCREG_ICC_SGI1R)
6608 .allPrivileges().exceptUserMode().reads(0);
6609 InitReg(MISCREG_ICC_SRE)
6610 .allPrivileges().exceptUserMode();
6611 InitReg(MISCREG_ICC_SRE_NS)
6612 .allPrivileges().exceptUserMode();
6613 InitReg(MISCREG_ICC_SRE_S)
6614 .allPrivileges().exceptUserMode();
6615
6616 InitReg(MISCREG_ICH_AP0R0)
6617 .hyp().mon();
6618 InitReg(MISCREG_ICH_AP0R1)
6619 .hyp().mon();
6620 InitReg(MISCREG_ICH_AP0R2)
6621 .hyp().mon();
6622 InitReg(MISCREG_ICH_AP0R3)
6623 .hyp().mon();
6624 InitReg(MISCREG_ICH_AP1R0)
6625 .hyp().mon();
6626 InitReg(MISCREG_ICH_AP1R1)
6627 .hyp().mon();
6628 InitReg(MISCREG_ICH_AP1R2)
6629 .hyp().mon();
6630 InitReg(MISCREG_ICH_AP1R3)
6631 .hyp().mon();
6632 InitReg(MISCREG_ICH_HCR)
6633 .hyp().mon();
6634 InitReg(MISCREG_ICH_VTR)
6635 .hyp().mon().writes(0);
6636 InitReg(MISCREG_ICH_MISR)
6637 .hyp().mon().writes(0);
6638 InitReg(MISCREG_ICH_EISR)
6639 .hyp().mon().writes(0);
6640 InitReg(MISCREG_ICH_ELRSR)
6641 .hyp().mon().writes(0);
6642 InitReg(MISCREG_ICH_VMCR)
6643 .hyp().mon();
6644 InitReg(MISCREG_ICH_LR0)
6645 .hyp().mon();
6646 InitReg(MISCREG_ICH_LR1)
6647 .hyp().mon();
6648 InitReg(MISCREG_ICH_LR2)
6649 .hyp().mon();
6650 InitReg(MISCREG_ICH_LR3)
6651 .hyp().mon();
6652 InitReg(MISCREG_ICH_LR4)
6653 .hyp().mon();
6654 InitReg(MISCREG_ICH_LR5)
6655 .hyp().mon();
6656 InitReg(MISCREG_ICH_LR6)
6657 .hyp().mon();
6658 InitReg(MISCREG_ICH_LR7)
6659 .hyp().mon();
6660 InitReg(MISCREG_ICH_LR8)
6661 .hyp().mon();
6662 InitReg(MISCREG_ICH_LR9)
6663 .hyp().mon();
6664 InitReg(MISCREG_ICH_LR10)
6665 .hyp().mon();
6666 InitReg(MISCREG_ICH_LR11)
6667 .hyp().mon();
6668 InitReg(MISCREG_ICH_LR12)
6669 .hyp().mon();
6670 InitReg(MISCREG_ICH_LR13)
6671 .hyp().mon();
6672 InitReg(MISCREG_ICH_LR14)
6673 .hyp().mon();
6674 InitReg(MISCREG_ICH_LR15)
6675 .hyp().mon();
6676 InitReg(MISCREG_ICH_LRC0)
6677 .hyp().mon();
6678 InitReg(MISCREG_ICH_LRC1)
6679 .hyp().mon();
6680 InitReg(MISCREG_ICH_LRC2)
6681 .hyp().mon();
6682 InitReg(MISCREG_ICH_LRC3)
6683 .hyp().mon();
6684 InitReg(MISCREG_ICH_LRC4)
6685 .hyp().mon();
6686 InitReg(MISCREG_ICH_LRC5)
6687 .hyp().mon();
6688 InitReg(MISCREG_ICH_LRC6)
6689 .hyp().mon();
6690 InitReg(MISCREG_ICH_LRC7)
6691 .hyp().mon();
6692 InitReg(MISCREG_ICH_LRC8)
6693 .hyp().mon();
6694 InitReg(MISCREG_ICH_LRC9)
6695 .hyp().mon();
6696 InitReg(MISCREG_ICH_LRC10)
6697 .hyp().mon();
6698 InitReg(MISCREG_ICH_LRC11)
6699 .hyp().mon();
6700 InitReg(MISCREG_ICH_LRC12)
6701 .hyp().mon();
6702 InitReg(MISCREG_ICH_LRC13)
6703 .hyp().mon();
6704 InitReg(MISCREG_ICH_LRC14)
6705 .hyp().mon();
6706 InitReg(MISCREG_ICH_LRC15)
6707 .hyp().mon();
6708
6709 // SVE
6710 InitReg(MISCREG_ID_AA64ZFR0_EL1)
6711 .reset([this](){
6712 AA64ZFR0 zfr0_el1 = 0;
6713 zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0;
6714 zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0;
6715 zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0;
6716 return zfr0_el1;
6717 }())
6718 .faultRead(EL0, faultIdst)
6719 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
6720 .allPrivileges().exceptUserMode().writes(0);
6721 InitReg(MISCREG_ZCR_EL3)
6722 .reset(sveVL - 1)
6723 .fault(EL3, faultZcrEL3)
6724 .mon();
6725 InitReg(MISCREG_ZCR_EL2)
6726 .reset(sveVL - 1)
6727 .fault(EL2, faultZcrEL2)
6728 .fault(EL3, faultZcrEL3)
6729 .hyp().mon();
6730 InitReg(MISCREG_ZCR_EL12)
6731 .fault(EL2, defaultFaultE2H_EL2)
6732 .fault(EL3, defaultFaultE2H_EL3)
6733 .mapsTo(MISCREG_ZCR_EL1);
6734 InitReg(MISCREG_ZCR_EL1)
6735 .reset(sveVL - 1)
6736 .fault(EL1, faultZcrEL1)
6737 .fault(EL2, faultZcrEL2)
6738 .fault(EL3, faultZcrEL3)
6739 .allPrivileges().exceptUserMode();
6740
6741 // SME
6742 InitReg(MISCREG_ID_AA64SMFR0_EL1)
6743 .reset([](){
6744 AA64SMFR0 smfr0_el1 = 0;
6745 smfr0_el1.f32f32 = 0x1;
6746 // The following BF16F32 is actually not implemented due to a
6747 // lack of BF16 support in gem5's fplib. However, as per the
6748 // SME spec the _only_ allowed value is 0x1.
6749 smfr0_el1.b16f32 = 0x1;
6750 smfr0_el1.f16f32 = 0x1;
6751 smfr0_el1.i8i32 = 0xF;
6752 smfr0_el1.f64f64 = 0x1;
6753 smfr0_el1.i16i64 = 0xF;
6754 smfr0_el1.smEver = 0;
6755 smfr0_el1.fa64 = 0x1;
6756 return smfr0_el1;
6757 }())
6758 .faultRead(EL0, faultIdst)
6759 .faultRead(EL1, faultHcrEL1<&HCR::tid3>)
6760 .allPrivileges().writes(0);
6761 InitReg(MISCREG_SVCR)
6762 .res0([](){
6763 SVCR svcr_mask = 0;
6764 svcr_mask.sm = 1;
6765 svcr_mask.za = 1;
6766 return ~svcr_mask;
6767 }())
6768 .fault(EL0, faultSmenEL0)
6769 .fault(EL1, faultSmenEL1)
6770 .fault(EL2, faultTsmSmen)
6771 .fault(EL3, faultEsm)
6772 .allPrivileges();
6773 InitReg(MISCREG_SMIDR_EL1)
6774 .reset([](){
6775 SMIDR smidr_el1 = 0;
6776 smidr_el1.affinity = 0;
6777 smidr_el1.smps = 0;
6778 smidr_el1.implementer = 0x41;
6779 return smidr_el1;
6780 }())
6781 .faultRead(EL0, faultIdst)
6782 .faultRead(EL1, faultHcrEL1<&HCR::tid1>)
6783 .allPrivileges().writes(0);
6784 InitReg(MISCREG_SMPRI_EL1)
6785 .res0(mask(63, 4))
6786 .fault(EL1, faultEsm)
6787 .fault(EL2, faultEsm)
6788 .fault(EL3, faultEsm)
6789 .allPrivileges().exceptUserMode();
6790 InitReg(MISCREG_SMPRIMAP_EL2)
6791 .fault(EL2, faultEsm)
6792 .fault(EL3, faultEsm)
6793 .hyp().mon();
6794 InitReg(MISCREG_SMCR_EL3)
6795 .reset([this](){
6796 // We want to support FEAT_SME_FA64. Therefore, we enable it in
6797 // all SMCR_ELx registers by default. Runtime software might
6798 // change this later, but given that gem5 doesn't disable
6799 // instructions based on this flag we default to the most
6800 // representative value.
6801 SMCR smcr_el3 = 0;
6802 smcr_el3.fa64 = 1;
6803 smcr_el3.len = smeVL - 1;
6804 return smcr_el3;
6805 }())
6806 .fault(EL3, faultEsm)
6807 .mon();
6808 InitReg(MISCREG_SMCR_EL2)
6809 .reset([this](){
6810 // We want to support FEAT_SME_FA64. Therefore, we enable it in
6811 // all SMCR_ELx registers by default. Runtime software might
6812 // change this later, but given that gem5 doesn't disable
6813 // instructions based on this flag we default to the most
6814 // representative value.
6815 SMCR smcr_el2 = 0;
6816 smcr_el2.fa64 = 1;
6817 smcr_el2.len = smeVL - 1;
6818 return smcr_el2;
6819 }())
6820 .fault(EL2, faultTsmSmen)
6821 .fault(EL3, faultEsm)
6822 .hyp().mon();
6823 InitReg(MISCREG_SMCR_EL12)
6824 .allPrivileges().exceptUserMode();
6825 InitReg(MISCREG_SMCR_EL1)
6826 .reset([this](){
6827 // We want to support FEAT_SME_FA64. Therefore, we enable it in
6828 // all SMCR_ELx registers by default. Runtime software might
6829 // change this later, but given that gem5 doesn't disable
6830 // instructions based on this flag we default to the most
6831 // representative value.
6832 SMCR smcr_el1 = 0;
6833 smcr_el1.fa64 = 1;
6834 smcr_el1.len = smeVL - 1;
6835 return smcr_el1;
6836 }())
6837 .fault(EL1, faultSmenEL1)
6838 .fault(EL2, faultTsmSmen)
6839 .fault(EL3, faultEsm)
6840 .allPrivileges().exceptUserMode();
6841 InitReg(MISCREG_TPIDR2_EL0)
6842 .allPrivileges();
6843
6844 InitReg(MISCREG_RNDR)
6845 .faultRead(EL0, faultRng)
6846 .faultRead(EL1, faultRng)
6847 .faultRead(EL2, faultRng)
6848 .faultRead(EL3, faultRng)
6849 .unverifiable()
6850 .allPrivileges().writes(0);
6851 InitReg(MISCREG_RNDRRS)
6852 .faultRead(EL0, faultRng)
6853 .faultRead(EL1, faultRng)
6854 .faultRead(EL2, faultRng)
6855 .faultRead(EL3, faultRng)
6856 .unverifiable()
6857 .allPrivileges().writes(0);
6858
6859 // FEAT_FGT extension
6860 InitReg(MISCREG_HFGRTR_EL2)
6861 .fault(EL2, faultFgtCtrlRegs)
6862 .hyp().mon(release->has(ArmExtension::FEAT_FGT));
6863 InitReg(MISCREG_HFGWTR_EL2)
6864 .fault(EL2, faultFgtCtrlRegs)
6865 .hyp().mon(release->has(ArmExtension::FEAT_FGT));
6866 InitReg(MISCREG_HFGITR_EL2)
6867 .fault(EL2, faultFgtCtrlRegs)
6868 .hyp().mon(release->has(ArmExtension::FEAT_FGT));
6869 InitReg(MISCREG_HDFGRTR_EL2)
6870 .fault(EL2, faultFgtCtrlRegs)
6871 .hyp().mon(release->has(ArmExtension::FEAT_FGT));
6872 InitReg(MISCREG_HDFGWTR_EL2)
6873 .fault(EL2, faultFgtCtrlRegs)
6874 .hyp().mon(release->has(ArmExtension::FEAT_FGT));
6875 InitReg(MISCREG_HAFGRTR_EL2)
6876 .fault(EL2, faultFgtCtrlRegs)
6877 .hyp().mon(release->has(ArmExtension::FEAT_FGT));
6878
6879 // Dummy registers
6880 InitReg(MISCREG_NOP)
6881 .allPrivileges();
6882 InitReg(MISCREG_RAZ)
6883 .allPrivileges().exceptUserMode().writes(0);
6884 InitReg(MISCREG_UNKNOWN);
6885 InitReg(MISCREG_IMPDEF_UNIMPL)
6886 .fault(EL1, faultImpdefUnimplEL1)
6887 .fault(EL2, faultUnimplemented)
6888 .fault(EL3, faultUnimplemented)
6889 .warnNotFail(impdefAsNop);
6890
6891 // RAS extension (unimplemented)
6892 InitReg(MISCREG_ERRIDR_EL1)
6893 .warnNotFail()
6894 .fault(faultUnimplemented);
6895 InitReg(MISCREG_ERRSELR_EL1)
6896 .warnNotFail()
6897 .fault(faultUnimplemented);
6898 InitReg(MISCREG_ERXFR_EL1)
6899 .warnNotFail()
6900 .fault(faultUnimplemented);
6901 InitReg(MISCREG_ERXCTLR_EL1)
6902 .warnNotFail()
6903 .fault(faultUnimplemented);
6904 InitReg(MISCREG_ERXSTATUS_EL1)
6905 .warnNotFail()
6906 .fault(faultUnimplemented);
6907 InitReg(MISCREG_ERXADDR_EL1)
6908 .warnNotFail()
6909 .fault(faultUnimplemented);
6910 InitReg(MISCREG_ERXMISC0_EL1)
6911 .warnNotFail()
6912 .fault(faultUnimplemented);
6913 InitReg(MISCREG_ERXMISC1_EL1)
6914 .warnNotFail()
6915 .fault(faultUnimplemented);
6916 InitReg(MISCREG_DISR_EL1)
6917 .warnNotFail()
6918 .fault(faultUnimplemented);
6919 InitReg(MISCREG_VSESR_EL2)
6920 .warnNotFail()
6921 .fault(faultUnimplemented);
6922 InitReg(MISCREG_VDISR_EL2)
6923 .warnNotFail()
6924 .fault(faultUnimplemented);
6925
6926 // MPAM extension
6927 InitReg(MISCREG_MPAMIDR_EL1)
6928 .reset(p.mpamidr_el1)
6929 .res0(mask(63, 62) | mask(56, 40) | mask(31, 21) | mask(16, 16))
6930 .faultRead(EL1, faultMpamIdrEL1)
6931 .faultRead(EL2, faultMpamEL2)
6932 .allPrivileges().exceptUserMode().writes(0);
6933 InitReg(MISCREG_MPAM0_EL1)
6934 .res0(mask(63, 48))
6935 .fault(EL1, faultMpam0EL1)
6936 .fault(EL2, faultMpamEL2)
6937 .priv().hyp().mon();
6938 InitReg(MISCREG_MPAM1_EL1)
6939 .res0(mask(62, 61) | mask(59, 48))
6940 .fault(EL1, faultMpam1EL1)
6941 .fault(EL2, faultMpamEL2)
6942 .priv().hyp().mon();
6943 InitReg(MISCREG_MPAM1_EL12)
6944 .res0(mask(59, 48))
6945 .fault(EL2, faultMpam12EL2)
6946 .fault(EL3, defaultFaultE2H_EL3)
6947 .hyp().mon();
6948 InitReg(MISCREG_MPAM2_EL2)
6949 .res0(mask(62, 59) | mask(57, 50))
6950 .fault(EL2, faultMpamEL2)
6951 .hyp().mon();
6952 InitReg(MISCREG_MPAMHCR_EL2)
6953 .res0(mask(63, 32) | mask(30, 9) | mask(7, 2))
6954 .fault(EL2, faultMpamEL2)
6955 .hyp().mon();
6956 InitReg(MISCREG_MPAMVPM0_EL2)
6957 .fault(EL2, faultMpamEL2)
6958 .hyp().mon();
6959 InitReg(MISCREG_MPAMVPM1_EL2)
6960 .fault(EL2, faultMpamEL2)
6961 .hyp().mon();
6962 InitReg(MISCREG_MPAMVPM2_EL2)
6963 .fault(EL2, faultMpamEL2)
6964 .hyp().mon();
6965 InitReg(MISCREG_MPAMVPM3_EL2)
6966 .fault(EL2, faultMpamEL2)
6967 .hyp().mon();
6968 InitReg(MISCREG_MPAMVPM4_EL2)
6969 .fault(EL2, faultMpamEL2)
6970 .hyp().mon();
6971 InitReg(MISCREG_MPAMVPM5_EL2)
6972 .fault(EL2, faultMpamEL2)
6973 .hyp().mon();
6974 InitReg(MISCREG_MPAMVPM6_EL2)
6975 .fault(EL2, faultMpamEL2)
6976 .hyp().mon();
6977 InitReg(MISCREG_MPAMVPM7_EL2)
6978 .fault(EL2, faultMpamEL2)
6979 .hyp().mon();
6980 InitReg(MISCREG_MPAMVPMV_EL2)
6981 .res0(mask(63, 32))
6982 .fault(EL2, faultMpamEL2)
6983 .hyp().mon();
6984 InitReg(MISCREG_MPAM3_EL3)
6985 .res0(mask(59, 48))
6986 .mon();
6987 InitReg(MISCREG_MPAMSM_EL1)
6988 .res0(mask(63, 48) | mask(39, 32) | mask(15, 0))
6989 .fault(EL1, faultMpamsmEL1)
6990 .fault(EL2, faultMpamEL2)
6991 .allPrivileges().exceptUserMode();
6992
6993 // Register mappings for some unimplemented registers:
6994 // ESR_EL1 -> DFSR
6995 // RMR_EL1 -> RMR
6996 // RMR_EL2 -> HRMR
6997 // DBGDTR_EL0 -> DBGDTR{R or T}Xint
6998 // DBGDTRRX_EL0 -> DBGDTRRXint
6999 // DBGDTRTX_EL0 -> DBGDTRRXint
7000 // MDCR_EL3 -> SDCR, NAM D7-2108 (the latter is unimpl. in gem5)
7001
7002 // Populate the idxToMiscRegNum map
7003 assert(idxToMiscRegNum.empty());
7004 for (const auto& [key, val] : miscRegNumToIdx) {
7005 idxToMiscRegNum.insert({val, key});
7006 }
7007
7008 completed = true;
7009}
7010
7011} // namespace ArmISA
7012} // namespace gem5
gem5::ArmISA::ArmStaticInst::undefined
Fault undefined(bool disabled=false) const
Definition static_inst.hh:631
gem5::ArmISA::ISA::system
ArmSystem * system
Definition isa.hh:75
gem5::ArmISA::ISA::InitReg
const MiscRegLUTEntryInitializer InitReg(uint32_t reg)
Definition isa.hh:118
gem5::ArmISA::ISA::initializeMiscRegMetadata
void initializeMiscRegMetadata()
Definition misc.cc:3057
gem5::ArmISA::ISA::release
const ArmRelease * release
This could be either a FS or a SE release.
Definition isa.hh:105
gem5::ArmISA::ISA::highestELIs64
bool highestELIs64
Definition isa.hh:93
gem5::ArmISA::MiscRegLUTEntryInitializer
Metadata table accessible via the value of the register.
Definition misc.hh:1325
gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite
chain userNonSecureWrite(bool v=true) const
Definition misc.hh:1426
gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite
chain userSecureWrite(bool v=true) const
Definition misc.hh:1438
gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail
chain warnNotFail(bool v=true) const
Definition misc.hh:1390
gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo
chain mapsTo(uint32_t l, uint32_t u=0) const
Definition misc.hh:1330
gem5::ArmISA::MiscRegLUTEntryInitializer::fault
chain fault(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1700
gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead
chain userSecureRead(bool v=true) const
Definition misc.hh:1432
gem5::ArmISA::MiscRegLUTEntryInitializer::highest
chain highest(ArmSystem *const sys) const
Definition misc.cc:3012
gem5::ArmISA::MiscRegLUTEntryInitializer::secure
chain secure(bool v=true) const
Definition misc.hh:1643
gem5::ArmISA::MiscRegLUTEntryInitializer::mutex
chain mutex(bool v=true) const
Definition misc.hh:1396
gem5::ArmISA::MiscRegLUTEntryInitializer::raz
chain raz(uint64_t mask=(uint64_t) -1) const
Definition misc.hh:1355
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecure
chain monSecure(bool v=true) const
Definition misc.hh:1597
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure
chain privSecure(bool v=true) const
Definition misc.hh:1484
gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure
chain nonSecure(bool v=true) const
Definition misc.hh:1630
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite
chain monNonSecureWrite(bool v=true) const
Definition misc.hh:1575
gem5::ArmISA::MiscRegLUTEntryInitializer::reset
chain reset(uint64_t res_val) const
Definition misc.hh:1337
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead
chain monNonSecureRead(bool v=true) const
Definition misc.hh:1569
gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable
chain unverifiable(bool v=true) const
Definition misc.hh:1378
gem5::ArmISA::MiscRegLUTEntryInitializer::banked
chain banked(bool v=true) const
Definition misc.hh:1402
gem5::ArmISA::MiscRegLUTEntryInitializer::res0
chain res0(uint64_t mask) const
Definition misc.hh:1343
gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild
chain bankedChild(bool v=true) const
Definition misc.hh:1414
gem5::ArmISA::MiscRegLUTEntryInitializer::hypWrite
chain hypWrite(bool v=true) const
Definition misc.hh:1536
gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges
chain allPrivileges(bool v=true) const
Definition misc.hh:1611
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead
chain monSecureRead(bool v=true) const
Definition misc.hh:1557
gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite
chain privSecureWrite(bool v=true) const
Definition misc.hh:1478
gem5::ArmISA::MiscRegLUTEntryInitializer::res1
chain res1(uint64_t mask) const
Definition misc.hh:1349
gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead
chain faultRead(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1686
gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure
chain monNonSecure(bool v=true) const
Definition misc.hh:1604
gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite
chain monSecureWrite(bool v=true) const
Definition misc.hh:1563
gem5::ArmISA::MiscRegLUTEntryInitializer::mon
chain mon(bool v=true) const
Definition misc.hh:1581
gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite
chain privNonSecureWrite(bool v=true) const
Definition misc.hh:1459
gem5::ArmISA::MiscRegLUTEntryInitializer::unserialize
chain unserialize(bool v=true) const
Definition misc.hh:1384
gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite
chain faultWrite(ExceptionLevel el, MiscRegLUTEntry::FaultCB cb) const
Definition misc.hh:1693
gem5::ArmISA::MiscRegLUTEntryInitializer::hyp
chain hyp(bool v=true) const
Definition misc.hh:1550
gem5::ArmRelease::has
bool has(ArmExtension ext) const
Definition system.hh:76
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition system.hh:187
gem5::ArmSystem::highestEL
ArmISA::ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition system.hh:191
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition system.cc:132
gem5::MiscRegOp64
This class is implementing the Base class for a generic AArch64 instruction which is making use of sy...
Definition misc64.hh:160
gem5::MiscRegOp64::miscRead
bool miscRead() const
Definition misc64.hh:176
gem5::SimObject::Params
SimObjectParams Params
Definition sim_object.hh:170
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition thread_context.hh:89
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
std::vector
STL vector class.
Definition stl.hh:37
thread_context.hh
full_system.hh
gic_v3_cpu_interface.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
gem5::SimObject::params
const Params & params() const
Definition sim_object.hh:176
warn
#define warn(...)
Definition logging.hh:256
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition utility.cc:283
gem5::ArmISA::resetCPSR
static CPSR resetCPSR(ArmSystem *system)
Definition misc.cc:3024
gem5::ArmISA::MODE_UNDEFINED
@ MODE_UNDEFINED
Definition types.hh:332
gem5::ArmISA::unflattenResultMiscReg
int unflattenResultMiscReg[NUM_MISCREGS]
If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
Definition misc.cc:719
gem5::ArmISA::asidbits
Bitfield< 7, 4 > asidbits
Definition misc_types.hh:163
gem5::ArmISA::AArch32isUndefinedGenericTimer
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:674
gem5::ArmISA::encodePhysAddrRange64
uint8_t encodePhysAddrRange64(int pa_size)
Returns the encoding corresponding to the specified n.
Definition utility.cc:1312
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition utility.cc:291
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition utility.cc:134
gem5::ArmISA::decodeAArch64SysReg
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition misc.cc:2930
gem5::ArmISA::i
Bitfield< 7 > i
Definition misc_types.hh:67
gem5::ArmISA::gic
Bitfield< 27, 24 > gic
Definition misc_types.hh:221
gem5::ArmISA::decodeCP15Reg
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition misc.cc:549
gem5::ArmISA::checkFaultAccessAArch64SysReg
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:744
gem5::ArmISA::parange
Bitfield< 3, 0 > parange
Definition misc_types.hh:164
gem5::ArmISA::opc2
Bitfield< 7, 5 > opc2
Definition types.hh:106
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition utility.cc:86
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition misc_types.hh:418
gem5::ArmISA::fgtEnabled
bool fgtEnabled(ThreadContext *tc)
Definition utility.cc:1361
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition utility.cc:268
gem5::ArmISA::preUnflattenMiscReg
void preUnflattenMiscReg()
Definition misc.cc:722
gem5::ArmISA::isHcrxEL2Enabled
bool isHcrxEL2Enabled(ThreadContext *tc)
Definition utility.cc:1369
gem5::ArmISA::MISCREG_PMXEVTYPER_EL0
@ MISCREG_PMXEVTYPER_EL0
Definition misc.hh:805
gem5::ArmISA::MISCREG_ERXSTATUS_EL1
@ MISCREG_ERXSTATUS_EL1
Definition misc.hh:1210
gem5::ArmISA::MISCREG_AMAIR_EL3
@ MISCREG_AMAIR_EL3
Definition misc.hh:817
gem5::ArmISA::MISCREG_PMEVTYPER0
@ MISCREG_PMEVTYPER0
Definition misc.hh:385
gem5::ArmISA::MISCREG_DBGWVR1_EL1
@ MISCREG_DBGWVR1_EL1
Definition misc.hh:521
gem5::ArmISA::MISCREG_DBGDRAR
@ MISCREG_DBGDRAR
Definition misc.hh:188
gem5::ArmISA::MISCREG_NSACR
@ MISCREG_NSACR
Definition misc.hh:263
gem5::ArmISA::MISCREG_DL1DATA1
@ MISCREG_DL1DATA1
Definition misc.hh:470
gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition misc.hh:591
gem5::ArmISA::MISCREG_DBGWCR5
@ MISCREG_DBGWCR5
Definition misc.hh:177
gem5::ArmISA::MISCREG_ICH_VMCR
@ MISCREG_ICH_VMCR
Definition misc.hh:1104
gem5::ArmISA::MISCREG_CSSELR_NS
@ MISCREG_CSSELR_NS
Definition misc.hh:249
gem5::ArmISA::MISCREG_HSTR_EL2
@ MISCREG_HSTR_EL2
Definition misc.hh:623
gem5::ArmISA::MISCREG_DBGWVR13_EL1
@ MISCREG_DBGWVR13_EL1
Definition misc.hh:533
gem5::ArmISA::MISCREG_PMUSERENR
@ MISCREG_PMUSERENR
Definition misc.hh:393
gem5::ArmISA::MISCREG_DBGBCR15
@ MISCREG_DBGBCR15
Definition misc.hh:155
gem5::ArmISA::MISCREG_DBGOSLSR
@ MISCREG_DBGOSLSR
Definition misc.hh:206
gem5::ArmISA::MISCREG_DBGDTRRXext
@ MISCREG_DBGDTRRXext
Definition misc.hh:120
gem5::ArmISA::MISCREG_ID_MMFR2_EL1
@ MISCREG_ID_MMFR2_EL1
Definition misc.hh:578
gem5::ArmISA::MISCREG_TTBR1_EL12
@ MISCREG_TTBR1_EL12
Definition misc.hh:635
gem5::ArmISA::MISCREG_DCCISW
@ MISCREG_DCCISW
Definition misc.hh:336
gem5::ArmISA::MISCREG_ERRIDR_EL1
@ MISCREG_ERRIDR_EL1
Definition misc.hh:1206
gem5::ArmISA::MISCREG_DACR_S
@ MISCREG_DACR_S
Definition misc.hh:285
gem5::ArmISA::MISCREG_CNTV_CTL_EL0
@ MISCREG_CNTV_CTL_EL0
Definition misc.hh:843
gem5::ArmISA::MISCREG_ICH_LR7
@ MISCREG_ICH_LR7
Definition misc.hh:1112
gem5::ArmISA::MISCREG_DBGWCR8
@ MISCREG_DBGWCR8
Definition misc.hh:180
gem5::ArmISA::MISCREG_HCR
@ MISCREG_HCR
Definition misc.hh:266
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS
@ MISCREG_ICC_BPR1_EL1_NS
Definition misc.hh:952
gem5::ArmISA::MISCREG_NMRR_NS
@ MISCREG_NMRR_NS
Definition misc.hh:406
gem5::ArmISA::MISCREG_CPSR_MODE
@ MISCREG_CPSR_MODE
Definition misc.hh:96
gem5::ArmISA::MISCREG_PRRR_MAIR0
@ MISCREG_PRRR_MAIR0
Definition misc.hh:102
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS
@ MISCREG_ICC_IGRPEN1_EL1_NS
Definition misc.hh:962
gem5::ArmISA::MISCREG_ICH_AP0R2_EL2
@ MISCREG_ICH_AP0R2_EL2
Definition misc.hh:972
gem5::ArmISA::MISCREG_VSTCR_EL2
@ MISCREG_VSTCR_EL2
Definition misc.hh:646
gem5::ArmISA::MISCREG_DBGWVR14
@ MISCREG_DBGWVR14
Definition misc.hh:170
gem5::ArmISA::MISCREG_HDFAR
@ MISCREG_HDFAR
Definition misc.hh:307
gem5::ArmISA::MISCREG_MPIDR_EL1
@ MISCREG_MPIDR_EL1
Definition misc.hh:570
gem5::ArmISA::MISCREG_ICC_IGRPEN1
@ MISCREG_ICC_IGRPEN1
Definition misc.hh:1077
gem5::ArmISA::MISCREG_DFSR_S
@ MISCREG_DFSR_S
Definition misc.hh:288
gem5::ArmISA::MISCREG_IL1DATA1
@ MISCREG_IL1DATA1
Definition misc.hh:466
gem5::ArmISA::MISCREG_DBGWVR10_EL1
@ MISCREG_DBGWVR10_EL1
Definition misc.hh:530
gem5::ArmISA::MISCREG_DL1DATA0
@ MISCREG_DL1DATA0
Definition misc.hh:469
gem5::ArmISA::MISCREG_CPUECTLR_EL1
@ MISCREG_CPUECTLR_EL1
Definition misc.hh:897
gem5::ArmISA::MISCREG_ATS1HR
@ MISCREG_ATS1HR
Definition misc.hh:337
gem5::ArmISA::MISCREG_ERXCTLR_EL1
@ MISCREG_ERXCTLR_EL1
Definition misc.hh:1209
gem5::ArmISA::MISCREG_SCTLR_EL2
@ MISCREG_SCTLR_EL2
Definition misc.hh:616
gem5::ArmISA::MISCREG_PMSELR_EL0
@ MISCREG_PMSELR_EL0
Definition misc.hh:801
gem5::ArmISA::MISCREG_ID_DFR0_EL1
@ MISCREG_ID_DFR0_EL1
Definition misc.hh:574
gem5::ArmISA::MISCREG_CNTV_CVAL_EL02
@ MISCREG_CNTV_CVAL_EL02
Definition misc.hh:850
gem5::ArmISA::MISCREG_CP15ISB
@ MISCREG_CP15ISB
Definition misc.hh:317
gem5::ArmISA::MISCREG_PMEVTYPER5
@ MISCREG_PMEVTYPER5
Definition misc.hh:390
gem5::ArmISA::MISCREG_CNTP_CTL_EL0
@ MISCREG_CNTP_CTL_EL0
Definition misc.hh:840
gem5::ArmISA::MISCREG_DFAR_NS
@ MISCREG_DFAR_NS
Definition misc.hh:302
gem5::ArmISA::MISCREG_DBGBXVR8
@ MISCREG_DBGBXVR8
Definition misc.hh:197
gem5::ArmISA::MISCREG_TLBIMVALIS
@ MISCREG_TLBIMVALIS
Definition misc.hh:343
gem5::ArmISA::MISCREG_PMOVSSET
@ MISCREG_PMOVSSET
Definition misc.hh:396
gem5::ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition misc.hh:93
gem5::ArmISA::MISCREG_DBGWCR1
@ MISCREG_DBGWCR1
Definition misc.hh:173
gem5::ArmISA::MISCREG_MPAMVPM2_EL2
@ MISCREG_MPAMVPM2_EL2
Definition misc.hh:1181
gem5::ArmISA::MISCREG_NMRR_MAIR1_S
@ MISCREG_NMRR_MAIR1_S
Definition misc.hh:107
gem5::ArmISA::MISCREG_ICH_LR7_EL2
@ MISCREG_ICH_LR7_EL2
Definition misc.hh:991
gem5::ArmISA::MISCREG_CNTP_CTL_EL02
@ MISCREG_CNTP_CTL_EL02
Definition misc.hh:846
gem5::ArmISA::MISCREG_ICC_IAR1_EL1
@ MISCREG_ICC_IAR1_EL1
Definition misc.hh:948
gem5::ArmISA::MISCREG_SPSEL
@ MISCREG_SPSEL
Definition misc.hh:655
gem5::ArmISA::MISCREG_TCR_EL2
@ MISCREG_TCR_EL2
Definition misc.hh:641
gem5::ArmISA::MISCREG_AT_S1E1W_Xt
@ MISCREG_AT_S1E1W_Xt
Definition misc.hh:698
gem5::ArmISA::MISCREG_ID_ISAR0_EL1
@ MISCREG_ID_ISAR0_EL1
Definition misc.hh:581
gem5::ArmISA::MISCREG_DBGWCR5_EL1
@ MISCREG_DBGWCR5_EL1
Definition misc.hh:541
gem5::ArmISA::MISCREG_RNDRRS
@ MISCREG_RNDRRS
Definition misc.hh:1160
gem5::ArmISA::MISCREG_DBGWVR2
@ MISCREG_DBGWVR2
Definition misc.hh:158
gem5::ArmISA::MISCREG_ICH_LR6_EL2
@ MISCREG_ICH_LR6_EL2
Definition misc.hh:990
gem5::ArmISA::MISCREG_PMEVCNTR5
@ MISCREG_PMEVCNTR5
Definition misc.hh:384
gem5::ArmISA::MISCREG_ICH_AP1R1
@ MISCREG_ICH_AP1R1
Definition misc.hh:1096
gem5::ArmISA::MISCREG_DBGDSCRint
@ MISCREG_DBGDSCRint
Definition misc.hh:114
gem5::ArmISA::MISCREG_MVFR1
@ MISCREG_MVFR1
Definition misc.hh:91
gem5::ArmISA::MISCREG_IL1DATA0_EL1
@ MISCREG_IL1DATA0_EL1
Definition misc.hh:886
gem5::ArmISA::MISCREG_MIDR_EL1
@ MISCREG_MIDR_EL1
Definition misc.hh:569
gem5::ArmISA::MISCREG_SDER
@ MISCREG_SDER
Definition misc.hh:262
gem5::ArmISA::MISCREG_DBGWCR12_EL1
@ MISCREG_DBGWCR12_EL1
Definition misc.hh:548
gem5::ArmISA::MISCREG_OSDLR_EL1
@ MISCREG_OSDLR_EL1
Definition misc.hh:560
gem5::ArmISA::MISCREG_DL1DATA3
@ MISCREG_DL1DATA3
Definition misc.hh:472
gem5::ArmISA::MISCREG_HTPIDR
@ MISCREG_HTPIDR
Definition misc.hh:441
gem5::ArmISA::MISCREG_DBGBXVR15
@ MISCREG_DBGBXVR15
Definition misc.hh:204
gem5::ArmISA::MISCREG_TLBIMVAALIS
@ MISCREG_TLBIMVAALIS
Definition misc.hh:344
gem5::ArmISA::MISCREG_ICC_MGRPEN1
@ MISCREG_ICC_MGRPEN1
Definition misc.hh:1081
gem5::ArmISA::MISCREG_ZCR_EL2
@ MISCREG_ZCR_EL2
Definition misc.hh:1141
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3
@ MISCREG_ICC_IGRPEN1_EL3
Definition misc.hh:967
gem5::ArmISA::MISCREG_SPSR_HYP
@ MISCREG_SPSR_HYP
Definition misc.hh:86
gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1
@ MISCREG_ID_AA64ZFR0_EL1
Definition misc.hh:1139
gem5::ArmISA::MISCREG_MPAMVPM7_EL2
@ MISCREG_MPAMVPM7_EL2
Definition misc.hh:1186
gem5::ArmISA::MISCREG_DBGDEVID0
@ MISCREG_DBGDEVID0
Definition misc.hh:215
gem5::ArmISA::MISCREG_CNTFRQ
@ MISCREG_CNTFRQ
Definition misc.hh:443
gem5::ArmISA::MISCREG_DBGDSAR
@ MISCREG_DBGDSAR
Definition misc.hh:209
gem5::ArmISA::MISCREG_AFSR1_EL12
@ MISCREG_AFSR1_EL12
Definition misc.hh:676
gem5::ArmISA::MISCREG_CPUMERRSR
@ MISCREG_CPUMERRSR
Definition misc.hh:479
gem5::ArmISA::MISCREG_CPSR_Q
@ MISCREG_CPSR_Q
Definition misc.hh:97
gem5::ArmISA::MISCREG_DBGBVR5_EL1
@ MISCREG_DBGBVR5_EL1
Definition misc.hh:493
gem5::ArmISA::MISCREG_MAIR_EL1
@ MISCREG_MAIR_EL1
Definition misc.hh:810
gem5::ArmISA::MISCREG_DBGBCR2_EL1
@ MISCREG_DBGBCR2_EL1
Definition misc.hh:506
gem5::ArmISA::MISCREG_ID_ISAR2_EL1
@ MISCREG_ID_ISAR2_EL1
Definition misc.hh:583
gem5::ArmISA::MISCREG_TLBIMVAAL
@ MISCREG_TLBIMVAAL
Definition misc.hh:356
gem5::ArmISA::MISCREG_DBGBVR1_EL1
@ MISCREG_DBGBVR1_EL1
Definition misc.hh:489
gem5::ArmISA::MISCREG_PAR_NS
@ MISCREG_PAR_NS
Definition misc.hh:313
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S
@ MISCREG_ICC_IGRPEN1_EL1_S
Definition misc.hh:963
gem5::ArmISA::MISCREG_HAMAIR1
@ MISCREG_HAMAIR1
Definition misc.hh:420
gem5::ArmISA::MISCREG_PMXEVCNTR_EL0
@ MISCREG_PMXEVCNTR_EL0
Definition misc.hh:807
gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS
@ MISCREG_ICC_IGRPEN1_NS
Definition misc.hh:1078
gem5::ArmISA::MISCREG_ICC_PMR_EL1
@ MISCREG_ICC_PMR_EL1
Definition misc.hh:922
gem5::ArmISA::MISCREG_CONTEXTIDR_EL1
@ MISCREG_CONTEXTIDR_EL1
Definition misc.hh:829
gem5::ArmISA::MISCREG_CNTV_TVAL
@ MISCREG_CNTV_TVAL
Definition misc.hh:457
gem5::ArmISA::MISCREG_VBAR_EL3
@ MISCREG_VBAR_EL3
Definition misc.hh:826
gem5::ArmISA::MISCREG_AIFSR_NS
@ MISCREG_AIFSR_NS
Definition misc.hh:296
gem5::ArmISA::MISCREG_DBGWCR10
@ MISCREG_DBGWCR10
Definition misc.hh:182
gem5::ArmISA::MISCREG_DBGBXVR9
@ MISCREG_DBGBXVR9
Definition misc.hh:198
gem5::ArmISA::MISCREG_ICC_CTLR_NS
@ MISCREG_ICC_CTLR_NS
Definition misc.hh:1066
gem5::ArmISA::MISCREG_PMEVTYPER1
@ MISCREG_PMEVTYPER1
Definition misc.hh:386
gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1
@ MISCREG_CNTPS_TVAL_EL1
Definition misc.hh:856
gem5::ArmISA::MISCREG_ICC_AP1R3
@ MISCREG_ICC_AP1R3
Definition misc.hh:1057
gem5::ArmISA::MISCREG_ICC_MCTLR
@ MISCREG_ICC_MCTLR
Definition misc.hh:1080
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition misc.hh:269
gem5::ArmISA::MISCREG_SPSR_EL2
@ MISCREG_SPSR_EL2
Definition misc.hh:663
gem5::ArmISA::MISCREG_ICH_LR8
@ MISCREG_ICH_LR8
Definition misc.hh:1113
gem5::ArmISA::MISCREG_MPAMVPM4_EL2
@ MISCREG_MPAMVPM4_EL2
Definition misc.hh:1183
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1
@ MISCREG_ICC_AP1R0_EL1
Definition misc.hh:931
gem5::ArmISA::MISCREG_ICC_BPR0_EL1
@ MISCREG_ICC_BPR0_EL1
Definition misc.hh:926
gem5::ArmISA::MISCREG_DBGWFAR
@ MISCREG_DBGWFAR
Definition misc.hh:118
gem5::ArmISA::MISCREG_IFAR
@ MISCREG_IFAR
Definition misc.hh:304
gem5::ArmISA::MISCREG_FCSEIDR
@ MISCREG_FCSEIDR
Definition misc.hh:428
gem5::ArmISA::MISCREG_DBGWVR7
@ MISCREG_DBGWVR7
Definition misc.hh:163
gem5::ArmISA::MISCREG_ID_MMFR1
@ MISCREG_ID_MMFR1
Definition misc.hh:234
gem5::ArmISA::MISCREG_AT_S1E2W_Xt
@ MISCREG_AT_S1E2W_Xt
Definition misc.hh:709
gem5::ArmISA::MISCREG_PMEVTYPER1_EL0
@ MISCREG_PMEVTYPER1_EL0
Definition misc.hh:881
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition misc.hh:101
gem5::ArmISA::MISCREG_ICH_LR15_EL2
@ MISCREG_ICH_LR15_EL2
Definition misc.hh:999
gem5::ArmISA::MISCREG_FPSID
@ MISCREG_FPSID
Definition misc.hh:89
gem5::ArmISA::MISCREG_MPAM3_EL3
@ MISCREG_MPAM3_EL3
Definition misc.hh:1175
gem5::ArmISA::MISCREG_DBGBXVR12
@ MISCREG_DBGBXVR12
Definition misc.hh:201
gem5::ArmISA::MISCREG_ICH_MISR
@ MISCREG_ICH_MISR
Definition misc.hh:1101
gem5::ArmISA::MISCREG_DBGWCR6_EL1
@ MISCREG_DBGWCR6_EL1
Definition misc.hh:542
gem5::ArmISA::MISCREG_ID_AFR0_EL1
@ MISCREG_ID_AFR0_EL1
Definition misc.hh:575
gem5::ArmISA::MISCREG_DBGBVR2
@ MISCREG_DBGBVR2
Definition misc.hh:126
gem5::ArmISA::MISCREG_MAIR_EL12
@ MISCREG_MAIR_EL12
Definition misc.hh:811
gem5::ArmISA::MISCREG_DBGBVR7_EL1
@ MISCREG_DBGBVR7_EL1
Definition misc.hh:495
gem5::ArmISA::MISCREG_ICH_LRC0
@ MISCREG_ICH_LRC0
Definition misc.hh:1121
gem5::ArmISA::MISCREG_SMIDR_EL1
@ MISCREG_SMIDR_EL1
Definition misc.hh:1148
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition misc.hh:253
gem5::ArmISA::MISCREG_PAR_EL1
@ MISCREG_PAR_EL1
Definition misc.hh:693
gem5::ArmISA::MISCREG_TTBCR
@ MISCREG_TTBCR
Definition misc.hh:278
gem5::ArmISA::MISCREG_DBGWVR3_EL1
@ MISCREG_DBGWVR3_EL1
Definition misc.hh:523
gem5::ArmISA::MISCREG_ICH_LR5
@ MISCREG_ICH_LR5
Definition misc.hh:1110
gem5::ArmISA::MISCREG_AT_S12E1W_Xt
@ MISCREG_AT_S12E1W_Xt
Definition misc.hh:711
gem5::ArmISA::MISCREG_TLBIIPAS2
@ MISCREG_TLBIIPAS2
Definition misc.hh:363
gem5::ArmISA::MISCREG_ATS12NSOUW
@ MISCREG_ATS12NSOUW
Definition misc.hh:329
gem5::ArmISA::MISCREG_MAIR_EL2
@ MISCREG_MAIR_EL2
Definition misc.hh:814
gem5::ArmISA::MISCREG_CNTV_CVAL
@ MISCREG_CNTV_CVAL
Definition misc.hh:456
gem5::ArmISA::MISCREG_APDBKeyLo_EL1
@ MISCREG_APDBKeyLo_EL1
Definition misc.hh:913
gem5::ArmISA::MISCREG_MDRAR_EL1
@ MISCREG_MDRAR_EL1
Definition misc.hh:557
gem5::ArmISA::MISCREG_CSSELR
@ MISCREG_CSSELR
Definition misc.hh:248
gem5::ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition misc.hh:259
gem5::ArmISA::MISCREG_HAMAIR0
@ MISCREG_HAMAIR0
Definition misc.hh:419
gem5::ArmISA::MISCREG_TLBIIPAS2L
@ MISCREG_TLBIIPAS2L
Definition misc.hh:364
gem5::ArmISA::MISCREG_ICC_BPR1_S
@ MISCREG_ICC_BPR1_S
Definition misc.hh:1064
gem5::ArmISA::MISCREG_DBGBVR8
@ MISCREG_DBGBVR8
Definition misc.hh:132
gem5::ArmISA::MISCREG_ADFSR_S
@ MISCREG_ADFSR_S
Definition misc.hh:294
gem5::ArmISA::MISCREG_ICH_LRC11
@ MISCREG_ICH_LRC11
Definition misc.hh:1132
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition misc.hh:628
gem5::ArmISA::MISCREG_TTBR0_S
@ MISCREG_TTBR0_S
Definition misc.hh:274
gem5::ArmISA::MISCREG_TLBIALLHIS
@ MISCREG_TLBIALLHIS
Definition misc.hh:359
gem5::ArmISA::MISCREG_IL1DATA1_EL1
@ MISCREG_IL1DATA1_EL1
Definition misc.hh:887
gem5::ArmISA::MISCREG_CNTKCTL_EL12
@ MISCREG_CNTKCTL_EL12
Definition misc.hh:853
gem5::ArmISA::MISCREG_APDAKeyHi_EL1
@ MISCREG_APDAKeyHi_EL1
Definition misc.hh:910
gem5::ArmISA::MISCREG_TLBIIPAS2LIS
@ MISCREG_TLBIIPAS2LIS
Definition misc.hh:358
gem5::ArmISA::MISCREG_TLBIASIDIS
@ MISCREG_TLBIASIDIS
Definition misc.hh:341
gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1
@ MISCREG_ID_AA64DFR0_EL1
Definition misc.hh:593
gem5::ArmISA::MISCREG_ID_ISAR6
@ MISCREG_ID_ISAR6
Definition misc.hh:244
gem5::ArmISA::MISCREG_DBGCLAIMCLR
@ MISCREG_DBGCLAIMCLR
Definition misc.hh:211
gem5::ArmISA::MISCREG_TPIDRRO_EL0
@ MISCREG_TPIDRRO_EL0
Definition misc.hh:833
gem5::ArmISA::MISCREG_DBGBVR3
@ MISCREG_DBGBVR3
Definition misc.hh:127
gem5::ArmISA::MISCREG_DBGWVR5_EL1
@ MISCREG_DBGWVR5_EL1
Definition misc.hh:525
gem5::ArmISA::MISCREG_DBGOSLAR
@ MISCREG_DBGOSLAR
Definition misc.hh:205
gem5::ArmISA::MISCREG_PMEVTYPER3_EL0
@ MISCREG_PMEVTYPER3_EL0
Definition misc.hh:883
gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS
@ MISCREG_ICC_SRE_EL1_NS
Definition misc.hh:958
gem5::ArmISA::MISCREG_DBGBCR10
@ MISCREG_DBGBCR10
Definition misc.hh:150
gem5::ArmISA::MISCREG_SPSR_SVC
@ MISCREG_SPSR_SVC
Definition misc.hh:83
gem5::ArmISA::MISCREG_REVIDR_EL1
@ MISCREG_REVIDR_EL1
Definition misc.hh:571
gem5::ArmISA::MISCREG_DBGDSCRext
@ MISCREG_DBGDSCRext
Definition misc.hh:121
gem5::ArmISA::MISCREG_SCTLR2_EL12
@ MISCREG_SCTLR2_EL12
Definition misc.hh:612
gem5::ArmISA::MISCREG_SCTLR2_EL1
@ MISCREG_SCTLR2_EL1
Definition misc.hh:611
gem5::ArmISA::MISCREG_TCR_EL3
@ MISCREG_TCR_EL3
Definition misc.hh:648
gem5::ArmISA::MISCREG_SCTLR2_EL3
@ MISCREG_SCTLR2_EL3
Definition misc.hh:626
gem5::ArmISA::MISCREG_SMCR_EL1
@ MISCREG_SMCR_EL1
Definition misc.hh:1154
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition misc.hh:660
gem5::ArmISA::MISCREG_DBGDIDR
@ MISCREG_DBGDIDR
Definition misc.hh:113
gem5::ArmISA::MISCREG_DBGBVR9_EL1
@ MISCREG_DBGBVR9_EL1
Definition misc.hh:497
gem5::ArmISA::MISCREG_ICH_HCR_EL2
@ MISCREG_ICH_HCR_EL2
Definition misc.hh:978
gem5::ArmISA::MISCREG_CPACR_EL12
@ MISCREG_CPACR_EL12
Definition misc.hh:615
gem5::ArmISA::MISCREG_HDCR
@ MISCREG_HDCR
Definition misc.hh:268
gem5::ArmISA::MISCREG_AIFSR_S
@ MISCREG_AIFSR_S
Definition misc.hh:297
gem5::ArmISA::MISCREG_ESR_EL1
@ MISCREG_ESR_EL1
Definition misc.hh:677
gem5::ArmISA::MISCREG_DISR_EL1
@ MISCREG_DISR_EL1
Definition misc.hh:1214
gem5::ArmISA::MISCREG_ADFSR
@ MISCREG_ADFSR
Definition misc.hh:292
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS
@ MISCREG_ICC_AP1R3_EL1_NS
Definition misc.hh:941
gem5::ArmISA::MISCREG_PMCCNTR_EL0
@ MISCREG_PMCCNTR_EL0
Definition misc.hh:804
gem5::ArmISA::MISCREG_CNTP_TVAL
@ MISCREG_CNTP_TVAL
Definition misc.hh:452
gem5::ArmISA::MISCREG_MDCCSR_EL0
@ MISCREG_MDCCSR_EL0
Definition misc.hh:552
gem5::ArmISA::MISCREG_DTLBIMVA
@ MISCREG_DTLBIMVA
Definition misc.hh:349
gem5::ArmISA::MISCREG_SPSR_UND_AA64
@ MISCREG_SPSR_UND_AA64
Definition misc.hh:668
gem5::ArmISA::MISCREG_DBGWVR13
@ MISCREG_DBGWVR13
Definition misc.hh:169
gem5::ArmISA::MISCREG_AT_S12E0W_Xt
@ MISCREG_AT_S12E0W_Xt
Definition misc.hh:713
gem5::ArmISA::MISCREG_PMEVTYPER2
@ MISCREG_PMEVTYPER2
Definition misc.hh:387
gem5::ArmISA::MISCREG_DBGBXVR4
@ MISCREG_DBGBXVR4
Definition misc.hh:193
gem5::ArmISA::MISCREG_TCR_EL1
@ MISCREG_TCR_EL1
Definition misc.hh:636
gem5::ArmISA::MISCREG_PMINTENSET
@ MISCREG_PMINTENSET
Definition misc.hh:394
gem5::ArmISA::MISCREG_TTBCR_NS
@ MISCREG_TTBCR_NS
Definition misc.hh:279
gem5::ArmISA::MISCREG_PMXEVTYPER
@ MISCREG_PMXEVTYPER
Definition misc.hh:378
gem5::ArmISA::MISCREG_DBGBCR13_EL1
@ MISCREG_DBGBCR13_EL1
Definition misc.hh:517
gem5::ArmISA::MISCREG_TPIDR_EL3
@ MISCREG_TPIDR_EL3
Definition misc.hh:835
gem5::ArmISA::MISCREG_DBGBVR11
@ MISCREG_DBGBVR11
Definition misc.hh:135
gem5::ArmISA::MISCREG_HFGRTR_EL2
@ MISCREG_HFGRTR_EL2
Definition misc.hh:1164
gem5::ArmISA::MISCREG_ICC_AP0R3
@ MISCREG_ICC_AP0R3
Definition misc.hh:1047
gem5::ArmISA::MISCREG_VMPIDR
@ MISCREG_VMPIDR
Definition misc.hh:252
gem5::ArmISA::MISCREG_TPIDRURW_S
@ MISCREG_TPIDRURW_S
Definition misc.hh:434
gem5::ArmISA::MISCREG_CCSIDR_EL1
@ MISCREG_CCSIDR_EL1
Definition misc.hh:601
gem5::ArmISA::MISCREG_DBGBXVR5
@ MISCREG_DBGBXVR5
Definition misc.hh:194
gem5::ArmISA::MISCREG_CNTVCT
@ MISCREG_CNTVCT
Definition misc.hh:445
gem5::ArmISA::MISCREG_ESR_EL12
@ MISCREG_ESR_EL12
Definition misc.hh:678
gem5::ArmISA::MISCREG_TLBIMVALH
@ MISCREG_TLBIMVALH
Definition misc.hh:368
gem5::ArmISA::MISCREG_DL1DATA1_EL1
@ MISCREG_DL1DATA1_EL1
Definition misc.hh:891
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S
@ MISCREG_ICC_AP1R0_EL1_S
Definition misc.hh:933
gem5::ArmISA::MISCREG_DBGWCR8_EL1
@ MISCREG_DBGWCR8_EL1
Definition misc.hh:544
gem5::ArmISA::MISCREG_ICC_IGRPEN1_S
@ MISCREG_ICC_IGRPEN1_S
Definition misc.hh:1079
gem5::ArmISA::MISCREG_AFSR0_EL1
@ MISCREG_AFSR0_EL1
Definition misc.hh:673
gem5::ArmISA::MISCREG_ICC_AP1R0_S
@ MISCREG_ICC_AP1R0_S
Definition misc.hh:1050
gem5::ArmISA::MISCREG_SPSR_UND
@ MISCREG_SPSR_UND
Definition misc.hh:87
gem5::ArmISA::MISCREG_TCMTR
@ MISCREG_TCMTR
Definition misc.hh:225
gem5::ArmISA::MISCREG_DBGWCR13_EL1
@ MISCREG_DBGWCR13_EL1
Definition misc.hh:549
gem5::ArmISA::MISCREG_DBGOSDLR
@ MISCREG_DBGOSDLR
Definition misc.hh:207
gem5::ArmISA::MISCREG_DBGBXVR3
@ MISCREG_DBGBXVR3
Definition misc.hh:192
gem5::ArmISA::MISCREG_DBGWCR11_EL1
@ MISCREG_DBGWCR11_EL1
Definition misc.hh:547
gem5::ArmISA::MISCREG_DBGWVR11_EL1
@ MISCREG_DBGWVR11_EL1
Definition misc.hh:531
gem5::ArmISA::MISCREG_SPSR_IRQ
@ MISCREG_SPSR_IRQ
Definition misc.hh:82
gem5::ArmISA::MISCREG_ID_ISAR5
@ MISCREG_ID_ISAR5
Definition misc.hh:243
gem5::ArmISA::MISCREG_BPIALL
@ MISCREG_BPIALL
Definition misc.hh:318
gem5::ArmISA::MISCREG_DBGBVR10_EL1
@ MISCREG_DBGBVR10_EL1
Definition misc.hh:498
gem5::ArmISA::MISCREG_ID_ISAR3_EL1
@ MISCREG_ID_ISAR3_EL1
Definition misc.hh:584
gem5::ArmISA::MISCREG_PMEVTYPER4_EL0
@ MISCREG_PMEVTYPER4_EL0
Definition misc.hh:884
gem5::ArmISA::MISCREG_ATS1CUR
@ MISCREG_ATS1CUR
Definition misc.hh:324
gem5::ArmISA::MISCREG_ICH_ELRSR_EL2
@ MISCREG_ICH_ELRSR_EL2
Definition misc.hh:982
gem5::ArmISA::MISCREG_DC_CVAC_Xt
@ MISCREG_DC_CVAC_Xt
Definition misc.hh:705
gem5::ArmISA::MISCREG_VPIDR_EL2
@ MISCREG_VPIDR_EL2
Definition misc.hh:607
gem5::ArmISA::MISCREG_DBGWCR2
@ MISCREG_DBGWCR2
Definition misc.hh:174
gem5::ArmISA::MISCREG_OSLAR_EL1
@ MISCREG_OSLAR_EL1
Definition misc.hh:558
gem5::ArmISA::MISCREG_CNTPCT_EL0
@ MISCREG_CNTPCT_EL0
Definition misc.hh:838
gem5::ArmISA::MISCREG_DBGWCR4_EL1
@ MISCREG_DBGWCR4_EL1
Definition misc.hh:540
gem5::ArmISA::MISCREG_ERXADDR_EL1
@ MISCREG_ERXADDR_EL1
Definition misc.hh:1211
gem5::ArmISA::MISCREG_AMAIR0_NS
@ MISCREG_AMAIR0_NS
Definition misc.hh:412
gem5::ArmISA::MISCREG_DBGBCR14_EL1
@ MISCREG_DBGBCR14_EL1
Definition misc.hh:518
gem5::ArmISA::MISCREG_ICH_AP1R3
@ MISCREG_ICH_AP1R3
Definition misc.hh:1098
gem5::ArmISA::MISCREG_MPAM1_EL1
@ MISCREG_MPAM1_EL1
Definition misc.hh:1173
gem5::ArmISA::MISCREG_SPSR_ABT
@ MISCREG_SPSR_ABT
Definition misc.hh:85
gem5::ArmISA::MISCREG_DBGWVR0_EL1
@ MISCREG_DBGWVR0_EL1
Definition misc.hh:520
gem5::ArmISA::MISCREG_AFSR1_EL2
@ MISCREG_AFSR1_EL2
Definition misc.hh:681
gem5::ArmISA::MISCREG_CNTV_CTL_EL02
@ MISCREG_CNTV_CTL_EL02
Definition misc.hh:849
gem5::ArmISA::MISCREG_CP15DMB
@ MISCREG_CP15DMB
Definition misc.hh:333
gem5::ArmISA::MISCREG_DBGBCR0_EL1
@ MISCREG_DBGBCR0_EL1
Definition misc.hh:504
gem5::ArmISA::MISCREG_SCTLR2_EL2
@ MISCREG_SCTLR2_EL2
Definition misc.hh:617
gem5::ArmISA::MISCREG_DBGWVR15
@ MISCREG_DBGWVR15
Definition misc.hh:171
gem5::ArmISA::MISCREG_TLBIMVA
@ MISCREG_TLBIMVA
Definition misc.hh:352
gem5::ArmISA::MISCREG_PMEVCNTR4_EL0
@ MISCREG_PMEVCNTR4_EL0
Definition misc.hh:878
gem5::ArmISA::MISCREG_CONTEXTIDR_NS
@ MISCREG_CONTEXTIDR_NS
Definition misc.hh:430
gem5::ArmISA::MISCREG_ICH_AP1R3_EL2
@ MISCREG_ICH_AP1R3_EL2
Definition misc.hh:977
gem5::ArmISA::MISCREG_DBGBCR6_EL1
@ MISCREG_DBGBCR6_EL1
Definition misc.hh:510
gem5::ArmISA::MISCREG_HFGITR_EL2
@ MISCREG_HFGITR_EL2
Definition misc.hh:1163
gem5::ArmISA::MISCREG_ID_ISAR4
@ MISCREG_ID_ISAR4
Definition misc.hh:242
gem5::ArmISA::MISCREG_DBGBCR3_EL1
@ MISCREG_DBGBCR3_EL1
Definition misc.hh:507
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S
@ MISCREG_ICC_AP1R1_EL1_S
Definition misc.hh:936
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition misc.hh:609
gem5::ArmISA::MISCREG_CNTP_TVAL_EL02
@ MISCREG_CNTP_TVAL_EL02
Definition misc.hh:848
gem5::ArmISA::MISCREG_ICH_AP0R3
@ MISCREG_ICH_AP0R3
Definition misc.hh:1094
gem5::ArmISA::MISCREG_DBGWVR4_EL1
@ MISCREG_DBGWVR4_EL1
Definition misc.hh:524
gem5::ArmISA::MISCREG_TPIDRPRW_NS
@ MISCREG_TPIDRPRW_NS
Definition misc.hh:439
gem5::ArmISA::MISCREG_PMEVCNTR3
@ MISCREG_PMEVCNTR3
Definition misc.hh:382
gem5::ArmISA::MISCREG_AIDR_EL1
@ MISCREG_AIDR_EL1
Definition misc.hh:603
gem5::ArmISA::MISCREG_DC_CIVAC_Xt
@ MISCREG_DC_CIVAC_Xt
Definition misc.hh:707
gem5::ArmISA::MISCREG_DBGDEVID1
@ MISCREG_DBGDEVID1
Definition misc.hh:214
gem5::ArmISA::MISCREG_PRRR
@ MISCREG_PRRR
Definition misc.hh:399
gem5::ArmISA::MISCREG_ICC_IGRPEN0
@ MISCREG_ICC_IGRPEN0
Definition misc.hh:1076
gem5::ArmISA::MISCREG_ICH_LRC7
@ MISCREG_ICH_LRC7
Definition misc.hh:1128
gem5::ArmISA::MISCREG_TEECR
@ MISCREG_TEECR
Definition misc.hh:216
gem5::ArmISA::MISCREG_DC_CVAU_Xt
@ MISCREG_DC_CVAU_Xt
Definition misc.hh:706
gem5::ArmISA::MISCREG_DBGBXVR7
@ MISCREG_DBGBXVR7
Definition misc.hh:196
gem5::ArmISA::MISCREG_AMAIR1_S
@ MISCREG_AMAIR1_S
Definition misc.hh:416
gem5::ArmISA::MISCREG_DBGWVR7_EL1
@ MISCREG_DBGWVR7_EL1
Definition misc.hh:527
gem5::ArmISA::MISCREG_DBGBVR9
@ MISCREG_DBGBVR9
Definition misc.hh:133
gem5::ArmISA::MISCREG_PMEVTYPER0_EL0
@ MISCREG_PMEVTYPER0_EL0
Definition misc.hh:880
gem5::ArmISA::MISCREG_ICH_LRC8
@ MISCREG_ICH_LRC8
Definition misc.hh:1129
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition misc.hh:622
gem5::ArmISA::MISCREG_ICH_LR9_EL2
@ MISCREG_ICH_LR9_EL2
Definition misc.hh:993
gem5::ArmISA::MISCREG_DBGBCR8_EL1
@ MISCREG_DBGBCR8_EL1
Definition misc.hh:512
gem5::ArmISA::MISCREG_CCSIDR
@ MISCREG_CCSIDR
Definition misc.hh:245
gem5::ArmISA::MISCREG_FAR_EL1
@ MISCREG_FAR_EL1
Definition misc.hh:687
gem5::ArmISA::MISCREG_ERXMISC0_EL1
@ MISCREG_ERXMISC0_EL1
Definition misc.hh:1212
gem5::ArmISA::MISCREG_TPIDR_EL1
@ MISCREG_TPIDR_EL1
Definition misc.hh:831
gem5::ArmISA::MISCREG_PMUSERENR_EL0
@ MISCREG_PMUSERENR_EL0
Definition misc.hh:808
gem5::ArmISA::MISCREG_APIAKeyLo_EL1
@ MISCREG_APIAKeyLo_EL1
Definition misc.hh:917
gem5::ArmISA::MISCREG_DBGWCR0
@ MISCREG_DBGWCR0
Definition misc.hh:172
gem5::ArmISA::MISCREG_AT_S1E2R_Xt
@ MISCREG_AT_S1E2R_Xt
Definition misc.hh:708
gem5::ArmISA::MISCREG_PMCR
@ MISCREG_PMCR
Definition misc.hh:369
gem5::ArmISA::MISCREG_CNTHV_CTL_EL2
@ MISCREG_CNTHV_CTL_EL2
Definition misc.hh:865
gem5::ArmISA::MISCREG_ICC_DIR
@ MISCREG_ICC_DIR
Definition misc.hh:1068
gem5::ArmISA::MISCREG_CNTP_TVAL_NS
@ MISCREG_CNTP_TVAL_NS
Definition misc.hh:453
gem5::ArmISA::MISCREG_CNTV_CTL
@ MISCREG_CNTV_CTL
Definition misc.hh:455
gem5::ArmISA::MISCREG_AFSR1_EL3
@ MISCREG_AFSR1_EL3
Definition misc.hh:685
gem5::ArmISA::MISCREG_ADFSR_NS
@ MISCREG_ADFSR_NS
Definition misc.hh:293
gem5::ArmISA::MISCREG_APIBKeyLo_EL1
@ MISCREG_APIBKeyLo_EL1
Definition misc.hh:919
gem5::ArmISA::MISCREG_DFAR
@ MISCREG_DFAR
Definition misc.hh:301
gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1
@ MISCREG_ID_AA64DFR1_EL1
Definition misc.hh:594
gem5::ArmISA::MISCREG_DC_CSW_Xt
@ MISCREG_DC_CSW_Xt
Definition misc.hh:701
gem5::ArmISA::MISCREG_JMCR
@ MISCREG_JMCR
Definition misc.hh:220
gem5::ArmISA::MISCREG_RMR_EL3
@ MISCREG_RMR_EL3
Definition misc.hh:828
gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition misc.hh:598
gem5::ArmISA::MISCREG_PMEVCNTR2
@ MISCREG_PMEVCNTR2
Definition misc.hh:381
gem5::ArmISA::MISCREG_TLBIMVAL
@ MISCREG_TLBIMVAL
Definition misc.hh:355
gem5::ArmISA::MISCREG_SMCR_EL3
@ MISCREG_SMCR_EL3
Definition misc.hh:1151
gem5::ArmISA::MISCREG_ELR_EL12
@ MISCREG_ELR_EL12
Definition misc.hh:653
gem5::ArmISA::MISCREG_DL1DATA2_EL1
@ MISCREG_DL1DATA2_EL1
Definition misc.hh:892
gem5::ArmISA::MISCREG_DBGBVR0
@ MISCREG_DBGBVR0
Definition misc.hh:124
gem5::ArmISA::MISCREG_ICC_HSRE
@ MISCREG_ICC_HSRE
Definition misc.hh:1073
gem5::ArmISA::MISCREG_ICH_LR1
@ MISCREG_ICH_LR1
Definition misc.hh:1106
gem5::ArmISA::MISCREG_PMEVCNTR0_EL0
@ MISCREG_PMEVCNTR0_EL0
Definition misc.hh:874
gem5::ArmISA::MISCREG_TEECR32_EL1
@ MISCREG_TEECR32_EL1
Definition misc.hh:565
gem5::ArmISA::MISCREG_AFSR0_EL3
@ MISCREG_AFSR0_EL3
Definition misc.hh:684
gem5::ArmISA::MISCREG_CSSELR_EL1
@ MISCREG_CSSELR_EL1
Definition misc.hh:604
gem5::ArmISA::MISCREG_VBAR_EL12
@ MISCREG_VBAR_EL12
Definition misc.hh:821
gem5::ArmISA::MISCREG_MAIR_EL3
@ MISCREG_MAIR_EL3
Definition misc.hh:816
gem5::ArmISA::MISCREG_ITLBIALL
@ MISCREG_ITLBIALL
Definition misc.hh:345
gem5::ArmISA::MISCREG_L2MERRSR
@ MISCREG_L2MERRSR
Definition misc.hh:480
gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1
@ MISCREG_ID_AA64MMFR1_EL1
Definition misc.hh:600
gem5::ArmISA::MISCREG_DBGPRCR_EL1
@ MISCREG_DBGPRCR_EL1
Definition misc.hh:561
gem5::ArmISA::MISCREG_NMRR_MAIR1
@ MISCREG_NMRR_MAIR1
Definition misc.hh:105
gem5::ArmISA::MISCREG_ICH_LR4_EL2
@ MISCREG_ICH_LR4_EL2
Definition misc.hh:988
gem5::ArmISA::MISCREG_UNKNOWN
@ MISCREG_UNKNOWN
Definition misc.hh:1198
gem5::ArmISA::MISCREG_PMOVSR
@ MISCREG_PMOVSR
Definition misc.hh:372
gem5::ArmISA::MISCREG_ICH_ELRSR
@ MISCREG_ICH_ELRSR
Definition misc.hh:1103
gem5::ArmISA::MISCREG_TLBIALLNSNH
@ MISCREG_TLBIALLNSNH
Definition misc.hh:367
gem5::ArmISA::MISCREG_TTBR0_EL12
@ MISCREG_TTBR0_EL12
Definition misc.hh:633
gem5::ArmISA::MISCREG_CNTHP_TVAL
@ MISCREG_CNTHP_TVAL
Definition misc.hh:462
gem5::ArmISA::MISCREG_ATS12NSOUR
@ MISCREG_ATS12NSOUR
Definition misc.hh:328
gem5::ArmISA::MISCREG_ELR_HYP
@ MISCREG_ELR_HYP
Definition misc.hh:88
gem5::ArmISA::MISCREG_DBGWCR10_EL1
@ MISCREG_DBGWCR10_EL1
Definition misc.hh:546
gem5::ArmISA::MISCREG_CNTVCT_EL0
@ MISCREG_CNTVCT_EL0
Definition misc.hh:839
gem5::ArmISA::MISCREG_DBGBVR14
@ MISCREG_DBGBVR14
Definition misc.hh:138
gem5::ArmISA::MISCREG_DBGBVR8_EL1
@ MISCREG_DBGBVR8_EL1
Definition misc.hh:496
gem5::ArmISA::MISCREG_ICH_LR11_EL2
@ MISCREG_ICH_LR11_EL2
Definition misc.hh:995
gem5::ArmISA::MISCREG_CBAR_EL1
@ MISCREG_CBAR_EL1
Definition misc.hh:900
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1
@ MISCREG_ICC_AP1R1_EL1
Definition misc.hh:934
gem5::ArmISA::MISCREG_DL1DATA3_EL1
@ MISCREG_DL1DATA3_EL1
Definition misc.hh:893
gem5::ArmISA::MISCREG_RVBAR_EL2
@ MISCREG_RVBAR_EL2
Definition misc.hh:825
gem5::ArmISA::MISCREG_DBGDEVID2
@ MISCREG_DBGDEVID2
Definition misc.hh:213
gem5::ArmISA::MISCREG_SP_EL0
@ MISCREG_SP_EL0
Definition misc.hh:654
gem5::ArmISA::MISCREG_PMCNTENCLR
@ MISCREG_PMCNTENCLR
Definition misc.hh:371
gem5::ArmISA::MISCREG_ERRSELR_EL1
@ MISCREG_ERRSELR_EL1
Definition misc.hh:1207
gem5::ArmISA::MISCREG_DFAR_S
@ MISCREG_DFAR_S
Definition misc.hh:303
gem5::ArmISA::MISCREG_DBGBVR0_EL1
@ MISCREG_DBGBVR0_EL1
Definition misc.hh:488
gem5::ArmISA::MISCREG_ICC_AP1R2_NS
@ MISCREG_ICC_AP1R2_NS
Definition misc.hh:1055
gem5::ArmISA::MISCREG_DBGBCR4_EL1
@ MISCREG_DBGBCR4_EL1
Definition misc.hh:508
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition misc.hh:79
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition misc.hh:659
gem5::ArmISA::MISCREG_SDCR
@ MISCREG_SDCR
Definition misc.hh:260
gem5::ArmISA::MISCREG_DBGWCR4
@ MISCREG_DBGWCR4
Definition misc.hh:176
gem5::ArmISA::MISCREG_ICH_LR14_EL2
@ MISCREG_ICH_LR14_EL2
Definition misc.hh:998
gem5::ArmISA::MISCREG_RMR
@ MISCREG_RMR
Definition misc.hh:425
gem5::ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition misc.hh:614
gem5::ArmISA::MISCREG_PMEVTYPER3
@ MISCREG_PMEVTYPER3
Definition misc.hh:388
gem5::ArmISA::MISCREG_HACR
@ MISCREG_HACR
Definition misc.hh:271
gem5::ArmISA::MISCREG_ICC_RPR_EL1
@ MISCREG_ICC_RPR_EL1
Definition misc.hh:944
gem5::ArmISA::MISCREG_DBGBXVR13
@ MISCREG_DBGBXVR13
Definition misc.hh:202
gem5::ArmISA::MISCREG_IFSR_NS
@ MISCREG_IFSR_NS
Definition misc.hh:290
gem5::ArmISA::MISCREG_SMPRI_EL1
@ MISCREG_SMPRI_EL1
Definition misc.hh:1149
gem5::ArmISA::MISCREG_ID_MMFR0
@ MISCREG_ID_MMFR0
Definition misc.hh:233
gem5::ArmISA::MISCREG_PMEVTYPER5_EL0
@ MISCREG_PMEVTYPER5_EL0
Definition misc.hh:885
gem5::ArmISA::MISCREG_CNTP_CVAL
@ MISCREG_CNTP_CVAL
Definition misc.hh:449
gem5::ArmISA::MISCREG_ID_ISAR0
@ MISCREG_ID_ISAR0
Definition misc.hh:238
gem5::ArmISA::MISCREG_DBGBVR2_EL1
@ MISCREG_DBGBVR2_EL1
Definition misc.hh:490
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S
@ MISCREG_ICC_AP1R3_EL1_S
Definition misc.hh:942
gem5::ArmISA::MISCREG_DL1DATA4
@ MISCREG_DL1DATA4
Definition misc.hh:473
gem5::ArmISA::MISCREG_CNTKCTL_EL1
@ MISCREG_CNTKCTL_EL1
Definition misc.hh:852
gem5::ArmISA::MISCREG_HMAIR0
@ MISCREG_HMAIR0
Definition misc.hh:417
gem5::ArmISA::MISCREG_DBGWVR11
@ MISCREG_DBGWVR11
Definition misc.hh:167
gem5::ArmISA::MISCREG_ICC_AP0R3_EL1
@ MISCREG_ICC_AP0R3_EL1
Definition misc.hh:930
gem5::ArmISA::MISCREG_MPAMHCR_EL2
@ MISCREG_MPAMHCR_EL2
Definition misc.hh:1177
gem5::ArmISA::MISCREG_ICC_BPR1_NS
@ MISCREG_ICC_BPR1_NS
Definition misc.hh:1063
gem5::ArmISA::MISCREG_CNTPCT
@ MISCREG_CNTPCT
Definition misc.hh:444
gem5::ArmISA::MISCREG_ICH_LR10_EL2
@ MISCREG_ICH_LR10_EL2
Definition misc.hh:994
gem5::ArmISA::MISCREG_SP_EL2
@ MISCREG_SP_EL2
Definition misc.hh:672
gem5::ArmISA::MISCREG_ICC_AP0R1
@ MISCREG_ICC_AP0R1
Definition misc.hh:1045
gem5::ArmISA::MISCREG_PMCCFILTR_EL0
@ MISCREG_PMCCFILTR_EL0
Definition misc.hh:806
gem5::ArmISA::MISCREG_ICH_LR10
@ MISCREG_ICH_LR10
Definition misc.hh:1115
gem5::ArmISA::MISCREG_CNTPS_CTL_EL1
@ MISCREG_CNTPS_CTL_EL1
Definition misc.hh:854
gem5::ArmISA::MISCREG_ID_AA64MMFR3_EL1
@ MISCREG_ID_AA64MMFR3_EL1
Definition misc.hh:907
gem5::ArmISA::MISCREG_NMRR
@ MISCREG_NMRR
Definition misc.hh:405
gem5::ArmISA::MISCREG_MPAMVPMV_EL2
@ MISCREG_MPAMVPMV_EL2
Definition misc.hh:1178
gem5::ArmISA::MISCREG_ICC_SRE_EL1
@ MISCREG_ICC_SRE_EL1
Definition misc.hh:957
gem5::ArmISA::MISCREG_DBGBVR12_EL1
@ MISCREG_DBGBVR12_EL1
Definition misc.hh:500
gem5::ArmISA::MISCREG_PMSWINC_EL0
@ MISCREG_PMSWINC_EL0
Definition misc.hh:800
gem5::ArmISA::MISCREG_SCTLR_EL12
@ MISCREG_SCTLR_EL12
Definition misc.hh:610
gem5::ArmISA::MISCREG_DBGBVR10
@ MISCREG_DBGBVR10
Definition misc.hh:134
gem5::ArmISA::MISCREG_TTBR1_EL1
@ MISCREG_TTBR1_EL1
Definition misc.hh:634
gem5::ArmISA::MISCREG_PMEVTYPER2_EL0
@ MISCREG_PMEVTYPER2_EL0
Definition misc.hh:882
gem5::ArmISA::MISCREG_MAIR1
@ MISCREG_MAIR1
Definition misc.hh:408
gem5::ArmISA::MISCREG_DAIF
@ MISCREG_DAIF
Definition misc.hh:658
gem5::ArmISA::MISCREG_SPSR_ABT_AA64
@ MISCREG_SPSR_ABT_AA64
Definition misc.hh:667
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition misc.hh:109
gem5::ArmISA::MISCREG_SPSR_EL12
@ MISCREG_SPSR_EL12
Definition misc.hh:651
gem5::ArmISA::MISCREG_CNTP_CVAL_EL02
@ MISCREG_CNTP_CVAL_EL02
Definition misc.hh:847
gem5::ArmISA::MISCREG_ACTLR_NS
@ MISCREG_ACTLR_NS
Definition misc.hh:257
gem5::ArmISA::MISCREG_PMINTENSET_EL1
@ MISCREG_PMINTENSET_EL1
Definition misc.hh:794
gem5::ArmISA::MISCREG_ICC_AP1R1_S
@ MISCREG_ICC_AP1R1_S
Definition misc.hh:1053
gem5::ArmISA::MISCREG_PMINTENCLR_EL1
@ MISCREG_PMINTENCLR_EL1
Definition misc.hh:795
gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2
@ MISCREG_CNTHPS_CVAL_EL2
Definition misc.hh:862
gem5::ArmISA::MISCREG_REVIDR
@ MISCREG_REVIDR
Definition misc.hh:228
gem5::ArmISA::MISCREG_DBGBCR9
@ MISCREG_DBGBCR9
Definition misc.hh:149
gem5::ArmISA::MISCREG_MPAMVPM0_EL2
@ MISCREG_MPAMVPM0_EL2
Definition misc.hh:1179
gem5::ArmISA::MISCREG_DL1DATA0_EL1
@ MISCREG_DL1DATA0_EL1
Definition misc.hh:890
gem5::ArmISA::MISCREG_PMCCFILTR
@ MISCREG_PMCCFILTR
Definition misc.hh:391
gem5::ArmISA::MISCREG_ACTLR_EL3
@ MISCREG_ACTLR_EL3
Definition misc.hh:627
gem5::ArmISA::MISCREG_ID_PFR1_EL1
@ MISCREG_ID_PFR1_EL1
Definition misc.hh:573
gem5::ArmISA::MISCREG_DBGBCR11_EL1
@ MISCREG_DBGBCR11_EL1
Definition misc.hh:515
gem5::ArmISA::MISCREG_DBGBCR1_EL1
@ MISCREG_DBGBCR1_EL1
Definition misc.hh:505
gem5::ArmISA::MISCREG_TLBIIPAS2IS
@ MISCREG_TLBIIPAS2IS
Definition misc.hh:357
gem5::ArmISA::MISCREG_DBGBVR11_EL1
@ MISCREG_DBGBVR11_EL1
Definition misc.hh:499
gem5::ArmISA::MISCREG_DBGBCR14
@ MISCREG_DBGBCR14
Definition misc.hh:154
gem5::ArmISA::MISCREG_DBGBCR11
@ MISCREG_DBGBCR11
Definition misc.hh:151
gem5::ArmISA::MISCREG_APDBKeyHi_EL1
@ MISCREG_APDBKeyHi_EL1
Definition misc.hh:912
gem5::ArmISA::MISCREG_TEEHBR32_EL1
@ MISCREG_TEEHBR32_EL1
Definition misc.hh:566
gem5::ArmISA::MISCREG_DBGBVR13
@ MISCREG_DBGBVR13
Definition misc.hh:137
gem5::ArmISA::MISCREG_ID_MMFR3
@ MISCREG_ID_MMFR3
Definition misc.hh:236
gem5::ArmISA::MISCREG_CSSELR_S
@ MISCREG_CSSELR_S
Definition misc.hh:250
gem5::ArmISA::MISCREG_DBGBCR12
@ MISCREG_DBGBCR12
Definition misc.hh:152
gem5::ArmISA::MISCREG_ICH_LRC15
@ MISCREG_ICH_LRC15
Definition misc.hh:1136
gem5::ArmISA::MISCREG_ICC_SRE_EL2
@ MISCREG_ICC_SRE_EL2
Definition misc.hh:964
gem5::ArmISA::MISCREG_ICH_HCR
@ MISCREG_ICH_HCR
Definition misc.hh:1099
gem5::ArmISA::MISCREG_MPAMSM_EL1
@ MISCREG_MPAMSM_EL1
Definition misc.hh:1156
gem5::ArmISA::MISCREG_ICC_IAR0
@ MISCREG_ICC_IAR0
Definition misc.hh:1074
gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1
@ MISCREG_ICC_ASGI1R_EL1
Definition misc.hh:946
gem5::ArmISA::MISCREG_DBGVCR32_EL2
@ MISCREG_DBGVCR32_EL2
Definition misc.hh:556
gem5::ArmISA::MISCREG_DBGWVR9_EL1
@ MISCREG_DBGWVR9_EL1
Definition misc.hh:529
gem5::ArmISA::MISCREG_L2ECTLR
@ MISCREG_L2ECTLR
Definition misc.hh:398
gem5::ArmISA::MISCREG_TCR2_EL12
@ MISCREG_TCR2_EL12
Definition misc.hh:639
gem5::ArmISA::MISCREG_ID_PFR0_EL1
@ MISCREG_ID_PFR0_EL1
Definition misc.hh:572
gem5::ArmISA::MISCREG_ICC_CTLR
@ MISCREG_ICC_CTLR
Definition misc.hh:1065
gem5::ArmISA::MISCREG_ICH_LR2_EL2
@ MISCREG_ICH_LR2_EL2
Definition misc.hh:986
gem5::ArmISA::MISCREG_DL1DATA4_EL1
@ MISCREG_DL1DATA4_EL1
Definition misc.hh:894
gem5::ArmISA::MISCREG_TLBIMVAAIS
@ MISCREG_TLBIMVAAIS
Definition misc.hh:342
gem5::ArmISA::MISCREG_SMPRIMAP_EL2
@ MISCREG_SMPRIMAP_EL2
Definition misc.hh:1150
gem5::ArmISA::MISCREG_ICC_EOIR0
@ MISCREG_ICC_EOIR0
Definition misc.hh:1069
gem5::ArmISA::MISCREG_CNTP_CVAL_NS
@ MISCREG_CNTP_CVAL_NS
Definition misc.hh:450
gem5::ArmISA::MISCREG_OSECCR_EL1
@ MISCREG_OSECCR_EL1
Definition misc.hh:487
gem5::ArmISA::MISCREG_RVBAR_EL1
@ MISCREG_RVBAR_EL1
Definition misc.hh:822
gem5::ArmISA::MISCREG_ISR
@ MISCREG_ISR
Definition misc.hh:426
gem5::ArmISA::MISCREG_DBGWCR7_EL1
@ MISCREG_DBGWCR7_EL1
Definition misc.hh:543
gem5::ArmISA::MISCREG_HAIFSR
@ MISCREG_HAIFSR
Definition misc.hh:299
gem5::ArmISA::MISCREG_TCR2_EL2
@ MISCREG_TCR2_EL2
Definition misc.hh:642
gem5::ArmISA::MISCREG_ID_ISAR5_EL1
@ MISCREG_ID_ISAR5_EL1
Definition misc.hh:586
gem5::ArmISA::MISCREG_CONTEXTIDR
@ MISCREG_CONTEXTIDR
Definition misc.hh:429
gem5::ArmISA::MISCREG_PMCEID1
@ MISCREG_PMCEID1
Definition misc.hh:376
gem5::ArmISA::MISCREG_DBGBVR15_EL1
@ MISCREG_DBGBVR15_EL1
Definition misc.hh:503
gem5::ArmISA::MISCREG_ID_ISAR4_EL1
@ MISCREG_ID_ISAR4_EL1
Definition misc.hh:585
gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2
@ MISCREG_CNTHPS_TVAL_EL2
Definition misc.hh:863
gem5::ArmISA::MISCREG_SCR
@ MISCREG_SCR
Definition misc.hh:261
gem5::ArmISA::MISCREG_DC_IVAC_Xt
@ MISCREG_DC_IVAC_Xt
Definition misc.hh:695
gem5::ArmISA::MISCREG_ICC_AP1R0
@ MISCREG_ICC_AP1R0
Definition misc.hh:1048
gem5::ArmISA::MISCREG_TPIDR2_EL0
@ MISCREG_TPIDR2_EL0
Definition misc.hh:1155
gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1
@ MISCREG_ICC_HPPIR0_EL1
Definition misc.hh:925
gem5::ArmISA::MISCREG_PMCNTENSET
@ MISCREG_PMCNTENSET
Definition misc.hh:370
gem5::ArmISA::MISCREG_DBGBVR7
@ MISCREG_DBGBVR7
Definition misc.hh:131
gem5::ArmISA::MISCREG_ICC_SGI1R_EL1
@ MISCREG_ICC_SGI1R_EL1
Definition misc.hh:945
gem5::ArmISA::MISCREG_DBGWVR9
@ MISCREG_DBGWVR9
Definition misc.hh:165
gem5::ArmISA::MISCREG_ELR_EL2
@ MISCREG_ELR_EL2
Definition misc.hh:664
gem5::ArmISA::MISCREG_HDFGWTR_EL2
@ MISCREG_HDFGWTR_EL2
Definition misc.hh:1167
gem5::ArmISA::MISCREG_MAIR0_S
@ MISCREG_MAIR0_S
Definition misc.hh:404
gem5::ArmISA::MISCREG_ICH_LR5_EL2
@ MISCREG_ICH_LR5_EL2
Definition misc.hh:989
gem5::ArmISA::MISCREG_CONTEXTIDR_EL2
@ MISCREG_CONTEXTIDR_EL2
Definition misc.hh:901
gem5::ArmISA::MISCREG_CNTP_TVAL_S
@ MISCREG_CNTP_TVAL_S
Definition misc.hh:454
gem5::ArmISA::MISCREG_TCR_EL12
@ MISCREG_TCR_EL12
Definition misc.hh:637
gem5::ArmISA::MISCREG_CNTHCTL_EL2
@ MISCREG_CNTHCTL_EL2
Definition misc.hh:857
gem5::ArmISA::MISCREG_DBGBXVR6
@ MISCREG_DBGBXVR6
Definition misc.hh:195
gem5::ArmISA::MISCREG_DBGBXVR0
@ MISCREG_DBGBXVR0
Definition misc.hh:189
gem5::ArmISA::MISCREG_TEEHBR
@ MISCREG_TEEHBR
Definition misc.hh:218
gem5::ArmISA::MISCREG_ERXMISC1_EL1
@ MISCREG_ERXMISC1_EL1
Definition misc.hh:1213
gem5::ArmISA::MISCREG_MDSCR_EL1
@ MISCREG_MDSCR_EL1
Definition misc.hh:485
gem5::ArmISA::MISCREG_AMAIR1_NS
@ MISCREG_AMAIR1_NS
Definition misc.hh:415
gem5::ArmISA::MISCREG_DL1DATA2
@ MISCREG_DL1DATA2
Definition misc.hh:471
gem5::ArmISA::MISCREG_DBGWCR2_EL1
@ MISCREG_DBGWCR2_EL1
Definition misc.hh:538
gem5::ArmISA::MISCREG_ID_MMFR4_EL1
@ MISCREG_ID_MMFR4_EL1
Definition misc.hh:580
gem5::ArmISA::MISCREG_PAR_S
@ MISCREG_PAR_S
Definition misc.hh:314
gem5::ArmISA::MISCREG_DBGBCR12_EL1
@ MISCREG_DBGBCR12_EL1
Definition misc.hh:516
gem5::ArmISA::MISCREG_ID_DFR0
@ MISCREG_ID_DFR0
Definition misc.hh:231
gem5::ArmISA::MISCREG_CNTP_CTL_S
@ MISCREG_CNTP_CTL_S
Definition misc.hh:448
gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS
@ MISCREG_ICC_AP1R1_EL1_NS
Definition misc.hh:935
gem5::ArmISA::MISCREG_TTBR1_EL2
@ MISCREG_TTBR1_EL2
Definition misc.hh:904
gem5::ArmISA::MISCREG_ICC_SGI1R
@ MISCREG_ICC_SGI1R
Definition misc.hh:1086
gem5::ArmISA::MISCREG_DBGDTRTXint
@ MISCREG_DBGDTRTXint
Definition misc.hh:116
gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1
@ MISCREG_ID_AA64MMFR0_EL1
Definition misc.hh:599
gem5::ArmISA::MISCREG_HPFAR
@ MISCREG_HPFAR
Definition misc.hh:309
gem5::ArmISA::MISCREG_ICC_PMR
@ MISCREG_ICC_PMR
Definition misc.hh:1083
gem5::ArmISA::MISCREG_ICH_LRC5
@ MISCREG_ICH_LRC5
Definition misc.hh:1126
gem5::ArmISA::MISCREG_TPIDRPRW_S
@ MISCREG_TPIDRPRW_S
Definition misc.hh:440
gem5::ArmISA::MISCREG_ICH_LR6
@ MISCREG_ICH_LR6
Definition misc.hh:1111
gem5::ArmISA::MISCREG_TLBIMVAHIS
@ MISCREG_TLBIMVAHIS
Definition misc.hh:360
gem5::ArmISA::MISCREG_IC_IALLU
@ MISCREG_IC_IALLU
Definition misc.hh:694
gem5::ArmISA::MISCREG_ICC_AP1R2
@ MISCREG_ICC_AP1R2
Definition misc.hh:1054
gem5::ArmISA::MISCREG_DBGWCR9
@ MISCREG_DBGWCR9
Definition misc.hh:181
gem5::ArmISA::MISCREG_APIAKeyHi_EL1
@ MISCREG_APIAKeyHi_EL1
Definition misc.hh:916
gem5::ArmISA::MISCREG_MPAMIDR_EL1
@ MISCREG_MPAMIDR_EL1
Definition misc.hh:1171
gem5::ArmISA::MISCREG_SPSR_EL3
@ MISCREG_SPSR_EL3
Definition misc.hh:670
gem5::ArmISA::MISCREG_APDAKeyLo_EL1
@ MISCREG_APDAKeyLo_EL1
Definition misc.hh:911
gem5::ArmISA::MISCREG_AT_S1E1R_Xt
@ MISCREG_AT_S1E1R_Xt
Definition misc.hh:697
gem5::ArmISA::MISCREG_ICH_AP1R2_EL2
@ MISCREG_ICH_AP1R2_EL2
Definition misc.hh:976
gem5::ArmISA::MISCREG_DTLBIALL
@ MISCREG_DTLBIALL
Definition misc.hh:348
gem5::ArmISA::MISCREG_TLBIALLIS
@ MISCREG_TLBIALLIS
Definition misc.hh:339
gem5::ArmISA::MISCREG_AMAIR_EL1
@ MISCREG_AMAIR_EL1
Definition misc.hh:812
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS
@ MISCREG_ICC_CTLR_EL1_NS
Definition misc.hh:955
gem5::ArmISA::MISCREG_ICC_CTLR_S
@ MISCREG_ICC_CTLR_S
Definition misc.hh:1067
gem5::ArmISA::MISCREG_ESR_EL3
@ MISCREG_ESR_EL3
Definition misc.hh:686
gem5::ArmISA::MISCREG_IL1DATA0
@ MISCREG_IL1DATA0
Definition misc.hh:465
gem5::ArmISA::MISCREG_ATS1HW
@ MISCREG_ATS1HW
Definition misc.hh:338
gem5::ArmISA::MISCREG_ICH_VTR
@ MISCREG_ICH_VTR
Definition misc.hh:1100
gem5::ArmISA::MISCREG_VBAR_S
@ MISCREG_VBAR_S
Definition misc.hh:423
gem5::ArmISA::MISCREG_ICH_AP0R1_EL2
@ MISCREG_ICH_AP0R1_EL2
Definition misc.hh:971
gem5::ArmISA::MISCREG_AT_S1E3R_Xt
@ MISCREG_AT_S1E3R_Xt
Definition misc.hh:714
gem5::ArmISA::MISCREG_ICC_SRE
@ MISCREG_ICC_SRE
Definition misc.hh:1087
gem5::ArmISA::MISCREG_DC_ZVA_Xt
@ MISCREG_DC_ZVA_Xt
Definition misc.hh:703
gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2
@ MISCREG_CNTHVS_TVAL_EL2
Definition misc.hh:870
gem5::ArmISA::MISCREG_ATS1CPR
@ MISCREG_ATS1CPR
Definition misc.hh:322
gem5::ArmISA::MISCREG_TLBIASID
@ MISCREG_TLBIASID
Definition misc.hh:353
gem5::ArmISA::MISCREG_ICH_LRC12
@ MISCREG_ICH_LRC12
Definition misc.hh:1133
gem5::ArmISA::MISCREG_DBGBXVR10
@ MISCREG_DBGBXVR10
Definition misc.hh:199
gem5::ArmISA::MISCREG_APGAKeyLo_EL1
@ MISCREG_APGAKeyLo_EL1
Definition misc.hh:915
gem5::ArmISA::MISCREG_ITLBIMVA
@ MISCREG_ITLBIMVA
Definition misc.hh:346
gem5::ArmISA::MISCREG_NZCV
@ MISCREG_NZCV
Definition misc.hh:657
gem5::ArmISA::MISCREG_HTTBR
@ MISCREG_HTTBR
Definition misc.hh:477
gem5::ArmISA::MISCREG_IFSR32_EL2
@ MISCREG_IFSR32_EL2
Definition misc.hh:679
gem5::ArmISA::MISCREG_ICH_LRC9
@ MISCREG_ICH_LRC9
Definition misc.hh:1130
gem5::ArmISA::MISCREG_SPSR_EL1
@ MISCREG_SPSR_EL1
Definition misc.hh:650
gem5::ArmISA::MISCREG_APIBKeyHi_EL1
@ MISCREG_APIBKeyHi_EL1
Definition misc.hh:918
gem5::ArmISA::MISCREG_FAR_EL12
@ MISCREG_FAR_EL12
Definition misc.hh:688
gem5::ArmISA::MISCREG_MAIR0_NS
@ MISCREG_MAIR0_NS
Definition misc.hh:403
gem5::ArmISA::MISCREG_CP15DSB
@ MISCREG_CP15DSB
Definition misc.hh:332
gem5::ArmISA::MISCREG_ICH_LR13_EL2
@ MISCREG_ICH_LR13_EL2
Definition misc.hh:997
gem5::ArmISA::MISCREG_ICC_CTLR_EL3
@ MISCREG_ICC_CTLR_EL3
Definition misc.hh:965
gem5::ArmISA::MISCREG_DBGDCCINT
@ MISCREG_DBGDCCINT
Definition misc.hh:115
gem5::ArmISA::MISCREG_ICC_CTLR_EL1
@ MISCREG_ICC_CTLR_EL1
Definition misc.hh:954
gem5::ArmISA::MISCREG_TLBIALLNSNHIS
@ MISCREG_TLBIALLNSNHIS
Definition misc.hh:361
gem5::ArmISA::MISCREG_CNTP_CVAL_EL0
@ MISCREG_CNTP_CVAL_EL0
Definition misc.hh:841
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition misc.hh:619
gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2
@ MISCREG_CNTHVS_CVAL_EL2
Definition misc.hh:869
gem5::ArmISA::MISCREG_SMCR_EL2
@ MISCREG_SMCR_EL2
Definition misc.hh:1152
gem5::ArmISA::MISCREG_L2ACTLR_EL1
@ MISCREG_L2ACTLR_EL1
Definition misc.hh:895
gem5::ArmISA::MISCREG_DCIMVAC
@ MISCREG_DCIMVAC
Definition misc.hh:320
gem5::ArmISA::MISCREG_ATS1CPW
@ MISCREG_ATS1CPW
Definition misc.hh:323
gem5::ArmISA::MISCREG_TTBR1
@ MISCREG_TTBR1
Definition misc.hh:275
gem5::ArmISA::MISCREG_AT_S12E0R_Xt
@ MISCREG_AT_S12E0R_Xt
Definition misc.hh:712
gem5::ArmISA::MISCREG_ICH_AP1R0
@ MISCREG_ICH_AP1R0
Definition misc.hh:1095
gem5::ArmISA::MISCREG_MPIDR
@ MISCREG_MPIDR
Definition misc.hh:227
gem5::ArmISA::MISCREG_ICC_AP0R2
@ MISCREG_ICC_AP0R2
Definition misc.hh:1046
gem5::ArmISA::MISCREG_DBGCLAIMSET
@ MISCREG_DBGCLAIMSET
Definition misc.hh:210
gem5::ArmISA::MISCREG_TLBIMVALHIS
@ MISCREG_TLBIMVALHIS
Definition misc.hh:362
gem5::ArmISA::MISCREG_MPAMVPM3_EL2
@ MISCREG_MPAMVPM3_EL2
Definition misc.hh:1182
gem5::ArmISA::MISCREG_PRRR_NS
@ MISCREG_PRRR_NS
Definition misc.hh:400
gem5::ArmISA::MISCREG_ZCR_EL1
@ MISCREG_ZCR_EL1
Definition misc.hh:1143
gem5::ArmISA::MISCREG_PMCEID0_EL0
@ MISCREG_PMCEID0_EL0
Definition misc.hh:802
gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition misc.hh:906
gem5::ArmISA::MISCREG_ICC_DIR_EL1
@ MISCREG_ICC_DIR_EL1
Definition misc.hh:943
gem5::ArmISA::MISCREG_SDER32_EL3
@ MISCREG_SDER32_EL3
Definition misc.hh:629
gem5::ArmISA::MISCREG_TPIDR_EL0
@ MISCREG_TPIDR_EL0
Definition misc.hh:832
gem5::ArmISA::MISCREG_DBGDTRTXext
@ MISCREG_DBGDTRTXext
Definition misc.hh:122
gem5::ArmISA::MISCREG_DBGOSECCR
@ MISCREG_DBGOSECCR
Definition misc.hh:123
gem5::ArmISA::MISCREG_ICC_SRE_EL3
@ MISCREG_ICC_SRE_EL3
Definition misc.hh:966
gem5::ArmISA::MISCREG_VTCR_EL2
@ MISCREG_VTCR_EL2
Definition misc.hh:644
gem5::ArmISA::MISCREG_DBGWCR3
@ MISCREG_DBGWCR3
Definition misc.hh:175
gem5::ArmISA::MISCREG_ELR_EL3
@ MISCREG_ELR_EL3
Definition misc.hh:671
gem5::ArmISA::MISCREG_ITLBIASID
@ MISCREG_ITLBIASID
Definition misc.hh:347
gem5::ArmISA::MISCREG_ICH_LR12
@ MISCREG_ICH_LR12
Definition misc.hh:1117
gem5::ArmISA::MISCREG_DBGWCR11
@ MISCREG_DBGWCR11
Definition misc.hh:183
gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1
@ MISCREG_DBGCLAIMSET_EL1
Definition misc.hh:562
gem5::ArmISA::MISCREG_ICH_LR3_EL2
@ MISCREG_ICH_LR3_EL2
Definition misc.hh:987
gem5::ArmISA::MISCREG_VTTBR
@ MISCREG_VTTBR
Definition misc.hh:478
gem5::ArmISA::MISCREG_MDDTRRX_EL0
@ MISCREG_MDDTRRX_EL0
Definition misc.hh:555
gem5::ArmISA::MISCREG_HDFGRTR_EL2
@ MISCREG_HDFGRTR_EL2
Definition misc.hh:1166
gem5::ArmISA::MISCREG_CNTVOFF_EL2
@ MISCREG_CNTVOFF_EL2
Definition misc.hh:872
gem5::ArmISA::MISCREG_AIFSR
@ MISCREG_AIFSR
Definition misc.hh:295
gem5::ArmISA::MISCREG_DBGWCR6
@ MISCREG_DBGWCR6
Definition misc.hh:178
gem5::ArmISA::MISCREG_ICH_AP1R1_EL2
@ MISCREG_ICH_AP1R1_EL2
Definition misc.hh:975
gem5::ArmISA::MISCREG_VPIDR
@ MISCREG_VPIDR
Definition misc.hh:251
gem5::ArmISA::MISCREG_ICH_AP1R2
@ MISCREG_ICH_AP1R2
Definition misc.hh:1097
gem5::ArmISA::MISCREG_BPIALLIS
@ MISCREG_BPIALLIS
Definition misc.hh:311
gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS
@ MISCREG_ICC_AP1R0_EL1_NS
Definition misc.hh:932
gem5::ArmISA::MISCREG_DBGWCR15
@ MISCREG_DBGWCR15
Definition misc.hh:187
gem5::ArmISA::MISCREG_CNTHCTL
@ MISCREG_CNTHCTL
Definition misc.hh:459
gem5::ArmISA::MISCREG_ICC_EOIR0_EL1
@ MISCREG_ICC_EOIR0_EL1
Definition misc.hh:924
gem5::ArmISA::MISCREG_TTBR1_NS
@ MISCREG_TTBR1_NS
Definition misc.hh:276
gem5::ArmISA::MISCREG_FAR_EL3
@ MISCREG_FAR_EL3
Definition misc.hh:691
gem5::ArmISA::MISCREG_ACTLR_EL1
@ MISCREG_ACTLR_EL1
Definition misc.hh:613
gem5::ArmISA::MISCREG_ICH_LR8_EL2
@ MISCREG_ICH_LR8_EL2
Definition misc.hh:992
gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2
@ MISCREG_CNTHPS_CTL_EL2
Definition misc.hh:861
gem5::ArmISA::MISCREG_DBGBVR3_EL1
@ MISCREG_DBGBVR3_EL1
Definition misc.hh:491
gem5::ArmISA::MISCREG_DBGVCR
@ MISCREG_DBGVCR
Definition misc.hh:119
gem5::ArmISA::MISCREG_MDCCINT_EL1
@ MISCREG_MDCCINT_EL1
Definition misc.hh:483
gem5::ArmISA::MISCREG_DBGBVR6_EL1
@ MISCREG_DBGBVR6_EL1
Definition misc.hh:494
gem5::ArmISA::MISCREG_DBGWCR9_EL1
@ MISCREG_DBGWCR9_EL1
Definition misc.hh:545
gem5::ArmISA::MISCREG_ICC_IAR1
@ MISCREG_ICC_IAR1
Definition misc.hh:1075
gem5::ArmISA::MISCREG_IL1DATA3_EL1
@ MISCREG_IL1DATA3_EL1
Definition misc.hh:889
gem5::ArmISA::MISCREG_ICH_LR15
@ MISCREG_ICH_LR15
Definition misc.hh:1120
gem5::ArmISA::MISCREG_DC_CISW_Xt
@ MISCREG_DC_CISW_Xt
Definition misc.hh:702
gem5::ArmISA::MISCREG_ICH_AP0R0
@ MISCREG_ICH_AP0R0
Definition misc.hh:1091
gem5::ArmISA::MISCREG_VBAR_EL2
@ MISCREG_VBAR_EL2
Definition misc.hh:824
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S
@ MISCREG_ICC_AP1R2_EL1_S
Definition misc.hh:939
gem5::ArmISA::MISCREG_DBGBCR7_EL1
@ MISCREG_DBGBCR7_EL1
Definition misc.hh:511
gem5::ArmISA::MISCREG_ICC_EOIR1_EL1
@ MISCREG_ICC_EOIR1_EL1
Definition misc.hh:949
gem5::ArmISA::MISCREG_ICIMVAU
@ MISCREG_ICIMVAU
Definition misc.hh:316
gem5::ArmISA::MISCREG_ICH_AP0R3_EL2
@ MISCREG_ICH_AP0R3_EL2
Definition misc.hh:973
gem5::ArmISA::MISCREG_DBGWCR14
@ MISCREG_DBGWCR14
Definition misc.hh:186
gem5::ArmISA::MISCREG_DBGBCR5_EL1
@ MISCREG_DBGBCR5_EL1
Definition misc.hh:509
gem5::ArmISA::MISCREG_L2ACTLR
@ MISCREG_L2ACTLR
Definition misc.hh:475
gem5::ArmISA::MISCREG_ACTLR_EL2
@ MISCREG_ACTLR_EL2
Definition misc.hh:618
gem5::ArmISA::MISCREG_CPUMERRSR_EL1
@ MISCREG_CPUMERRSR_EL1
Definition misc.hh:898
gem5::ArmISA::MISCREG_IFAR_NS
@ MISCREG_IFAR_NS
Definition misc.hh:305
gem5::ArmISA::MISCREG_DBGWVR15_EL1
@ MISCREG_DBGWVR15_EL1
Definition misc.hh:535
gem5::ArmISA::MISCREG_CTR
@ MISCREG_CTR
Definition misc.hh:224
gem5::ArmISA::MISCREG_HPFAR_EL2
@ MISCREG_HPFAR_EL2
Definition misc.hh:690
gem5::ArmISA::MISCREG_TPIDRURW
@ MISCREG_TPIDRURW
Definition misc.hh:432
gem5::ArmISA::MISCREG_DBGBXVR11
@ MISCREG_DBGBXVR11
Definition misc.hh:200
gem5::ArmISA::MISCREG_ICH_LRC6
@ MISCREG_ICH_LRC6
Definition misc.hh:1127
gem5::ArmISA::MISCREG_ICH_LR1_EL2
@ MISCREG_ICH_LR1_EL2
Definition misc.hh:985
gem5::ArmISA::MISCREG_CLIDR
@ MISCREG_CLIDR
Definition misc.hh:246
gem5::ArmISA::MISCREG_SCTLR_S
@ MISCREG_SCTLR_S
Definition misc.hh:255
gem5::ArmISA::MISCREG_PMEVCNTR4
@ MISCREG_PMEVCNTR4
Definition misc.hh:383
gem5::ArmISA::MISCREG_DBGDTRRXint
@ MISCREG_DBGDTRRXint
Definition misc.hh:117
gem5::ArmISA::MISCREG_ICH_AP0R1
@ MISCREG_ICH_AP0R1
Definition misc.hh:1092
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition misc.hh:621
gem5::ArmISA::MISCREG_VBAR
@ MISCREG_VBAR
Definition misc.hh:421
gem5::ArmISA::MISCREG_IFSR
@ MISCREG_IFSR
Definition misc.hh:289
gem5::ArmISA::MISCREG_PMSELR
@ MISCREG_PMSELR
Definition misc.hh:374
gem5::ArmISA::MISCREG_ICIALLUIS
@ MISCREG_ICIALLUIS
Definition misc.hh:310
gem5::ArmISA::MISCREG_HACTLR
@ MISCREG_HACTLR
Definition misc.hh:265
gem5::ArmISA::MISCREG_ID_MMFR0_EL1
@ MISCREG_ID_MMFR0_EL1
Definition misc.hh:576
gem5::ArmISA::MISCREG_AMAIR1
@ MISCREG_AMAIR1
Definition misc.hh:414
gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2
@ MISCREG_CNTHV_TVAL_EL2
Definition misc.hh:867
gem5::ArmISA::MISCREG_VBAR_EL1
@ MISCREG_VBAR_EL1
Definition misc.hh:820
gem5::ArmISA::MISCREG_MIDR
@ MISCREG_MIDR
Definition misc.hh:223
gem5::ArmISA::MISCREG_ICH_EISR
@ MISCREG_ICH_EISR
Definition misc.hh:1102
gem5::ArmISA::MISCREG_PMEVCNTR2_EL0
@ MISCREG_PMEVCNTR2_EL0
Definition misc.hh:876
gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1
@ MISCREG_CNTPS_CVAL_EL1
Definition misc.hh:855
gem5::ArmISA::MISCREG_HTCR
@ MISCREG_HTCR
Definition misc.hh:281
gem5::ArmISA::MISCREG_AMAIR_EL2
@ MISCREG_AMAIR_EL2
Definition misc.hh:815
gem5::ArmISA::MISCREG_ICC_BPR0
@ MISCREG_ICC_BPR0
Definition misc.hh:1061
gem5::ArmISA::MISCREG_TLBIMVAIS
@ MISCREG_TLBIMVAIS
Definition misc.hh:340
gem5::ArmISA::MISCREG_TTBR1_S
@ MISCREG_TTBR1_S
Definition misc.hh:277
gem5::ArmISA::MISCREG_ICH_LR2
@ MISCREG_ICH_LR2
Definition misc.hh:1107
gem5::ArmISA::MISCREG_HVBAR
@ MISCREG_HVBAR
Definition misc.hh:427
gem5::ArmISA::MISCREG_MPAM0_EL1
@ MISCREG_MPAM0_EL1
Definition misc.hh:1172
gem5::ArmISA::MISCREG_JIDR
@ MISCREG_JIDR
Definition misc.hh:217
gem5::ArmISA::MISCREG_DC_ISW_Xt
@ MISCREG_DC_ISW_Xt
Definition misc.hh:696
gem5::ArmISA::MISCREG_L2CTLR
@ MISCREG_L2CTLR
Definition misc.hh:397
gem5::ArmISA::MISCREG_DBGPRCR
@ MISCREG_DBGPRCR
Definition misc.hh:208
gem5::ArmISA::MISCREG_DBGWVR10
@ MISCREG_DBGWVR10
Definition misc.hh:166
gem5::ArmISA::MISCREG_CNTP_CTL
@ MISCREG_CNTP_CTL
Definition misc.hh:446
gem5::ArmISA::MISCREG_TTBR0_EL3
@ MISCREG_TTBR0_EL3
Definition misc.hh:647
gem5::ArmISA::MISCREG_ICC_AP0R0_EL1
@ MISCREG_ICC_AP0R0_EL1
Definition misc.hh:927
gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1
@ MISCREG_ICC_IGRPEN0_EL1
Definition misc.hh:960
gem5::ArmISA::MISCREG_DBGWCR0_EL1
@ MISCREG_DBGWCR0_EL1
Definition misc.hh:536
gem5::ArmISA::MISCREG_ICC_AP1R2_S
@ MISCREG_ICC_AP1R2_S
Definition misc.hh:1056
gem5::ArmISA::MISCREG_DCZID_EL0
@ MISCREG_DCZID_EL0
Definition misc.hh:606
gem5::ArmISA::MISCREG_ICH_LRC13
@ MISCREG_ICH_LRC13
Definition misc.hh:1134
gem5::ArmISA::MISCREG_TLBIALLH
@ MISCREG_TLBIALLH
Definition misc.hh:365
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS
@ MISCREG_ICC_AP1R2_EL1_NS
Definition misc.hh:938
gem5::ArmISA::MISCREG_ICH_VMCR_EL2
@ MISCREG_ICH_VMCR_EL2
Definition misc.hh:983
gem5::ArmISA::MISCREG_ATS12NSOPW
@ MISCREG_ATS12NSOPW
Definition misc.hh:327
gem5::ArmISA::MISCREG_ICH_LRC14
@ MISCREG_ICH_LRC14
Definition misc.hh:1135
gem5::ArmISA::MISCREG_DACR_NS
@ MISCREG_DACR_NS
Definition misc.hh:284
gem5::ArmISA::MISCREG_TLBIMVAH
@ MISCREG_TLBIMVAH
Definition misc.hh:366
gem5::ArmISA::MISCREG_ICC_EOIR1
@ MISCREG_ICC_EOIR1
Definition misc.hh:1070
gem5::ArmISA::MISCREG_DBGWVR12
@ MISCREG_DBGWVR12
Definition misc.hh:168
gem5::ArmISA::MISCREG_ISR_EL1
@ MISCREG_ISR_EL1
Definition misc.hh:823
gem5::ArmISA::MISCREG_ICC_SGI0R_EL1
@ MISCREG_ICC_SGI0R_EL1
Definition misc.hh:947
gem5::ArmISA::MISCREG_HACR_EL2
@ MISCREG_HACR_EL2
Definition misc.hh:624
gem5::ArmISA::MISCREG_DBGBCR4
@ MISCREG_DBGBCR4
Definition misc.hh:144
gem5::ArmISA::MISCREG_OSDTRTX_EL1
@ MISCREG_OSDTRTX_EL1
Definition misc.hh:486
gem5::ArmISA::MISCREG_CNTVOFF
@ MISCREG_CNTVOFF
Definition misc.hh:463
gem5::ArmISA::MISCREG_ICH_LR12_EL2
@ MISCREG_ICH_LR12_EL2
Definition misc.hh:996
gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1
@ MISCREG_DBGCLAIMCLR_EL1
Definition misc.hh:563
gem5::ArmISA::MISCREG_ICH_LRC3
@ MISCREG_ICH_LRC3
Definition misc.hh:1124
gem5::ArmISA::MISCREG_AT_S1E0W_Xt
@ MISCREG_AT_S1E0W_Xt
Definition misc.hh:700
gem5::ArmISA::MISCREG_AMAIR0_S
@ MISCREG_AMAIR0_S
Definition misc.hh:413
gem5::ArmISA::MISCREG_DCCSW
@ MISCREG_DCCSW
Definition misc.hh:331
gem5::ArmISA::MISCREG_AT_S12E1R_Xt
@ MISCREG_AT_S12E1R_Xt
Definition misc.hh:710
gem5::ArmISA::MISCREG_DBGBXVR2
@ MISCREG_DBGBXVR2
Definition misc.hh:191
gem5::ArmISA::MISCREG_TLBTR
@ MISCREG_TLBTR
Definition misc.hh:226
gem5::ArmISA::MISCREG_DBGWVR0
@ MISCREG_DBGWVR0
Definition misc.hh:156
gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1
@ MISCREG_ID_AA64AFR1_EL1
Definition misc.hh:596
gem5::ArmISA::MISCREG_DBGWCR12
@ MISCREG_DBGWCR12
Definition misc.hh:184
gem5::ArmISA::MISCREG_HAFGRTR_EL2
@ MISCREG_HAFGRTR_EL2
Definition misc.hh:1168
gem5::ArmISA::MISCREG_AFSR0_EL12
@ MISCREG_AFSR0_EL12
Definition misc.hh:674
gem5::ArmISA::MISCREG_DCCMVAU
@ MISCREG_DCCMVAU
Definition misc.hh:334
gem5::ArmISA::MISCREG_IL1DATA2_EL1
@ MISCREG_IL1DATA2_EL1
Definition misc.hh:888
gem5::ArmISA::MISCREG_ICH_LR3
@ MISCREG_ICH_LR3
Definition misc.hh:1108
gem5::ArmISA::MISCREG_DBGBVR14_EL1
@ MISCREG_DBGBVR14_EL1
Definition misc.hh:502
gem5::ArmISA::MISCREG_DTLBIASID
@ MISCREG_DTLBIASID
Definition misc.hh:350
gem5::ArmISA::MISCREG_TLBINEEDSYNC
@ MISCREG_TLBINEEDSYNC
Definition misc.hh:110
gem5::ArmISA::MISCREG_ID_ISAR6_EL1
@ MISCREG_ID_ISAR6_EL1
Definition misc.hh:587
gem5::ArmISA::MISCREG_ELR_EL1
@ MISCREG_ELR_EL1
Definition misc.hh:652
gem5::ArmISA::MISCREG_AMAIR_EL12
@ MISCREG_AMAIR_EL12
Definition misc.hh:813
gem5::ArmISA::MISCREG_PMXEVCNTR
@ MISCREG_PMXEVCNTR
Definition misc.hh:392
gem5::ArmISA::MISCREG_DBGBVR1
@ MISCREG_DBGBVR1
Definition misc.hh:125
gem5::ArmISA::MISCREG_CNTHP_CTL
@ MISCREG_CNTHP_CTL
Definition misc.hh:460
gem5::ArmISA::MISCREG_DBGWCR15_EL1
@ MISCREG_DBGWCR15_EL1
Definition misc.hh:551
gem5::ArmISA::MISCREG_PMCEID0
@ MISCREG_PMCEID0
Definition misc.hh:375
gem5::ArmISA::MISCREG_ICH_LR9
@ MISCREG_ICH_LR9
Definition misc.hh:1114
gem5::ArmISA::MISCREG_TPIDR_EL2
@ MISCREG_TPIDR_EL2
Definition misc.hh:834
gem5::ArmISA::MISCREG_DBGBXVR14
@ MISCREG_DBGBXVR14
Definition misc.hh:203
gem5::ArmISA::MISCREG_ICC_SRE_NS
@ MISCREG_ICC_SRE_NS
Definition misc.hh:1088
gem5::ArmISA::MISCREG_TCR2_EL1
@ MISCREG_TCR2_EL1
Definition misc.hh:638
gem5::ArmISA::MISCREG_DFSR_NS
@ MISCREG_DFSR_NS
Definition misc.hh:287
gem5::ArmISA::MISCREG_ID_PFR1
@ MISCREG_ID_PFR1
Definition misc.hh:230
gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2
@ MISCREG_CNTHP_CVAL_EL2
Definition misc.hh:859
gem5::ArmISA::MISCREG_CNTV_TVAL_EL0
@ MISCREG_CNTV_TVAL_EL0
Definition misc.hh:845
gem5::ArmISA::MISCREG_HFGWTR_EL2
@ MISCREG_HFGWTR_EL2
Definition misc.hh:1165
gem5::ArmISA::MISCREG_MPAM2_EL2
@ MISCREG_MPAM2_EL2
Definition misc.hh:1174
gem5::ArmISA::MISCREG_ZCR_EL3
@ MISCREG_ZCR_EL3
Definition misc.hh:1140
gem5::ArmISA::MISCREG_DBGBCR2
@ MISCREG_DBGBCR2
Definition misc.hh:142
gem5::ArmISA::MISCREG_DBGWCR14_EL1
@ MISCREG_DBGWCR14_EL1
Definition misc.hh:550
gem5::ArmISA::MISCREG_SPSR_MON
@ MISCREG_SPSR_MON
Definition misc.hh:84
gem5::ArmISA::MISCREG_DCCIMVAC
@ MISCREG_DCCIMVAC
Definition misc.hh:335
gem5::ArmISA::MISCREG_L2CTLR_EL1
@ MISCREG_L2CTLR_EL1
Definition misc.hh:818
gem5::ArmISA::MISCREG_VTCR
@ MISCREG_VTCR
Definition misc.hh:282
gem5::ArmISA::MISCREG_FPSCR
@ MISCREG_FPSCR
Definition misc.hh:90
gem5::ArmISA::MISCREG_TTBR0
@ MISCREG_TTBR0
Definition misc.hh:272
gem5::ArmISA::MISCREG_DBGWVR14_EL1
@ MISCREG_DBGWVR14_EL1
Definition misc.hh:534
gem5::ArmISA::MISCREG_DBGWVR1
@ MISCREG_DBGWVR1
Definition misc.hh:157
gem5::ArmISA::MISCREG_DACR
@ MISCREG_DACR
Definition misc.hh:283
gem5::ArmISA::MISCREG_TTBR0_EL2
@ MISCREG_TTBR0_EL2
Definition misc.hh:640
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition misc.hh:264
gem5::ArmISA::MISCREG_SCTLR_NS
@ MISCREG_SCTLR_NS
Definition misc.hh:254
gem5::ArmISA::MISCREG_DBGWVR2_EL1
@ MISCREG_DBGWVR2_EL1
Definition misc.hh:522
gem5::ArmISA::MISCREG_PMEVTYPER4
@ MISCREG_PMEVTYPER4
Definition misc.hh:389
gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1
@ MISCREG_ICC_IGRPEN1_EL1
Definition misc.hh:961
gem5::ArmISA::MISCREG_ICC_AP0R0
@ MISCREG_ICC_AP0R0
Definition misc.hh:1044
gem5::ArmISA::MISCREG_ACTLR_S
@ MISCREG_ACTLR_S
Definition misc.hh:258
gem5::ArmISA::MISCREG_BPIMVA
@ MISCREG_BPIMVA
Definition misc.hh:319
gem5::ArmISA::MISCREG_PMINTENCLR
@ MISCREG_PMINTENCLR
Definition misc.hh:395
gem5::ArmISA::MISCREG_PMCNTENCLR_EL0
@ MISCREG_PMCNTENCLR_EL0
Definition misc.hh:798
gem5::ArmISA::MISCREG_MPAMVPM6_EL2
@ MISCREG_MPAMVPM6_EL2
Definition misc.hh:1185
gem5::ArmISA::MISCREG_IL1DATA2
@ MISCREG_IL1DATA2
Definition misc.hh:467
gem5::ArmISA::MISCREG_TTBR0_EL1
@ MISCREG_TTBR0_EL1
Definition misc.hh:632
gem5::ArmISA::MISCREG_ICC_HPPIR0
@ MISCREG_ICC_HPPIR0
Definition misc.hh:1071
gem5::ArmISA::MISCREG_JOSCR
@ MISCREG_JOSCR
Definition misc.hh:219
gem5::ArmISA::MISCREG_ICIALLU
@ MISCREG_ICIALLU
Definition misc.hh:315
gem5::ArmISA::MISCREG_IL1DATA3
@ MISCREG_IL1DATA3
Definition misc.hh:468
gem5::ArmISA::MISCREG_CNTP_CTL_NS
@ MISCREG_CNTP_CTL_NS
Definition misc.hh:447
gem5::ArmISA::MISCREG_HCRX_EL2
@ MISCREG_HCRX_EL2
Definition misc.hh:620
gem5::ArmISA::MISCREG_PMEVCNTR5_EL0
@ MISCREG_PMEVCNTR5_EL0
Definition misc.hh:879
gem5::ArmISA::MISCREG_TLBIALL
@ MISCREG_TLBIALL
Definition misc.hh:351
gem5::ArmISA::MISCREG_ICC_AP0R2_EL1
@ MISCREG_ICC_AP0R2_EL1
Definition misc.hh:929
gem5::ArmISA::MISCREG_SCTLR_EL3
@ MISCREG_SCTLR_EL3
Definition misc.hh:625
gem5::ArmISA::MISCREG_CNTP_TVAL_EL0
@ MISCREG_CNTP_TVAL_EL0
Definition misc.hh:842
gem5::ArmISA::MISCREG_FPSCR_QC
@ MISCREG_FPSCR_QC
Definition misc.hh:99
gem5::ArmISA::MISCREG_CURRENTEL
@ MISCREG_CURRENTEL
Definition misc.hh:656
gem5::ArmISA::MISCREG_DBGBVR13_EL1
@ MISCREG_DBGBVR13_EL1
Definition misc.hh:501
gem5::ArmISA::MISCREG_DBGWVR6
@ MISCREG_DBGWVR6
Definition misc.hh:162
gem5::ArmISA::MISCREG_VSESR_EL2
@ MISCREG_VSESR_EL2
Definition misc.hh:1215
gem5::ArmISA::MISCREG_DBGAUTHSTATUS
@ MISCREG_DBGAUTHSTATUS
Definition misc.hh:212
gem5::ArmISA::MISCREG_ICC_SGI0R
@ MISCREG_ICC_SGI0R
Definition misc.hh:1085
gem5::ArmISA::MISCREG_PMEVCNTR1
@ MISCREG_PMEVCNTR1
Definition misc.hh:380
gem5::ArmISA::MISCREG_MVFR0_EL1
@ MISCREG_MVFR0_EL1
Definition misc.hh:588
gem5::ArmISA::MISCREG_ICH_AP0R0_EL2
@ MISCREG_ICH_AP0R0_EL2
Definition misc.hh:970
gem5::ArmISA::MISCREG_ID_ISAR1
@ MISCREG_ID_ISAR1
Definition misc.hh:239
gem5::ArmISA::MISCREG_DBGBCR0
@ MISCREG_DBGBCR0
Definition misc.hh:140
gem5::ArmISA::MISCREG_ICH_MISR_EL2
@ MISCREG_ICH_MISR_EL2
Definition misc.hh:980
gem5::ArmISA::MISCREG_TTBCR_S
@ MISCREG_TTBCR_S
Definition misc.hh:280
gem5::ArmISA::MISCREG_IFSR_S
@ MISCREG_IFSR_S
Definition misc.hh:291
gem5::ArmISA::MISCREG_PMSWINC
@ MISCREG_PMSWINC
Definition misc.hh:373
gem5::ArmISA::MISCREG_MVFR1_EL1
@ MISCREG_MVFR1_EL1
Definition misc.hh:589
gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1
@ MISCREG_ID_AA64AFR0_EL1
Definition misc.hh:595
gem5::ArmISA::MISCREG_ATS12NSOPR
@ MISCREG_ATS12NSOPR
Definition misc.hh:326
gem5::ArmISA::MISCREG_MVFR2_EL1
@ MISCREG_MVFR2_EL1
Definition misc.hh:590
gem5::ArmISA::MISCREG_SMCR_EL12
@ MISCREG_SMCR_EL12
Definition misc.hh:1153
gem5::ArmISA::MISCREG_DBGBCR3
@ MISCREG_DBGBCR3
Definition misc.hh:143
gem5::ArmISA::MISCREG_OSLSR_EL1
@ MISCREG_OSLSR_EL1
Definition misc.hh:559
gem5::ArmISA::MISCREG_DBGBCR9_EL1
@ MISCREG_DBGBCR9_EL1
Definition misc.hh:513
gem5::ArmISA::MISCREG_PMCNTENSET_EL0
@ MISCREG_PMCNTENSET_EL0
Definition misc.hh:797
gem5::ArmISA::MISCREG_ID_ISAR1_EL1
@ MISCREG_ID_ISAR1_EL1
Definition misc.hh:582
gem5::ArmISA::MISCREG_AIDR
@ MISCREG_AIDR
Definition misc.hh:247
gem5::ArmISA::MISCREG_DFSR
@ MISCREG_DFSR
Definition misc.hh:286
gem5::ArmISA::MISCREG_DBGWVR12_EL1
@ MISCREG_DBGWVR12_EL1
Definition misc.hh:532
gem5::ArmISA::MISCREG_ICC_AP1R1
@ MISCREG_ICC_AP1R1
Definition misc.hh:1051
gem5::ArmISA::MISCREG_CPUACTLR_EL1
@ MISCREG_CPUACTLR_EL1
Definition misc.hh:896
gem5::ArmISA::MISCREG_DBGBCR15_EL1
@ MISCREG_DBGBCR15_EL1
Definition misc.hh:519
gem5::ArmISA::MISCREG_DLR_EL0
@ MISCREG_DLR_EL0
Definition misc.hh:662
gem5::ArmISA::MISCREG_DBGBVR5
@ MISCREG_DBGBVR5
Definition misc.hh:129
gem5::ArmISA::MISCREG_MVFR0
@ MISCREG_MVFR0
Definition misc.hh:92
gem5::ArmISA::MISCREG_ICH_LR0
@ MISCREG_ICH_LR0
Definition misc.hh:1105
gem5::ArmISA::MISCREG_ICH_LRC2
@ MISCREG_ICH_LRC2
Definition misc.hh:1123
gem5::ArmISA::MISCREG_DBGWVR5
@ MISCREG_DBGWVR5
Definition misc.hh:161
gem5::ArmISA::MISCREG_MPAMVPM1_EL2
@ MISCREG_MPAMVPM1_EL2
Definition misc.hh:1180
gem5::ArmISA::MISCREG_ID_MMFR1_EL1
@ MISCREG_ID_MMFR1_EL1
Definition misc.hh:577
gem5::ArmISA::MISCREG_PRRR_MAIR0_S
@ MISCREG_PRRR_MAIR0_S
Definition misc.hh:104
gem5::ArmISA::MISCREG_ICC_AP1R3_S
@ MISCREG_ICC_AP1R3_S
Definition misc.hh:1059
gem5::ArmISA::MISCREG_MAIR1_S
@ MISCREG_MAIR1_S
Definition misc.hh:410
gem5::ArmISA::MISCREG_DACR32_EL2
@ MISCREG_DACR32_EL2
Definition misc.hh:649
gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition misc.hh:597
gem5::ArmISA::MISCREG_HIFAR
@ MISCREG_HIFAR
Definition misc.hh:308
gem5::ArmISA::MISCREG_DBGWVR8
@ MISCREG_DBGWVR8
Definition misc.hh:164
gem5::ArmISA::MISCREG_ICC_SRE_EL1_S
@ MISCREG_ICC_SRE_EL1_S
Definition misc.hh:959
gem5::ArmISA::MISCREG_ICH_EISR_EL2
@ MISCREG_ICH_EISR_EL2
Definition misc.hh:981
gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2
@ MISCREG_CNTHP_TVAL_EL2
Definition misc.hh:860
gem5::ArmISA::MISCREG_AT_S1E3W_Xt
@ MISCREG_AT_S1E3W_Xt
Definition misc.hh:715
gem5::ArmISA::MISCREG_ICC_BPR1_EL1
@ MISCREG_ICC_BPR1_EL1
Definition misc.hh:951
gem5::ArmISA::MISCREG_ICC_AP0R1_EL1
@ MISCREG_ICC_AP0R1_EL1
Definition misc.hh:928
gem5::ArmISA::MISCREG_DBGWCR1_EL1
@ MISCREG_DBGWCR1_EL1
Definition misc.hh:537
gem5::ArmISA::MISCREG_DCISW
@ MISCREG_DCISW
Definition misc.hh:321
gem5::ArmISA::MISCREG_ID_MMFR2
@ MISCREG_ID_MMFR2
Definition misc.hh:235
gem5::ArmISA::MISCREG_HMAIR1
@ MISCREG_HMAIR1
Definition misc.hh:418
gem5::ArmISA::MISCREG_ICH_LR0_EL2
@ MISCREG_ICH_LR0_EL2
Definition misc.hh:984
gem5::ArmISA::MISCREG_APGAKeyHi_EL1
@ MISCREG_APGAKeyHi_EL1
Definition misc.hh:914
gem5::ArmISA::MISCREG_VMPIDR_EL2
@ MISCREG_VMPIDR_EL2
Definition misc.hh:608
gem5::ArmISA::MISCREG_IC_IVAU_Xt
@ MISCREG_IC_IVAU_Xt
Definition misc.hh:704
gem5::ArmISA::MISCREG_ICC_IAR0_EL1
@ MISCREG_ICC_IAR0_EL1
Definition misc.hh:923
gem5::ArmISA::MISCREG_MPAMVPM5_EL2
@ MISCREG_MPAMVPM5_EL2
Definition misc.hh:1184
gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S
@ MISCREG_ICC_BPR1_EL1_S
Definition misc.hh:953
gem5::ArmISA::MISCREG_DBGBCR8
@ MISCREG_DBGBCR8
Definition misc.hh:148
gem5::ArmISA::MISCREG_AMAIR0
@ MISCREG_AMAIR0
Definition misc.hh:411
gem5::ArmISA::MISCREG_VBAR_NS
@ MISCREG_VBAR_NS
Definition misc.hh:422
gem5::ArmISA::MISCREG_DBGWCR3_EL1
@ MISCREG_DBGWCR3_EL1
Definition misc.hh:539
gem5::ArmISA::MISCREG_PMEVCNTR0
@ MISCREG_PMEVCNTR0
Definition misc.hh:379
gem5::ArmISA::MISCREG_PMOVSCLR_EL0
@ MISCREG_PMOVSCLR_EL0
Definition misc.hh:799
gem5::ArmISA::MISCREG_ICC_MSRE
@ MISCREG_ICC_MSRE
Definition misc.hh:1082
gem5::ArmISA::MISCREG_DBGBCR5
@ MISCREG_DBGBCR5
Definition misc.hh:145
gem5::ArmISA::MISCREG_PMCCNTR
@ MISCREG_PMCCNTR
Definition misc.hh:377
gem5::ArmISA::MISCREG_ICC_AP1R0_NS
@ MISCREG_ICC_AP1R0_NS
Definition misc.hh:1049
gem5::ArmISA::MISCREG_HSR
@ MISCREG_HSR
Definition misc.hh:300
gem5::ArmISA::MISCREG_ICC_AP1R2_EL1
@ MISCREG_ICC_AP1R2_EL1
Definition misc.hh:937
gem5::ArmISA::MISCREG_TPIDRURO
@ MISCREG_TPIDRURO
Definition misc.hh:435
gem5::ArmISA::MISCREG_ICH_LRC1
@ MISCREG_ICH_LRC1
Definition misc.hh:1122
gem5::ArmISA::MISCREG_HCR2
@ MISCREG_HCR2
Definition misc.hh:267
gem5::ArmISA::MISCREG_DSPSR_EL0
@ MISCREG_DSPSR_EL0
Definition misc.hh:661
gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1
@ MISCREG_ICC_HPPIR1_EL1
Definition misc.hh:950
gem5::ArmISA::MISCREG_L2MERRSR_EL1
@ MISCREG_L2MERRSR_EL1
Definition misc.hh:899
gem5::ArmISA::MISCREG_ICC_AP1R3_EL1
@ MISCREG_ICC_AP1R3_EL1
Definition misc.hh:940
gem5::ArmISA::MISCREG_CNTHP_CVAL
@ MISCREG_CNTHP_CVAL
Definition misc.hh:461
gem5::ArmISA::MISCREG_TTBR0_NS
@ MISCREG_TTBR0_NS
Definition misc.hh:273
gem5::ArmISA::MISCREG_ICC_RPR
@ MISCREG_ICC_RPR
Definition misc.hh:1084
gem5::ArmISA::MISCREG_FAR_EL2
@ MISCREG_FAR_EL2
Definition misc.hh:689
gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2
@ MISCREG_CNTHVS_CTL_EL2
Definition misc.hh:868
gem5::ArmISA::MISCREG_DBGBCR7
@ MISCREG_DBGBCR7
Definition misc.hh:147
gem5::ArmISA::MISCREG_DBGWVR3
@ MISCREG_DBGWVR3
Definition misc.hh:159
gem5::ArmISA::MISCREG_ID_AA64SMFR0_EL1
@ MISCREG_ID_AA64SMFR0_EL1
Definition misc.hh:1146
gem5::ArmISA::MISCREG_ICC_ASGI1R
@ MISCREG_ICC_ASGI1R
Definition misc.hh:1060
gem5::ArmISA::MISCREG_ICH_AP1R0_EL2
@ MISCREG_ICH_AP1R0_EL2
Definition misc.hh:974
gem5::ArmISA::MISCREG_PMEVCNTR3_EL0
@ MISCREG_PMEVCNTR3_EL0
Definition misc.hh:877
gem5::ArmISA::MISCREG_FPSCR_EXC
@ MISCREG_FPSCR_EXC
Definition misc.hh:98
gem5::ArmISA::MISCREG_CNTV_TVAL_EL02
@ MISCREG_CNTV_TVAL_EL02
Definition misc.hh:851
gem5::ArmISA::MISCREG_RVBAR_EL3
@ MISCREG_RVBAR_EL3
Definition misc.hh:827
gem5::ArmISA::MISCREG_ICH_VTR_EL2
@ MISCREG_ICH_VTR_EL2
Definition misc.hh:979
gem5::ArmISA::MISCREG_DBGBCR10_EL1
@ MISCREG_DBGBCR10_EL1
Definition misc.hh:514
gem5::ArmISA::MISCREG_OSDTRRX_EL1
@ MISCREG_OSDTRRX_EL1
Definition misc.hh:484
gem5::ArmISA::MISCREG_AT_S1E0R_Xt
@ MISCREG_AT_S1E0R_Xt
Definition misc.hh:699
gem5::ArmISA::MISCREG_MPAM1_EL12
@ MISCREG_MPAM1_EL12
Definition misc.hh:1176
gem5::ArmISA::MISCREG_MDDTRTX_EL0
@ MISCREG_MDDTRTX_EL0
Definition misc.hh:554
gem5::ArmISA::MISCREG_ICC_SRE_S
@ MISCREG_ICC_SRE_S
Definition misc.hh:1089
gem5::ArmISA::MISCREG_DBGWVR6_EL1
@ MISCREG_DBGWVR6_EL1
Definition misc.hh:526
gem5::ArmISA::MISCREG_ID_ISAR3
@ MISCREG_ID_ISAR3
Definition misc.hh:241
gem5::ArmISA::MISCREG_CNTHP_CTL_EL2
@ MISCREG_CNTHP_CTL_EL2
Definition misc.hh:858
gem5::ArmISA::MISCREG_ICH_LR14
@ MISCREG_ICH_LR14
Definition misc.hh:1119
gem5::ArmISA::MISCREG_IMPDEF_UNIMPL
@ MISCREG_IMPDEF_UNIMPL
Definition misc.hh:1203
gem5::ArmISA::MISCREG_ICH_LRC10
@ MISCREG_ICH_LRC10
Definition misc.hh:1131
gem5::ArmISA::MISCREG_MVBAR
@ MISCREG_MVBAR
Definition misc.hh:424
gem5::ArmISA::MISCREG_DBGBCR6
@ MISCREG_DBGBCR6
Definition misc.hh:146
gem5::ArmISA::MISCREG_DBGWVR8_EL1
@ MISCREG_DBGWVR8_EL1
Definition misc.hh:528
gem5::ArmISA::MISCREG_ERXFR_EL1
@ MISCREG_ERXFR_EL1
Definition misc.hh:1208
gem5::ArmISA::MISCREG_PMCR_EL0
@ MISCREG_PMCR_EL0
Definition misc.hh:796
gem5::ArmISA::MISCREG_PAR
@ MISCREG_PAR
Definition misc.hh:312
gem5::ArmISA::MISCREG_CBAR
@ MISCREG_CBAR
Definition misc.hh:476
gem5::ArmISA::MISCREG_CONTEXTIDR_EL12
@ MISCREG_CONTEXTIDR_EL12
Definition misc.hh:830
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition misc.hh:630
gem5::ArmISA::MISCREG_ESR_EL2
@ MISCREG_ESR_EL2
Definition misc.hh:682
gem5::ArmISA::MISCREG_HADFSR
@ MISCREG_HADFSR
Definition misc.hh:298
gem5::ArmISA::MISCREG_SPSR_FIQ_AA64
@ MISCREG_SPSR_FIQ_AA64
Definition misc.hh:669
gem5::ArmISA::MISCREG_IC_IALLUIS
@ MISCREG_IC_IALLUIS
Definition misc.hh:692
gem5::ArmISA::MISCREG_NMRR_MAIR1_NS
@ MISCREG_NMRR_MAIR1_NS
Definition misc.hh:106
gem5::ArmISA::MISCREG_ICH_LR4
@ MISCREG_ICH_LR4
Definition misc.hh:1109
gem5::ArmISA::MISCREG_ID_PFR0
@ MISCREG_ID_PFR0
Definition misc.hh:229
gem5::ArmISA::MISCREG_CLIDR_EL1
@ MISCREG_CLIDR_EL1
Definition misc.hh:602
gem5::ArmISA::MISCREG_ICH_LRC4
@ MISCREG_ICH_LRC4
Definition misc.hh:1125
gem5::ArmISA::MISCREG_DBGBVR6
@ MISCREG_DBGBVR6
Definition misc.hh:130
gem5::ArmISA::MISCREG_NMRR_S
@ MISCREG_NMRR_S
Definition misc.hh:407
gem5::ArmISA::MISCREG_DCCMVAC
@ MISCREG_DCCMVAC
Definition misc.hh:330
gem5::ArmISA::MISCREG_L2ECTLR_EL1
@ MISCREG_L2ECTLR_EL1
Definition misc.hh:819
gem5::ArmISA::MISCREG_ICC_BPR1
@ MISCREG_ICC_BPR1
Definition misc.hh:1062
gem5::ArmISA::MISCREG_ICH_LR11
@ MISCREG_ICH_LR11
Definition misc.hh:1116
gem5::ArmISA::MISCREG_IFAR_S
@ MISCREG_IFAR_S
Definition misc.hh:306
gem5::ArmISA::MISCREG_ICH_AP0R2
@ MISCREG_ICH_AP0R2
Definition misc.hh:1093
gem5::ArmISA::MISCREG_ID_MMFR3_EL1
@ MISCREG_ID_MMFR3_EL1
Definition misc.hh:579
gem5::ArmISA::MISCREG_SPSR_IRQ_AA64
@ MISCREG_SPSR_IRQ_AA64
Definition misc.hh:666
gem5::ArmISA::MISCREG_ID_MMFR4
@ MISCREG_ID_MMFR4
Definition misc.hh:237
gem5::ArmISA::MISCREG_DBGBXVR1
@ MISCREG_DBGBXVR1
Definition misc.hh:190
gem5::ArmISA::MISCREG_AFSR1_EL1
@ MISCREG_AFSR1_EL1
Definition misc.hh:675
gem5::ArmISA::MISCREG_CNTP_CVAL_S
@ MISCREG_CNTP_CVAL_S
Definition misc.hh:451
gem5::ArmISA::MISCREG_ICH_LR13
@ MISCREG_ICH_LR13
Definition misc.hh:1118
gem5::ArmISA::MISCREG_TPIDRURO_S
@ MISCREG_TPIDRURO_S
Definition misc.hh:437
gem5::ArmISA::MISCREG_DBGBVR4_EL1
@ MISCREG_DBGBVR4_EL1
Definition misc.hh:492
gem5::ArmISA::MISCREG_VSTTBR_EL2
@ MISCREG_VSTTBR_EL2
Definition misc.hh:645
gem5::ArmISA::MISCREG_CNTKCTL
@ MISCREG_CNTKCTL
Definition misc.hh:458
gem5::ArmISA::MISCREG_PRRR_MAIR0_NS
@ MISCREG_PRRR_MAIR0_NS
Definition misc.hh:103
gem5::ArmISA::MISCREG_DBGWVR4
@ MISCREG_DBGWVR4
Definition misc.hh:160
gem5::ArmISA::MISCREG_CONTEXTIDR_S
@ MISCREG_CONTEXTIDR_S
Definition misc.hh:431
gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2
@ MISCREG_CNTHV_CVAL_EL2
Definition misc.hh:866
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition misc.hh:100
gem5::ArmISA::MISCREG_PMCEID1_EL0
@ MISCREG_PMCEID1_EL0
Definition misc.hh:803
gem5::ArmISA::MISCREG_TPIDRURW_NS
@ MISCREG_TPIDRURW_NS
Definition misc.hh:433
gem5::ArmISA::MISCREG_CTR_EL0
@ MISCREG_CTR_EL0
Definition misc.hh:605
gem5::ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition misc.hh:837
gem5::ArmISA::MISCREG_ID_AFR0
@ MISCREG_ID_AFR0
Definition misc.hh:232
gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S
@ MISCREG_ICC_CTLR_EL1_S
Definition misc.hh:956
gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1
@ MISCREG_DBGAUTHSTATUS_EL1
Definition misc.hh:564
gem5::ArmISA::MISCREG_DBGBCR1
@ MISCREG_DBGBCR1
Definition misc.hh:141
gem5::ArmISA::MISCREG_FPEXC32_EL2
@ MISCREG_FPEXC32_EL2
Definition misc.hh:683
gem5::ArmISA::MISCREG_TPIDRURO_NS
@ MISCREG_TPIDRURO_NS
Definition misc.hh:436
gem5::ArmISA::MISCREG_DBGBCR13
@ MISCREG_DBGBCR13
Definition misc.hh:153
gem5::ArmISA::MISCREG_MDDTR_EL0
@ MISCREG_MDDTR_EL0
Definition misc.hh:553
gem5::ArmISA::MISCREG_TLBIMVAA
@ MISCREG_TLBIMVAA
Definition misc.hh:354
gem5::ArmISA::MISCREG_ICC_AP1R1_NS
@ MISCREG_ICC_AP1R1_NS
Definition misc.hh:1052
gem5::ArmISA::MISCREG_PMEVCNTR1_EL0
@ MISCREG_PMEVCNTR1_EL0
Definition misc.hh:875
gem5::ArmISA::MISCREG_SPSR
@ MISCREG_SPSR
Definition misc.hh:80
gem5::ArmISA::MISCREG_TPIDRPRW
@ MISCREG_TPIDRPRW
Definition misc.hh:438
gem5::ArmISA::MISCREG_ACTLR
@ MISCREG_ACTLR
Definition misc.hh:256
gem5::ArmISA::MISCREG_DBGBVR12
@ MISCREG_DBGBVR12
Definition misc.hh:136
gem5::ArmISA::MISCREG_VTTBR_EL2
@ MISCREG_VTTBR_EL2
Definition misc.hh:643
gem5::ArmISA::MISCREG_DBGWCR7
@ MISCREG_DBGWCR7
Definition misc.hh:179
gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR
@ MISCREG_PMXEVTYPER_PMCCFILTR
Definition misc.hh:108
gem5::ArmISA::MISCREG_MAIR1_NS
@ MISCREG_MAIR1_NS
Definition misc.hh:409
gem5::ArmISA::MISCREG_ICC_HPPIR1
@ MISCREG_ICC_HPPIR1
Definition misc.hh:1072
gem5::ArmISA::MISCREG_VDISR_EL2
@ MISCREG_VDISR_EL2
Definition misc.hh:1216
gem5::ArmISA::MISCREG_DBGBVR15
@ MISCREG_DBGBVR15
Definition misc.hh:139
gem5::ArmISA::MISCREG_DBGBVR4
@ MISCREG_DBGBVR4
Definition misc.hh:128
gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1
@ MISCREG_ID_AA64PFR1_EL1
Definition misc.hh:592
gem5::ArmISA::MISCREG_RAMINDEX
@ MISCREG_RAMINDEX
Definition misc.hh:474
gem5::ArmISA::MISCREG_HSTR
@ MISCREG_HSTR
Definition misc.hh:270
gem5::ArmISA::MISCREG_MDCR_EL3
@ MISCREG_MDCR_EL3
Definition misc.hh:631
gem5::ArmISA::MISCREG_AFSR0_EL2
@ MISCREG_AFSR0_EL2
Definition misc.hh:680
gem5::ArmISA::MISCREG_ID_ISAR2
@ MISCREG_ID_ISAR2
Definition misc.hh:240
gem5::ArmISA::MISCREG_SPSR_FIQ
@ MISCREG_SPSR_FIQ
Definition misc.hh:81
gem5::ArmISA::MISCREG_PRRR_S
@ MISCREG_PRRR_S
Definition misc.hh:401
gem5::ArmISA::MISCREG_ICC_AP1R3_NS
@ MISCREG_ICC_AP1R3_NS
Definition misc.hh:1058
gem5::ArmISA::MISCREG_CNTV_CVAL_EL0
@ MISCREG_CNTV_CVAL_EL0
Definition misc.hh:844
gem5::ArmISA::MISCREG_ZCR_EL12
@ MISCREG_ZCR_EL12
Definition misc.hh:1142
gem5::ArmISA::MISCREG_DBGWCR13
@ MISCREG_DBGWCR13
Definition misc.hh:185
gem5::ArmISA::MISCREG_SP_EL1
@ MISCREG_SP_EL1
Definition misc.hh:665
gem5::ArmISA::MISCREG_ATS1CUW
@ MISCREG_ATS1CUW
Definition misc.hh:325
gem5::ArmISA::MISCREG_MAIR0
@ MISCREG_MAIR0
Definition misc.hh:402
gem5::ArmISA::MISCREG_PMOVSSET_EL0
@ MISCREG_PMOVSSET_EL0
Definition misc.hh:809
gem5::ArmISA::encodeAArch64SysReg
std::optional< MiscRegNum64 > encodeAArch64SysReg(MiscRegIndex misc_reg)
Definition misc.cc:2956
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition misc_types.hh:73
gem5::ArmISA::MISCREG_USR_S_RD
@ MISCREG_USR_S_RD
Definition misc.hh:1251
gem5::ArmISA::MISCREG_BANKED_CHILD
@ MISCREG_BANKED_CHILD
Definition misc.hh:1243
gem5::ArmISA::MISCREG_MON_NS1_RD
@ MISCREG_MON_NS1_RD
Definition misc.hh:1267
gem5::ArmISA::MISCREG_PRI_NS_WR
@ MISCREG_PRI_NS_WR
Definition misc.hh:1255
gem5::ArmISA::MISCREG_PRI_S_WR
@ MISCREG_PRI_S_WR
Definition misc.hh:1257
gem5::ArmISA::MISCREG_MON_NS0_RD
@ MISCREG_MON_NS0_RD
Definition misc.hh:1264
gem5::ArmISA::MISCREG_BANKED
@ MISCREG_BANKED
Definition misc.hh:1237
gem5::ArmISA::MISCREG_WARN_NOT_FAIL
@ MISCREG_WARN_NOT_FAIL
Definition misc.hh:1232
gem5::ArmISA::MISCREG_MON_NS1_WR
@ MISCREG_MON_NS1_WR
Definition misc.hh:1268
gem5::ArmISA::MISCREG_HYP_NS_WR
@ MISCREG_HYP_NS_WR
Definition misc.hh:1260
gem5::ArmISA::MISCREG_PRI_S_RD
@ MISCREG_PRI_S_RD
Definition misc.hh:1256
gem5::ArmISA::MISCREG_PRI_NS_RD
@ MISCREG_PRI_NS_RD
Definition misc.hh:1254
gem5::ArmISA::MISCREG_USR_NS_WR
@ MISCREG_USR_NS_WR
Definition misc.hh:1250
gem5::ArmISA::MISCREG_USR_S_WR
@ MISCREG_USR_S_WR
Definition misc.hh:1252
gem5::ArmISA::MISCREG_USR_NS_RD
@ MISCREG_USR_NS_RD
Definition misc.hh:1249
gem5::ArmISA::MISCREG_MON_NS0_WR
@ MISCREG_MON_NS0_WR
Definition misc.hh:1265
gem5::ArmISA::MISCREG_HYP_NS_RD
@ MISCREG_HYP_NS_RD
Definition misc.hh:1259
gem5::ArmISA::decodeCP14Reg
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition misc.cc:535
gem5::ArmISA::condGenericTimerSystemAccessTrapEL1
bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex misc_reg, ThreadContext *tc)
Definition utility.cc:898
gem5::ArmISA::unflattenMiscReg
int unflattenMiscReg(int reg)
Definition misc.cc:738
gem5::ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:686
gem5::ArmISA::aarch64
Bitfield< 34 > aarch64
Definition types.hh:81
gem5::ArmISA::canWriteCoprocReg
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to write coprocessor registers.
Definition misc.cc:627
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition utility.cc:232
gem5::ArmISA::snsBankedIndex64
int snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
Definition misc.cc:704
gem5::ArmISA::decodeCP15Reg64
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition misc.cc:568
gem5::ArmISA::lookUpMiscReg
std::vector< struct MiscRegLUTEntry > lookUpMiscReg(NUM_MISCREGS)
Definition misc.hh:1719
gem5::ArmISA::defaultFaultE2H_EL2
static Fault defaultFaultE2H_EL2(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:2987
gem5::ArmISA::canReadCoprocReg
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Check for permission to read coprocessor registers.
Definition misc.cc:580
gem5::ArmISA::defaultFaultE2H_EL3
static Fault defaultFaultE2H_EL3(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:2999
gem5::MipsISA::p
Bitfield< 0 > p
Definition pra_constants.hh:326
gem5::SparcISA::priv
Bitfield< 2 > priv
Definition misc.hh:131
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition types.hh:92
gem5::X86ISA::system
Bitfield< 15 > system
Definition misc.hh:1032
gem5::X86ISA::val
Bitfield< 63 > val
Definition misc.hh:804
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition root.cc:220
gem5::RegVal
uint64_t RegVal
Definition types.hh:173
gem5::hyp
Bitfield< 9 > hyp
Definition smmu_v3_defs.hh:116
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition types.hh:253
gem5::ArmISA::MiscRegLUTEntry
MiscReg metadata.
Definition misc.hh:1275
gem5::ArmISA::MiscRegLUTEntry::defaultFault
static Fault defaultFault(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
Definition misc.cc:2976
gem5::ArmISA::MiscRegLUTEntry::faultRead
std::array< FaultCB, EL3+1 > faultRead
Definition misc.hh:1290
gem5::ArmISA::MiscRegLUTEntry::info
std::bitset< NUM_MISCREG_INFOS > info
Definition misc.hh:1283
gem5::ArmISA::MiscRegLUTEntry::faultWrite
std::array< FaultCB, EL3+1 > faultWrite
Definition misc.hh:1291
gem5::ArmISA::MiscRegLUTEntry::checkFault
Fault checkFault(ThreadContext *tc, const MiscRegOp64 &inst, ExceptionLevel el)
Definition misc.cc:2967
Generated on Mon Jan 13 2025 04:28:21 for gem5 by doxygen 1.9.8