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flat.cc
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1/*
2 * Copyright (c) 2024 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "arch/amdgpu/vega/insts/instructions.hh"
33
34namespace gem5
35{
36
37namespace VegaISA
38{
39 // --- Inst_FLAT__FLAT_LOAD_UBYTE class methods ---
40
41 Inst_FLAT__FLAT_LOAD_UBYTE::Inst_FLAT__FLAT_LOAD_UBYTE(InFmt_FLAT *iFmt)
42 : Inst_FLAT(iFmt, "flat_load_ubyte")
43 {
44 setFlag(MemoryRef);
45 setFlag(Load);
46 } // Inst_FLAT__FLAT_LOAD_UBYTE
47
48 Inst_FLAT__FLAT_LOAD_UBYTE::~Inst_FLAT__FLAT_LOAD_UBYTE()
49 {
50 } // ~Inst_FLAT__FLAT_LOAD_UBYTE
51
52 // --- description from .arch file ---
53 // Untyped buffer load unsigned byte (zero extend to VGPR destination).
54 void
55 Inst_FLAT__FLAT_LOAD_UBYTE::execute(GPUDynInstPtr gpuDynInst)
56 {
57 Wavefront *wf = gpuDynInst->wavefront();
58
59 if (gpuDynInst->exec_mask.none()) {
60 wf->decVMemInstsIssued();
61 if (isFlat()) {
62 wf->decLGKMInstsIssued();
63 }
64 return;
65 }
66
67 gpuDynInst->execUnitId = wf->execUnitId;
68 gpuDynInst->latency.init(gpuDynInst->computeUnit());
69 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
70
71 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
72
73 issueRequestHelper(gpuDynInst);
74 } // execute
75
76 void
77 Inst_FLAT__FLAT_LOAD_UBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
78 {
79 initMemRead<VecElemU8>(gpuDynInst);
80 } // initiateAcc
81
82 void
83 Inst_FLAT__FLAT_LOAD_UBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
84 {
85 VecOperandU32 vdst(gpuDynInst, extData.VDST);
86
87 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
88 if (gpuDynInst->exec_mask[lane]) {
89 vdst[lane] = (VecElemU32)((reinterpret_cast<VecElemU8*>(
90 gpuDynInst->d_data))[lane]);
91 }
92 }
93 vdst.write();
94 } // execute
95 // --- Inst_FLAT__FLAT_LOAD_SBYTE class methods ---
96
97 Inst_FLAT__FLAT_LOAD_SBYTE::Inst_FLAT__FLAT_LOAD_SBYTE(InFmt_FLAT *iFmt)
98 : Inst_FLAT(iFmt, "flat_load_sbyte")
99 {
100 setFlag(MemoryRef);
101 setFlag(Load);
102 } // Inst_FLAT__FLAT_LOAD_SBYTE
103
104 Inst_FLAT__FLAT_LOAD_SBYTE::~Inst_FLAT__FLAT_LOAD_SBYTE()
105 {
106 } // ~Inst_FLAT__FLAT_LOAD_SBYTE
107
108 // --- description from .arch file ---
109 // Untyped buffer load signed byte (sign extend to VGPR destination).
110 void
111 Inst_FLAT__FLAT_LOAD_SBYTE::execute(GPUDynInstPtr gpuDynInst)
112 {
113 Wavefront *wf = gpuDynInst->wavefront();
114
115 if (gpuDynInst->exec_mask.none()) {
116 wf->decVMemInstsIssued();
117 if (isFlat()) {
118 wf->decLGKMInstsIssued();
119 }
120 return;
121 }
122
123 gpuDynInst->execUnitId = wf->execUnitId;
124 gpuDynInst->latency.init(gpuDynInst->computeUnit());
125 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
126
127 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
128
129 issueRequestHelper(gpuDynInst);
130 } // execute
131
132 void
133 Inst_FLAT__FLAT_LOAD_SBYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
134 {
135 initMemRead<VecElemI8>(gpuDynInst);
136 } // initiateAcc
137
138 void
139 Inst_FLAT__FLAT_LOAD_SBYTE::completeAcc(GPUDynInstPtr gpuDynInst)
140 {
141 VecOperandU32 vdst(gpuDynInst, extData.VDST);
142
143 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
144 if (gpuDynInst->exec_mask[lane]) {
145 vdst[lane] = (VecElemI32)((reinterpret_cast<VecElemI8*>(
146 gpuDynInst->d_data))[lane]);
147 }
148 }
149 vdst.write();
150 } // execute
151 // --- Inst_FLAT__FLAT_LOAD_USHORT class methods ---
152
153 Inst_FLAT__FLAT_LOAD_USHORT::Inst_FLAT__FLAT_LOAD_USHORT(InFmt_FLAT *iFmt)
154 : Inst_FLAT(iFmt, "flat_load_ushort")
155 {
156 setFlag(MemoryRef);
157 setFlag(Load);
158 } // Inst_FLAT__FLAT_LOAD_USHORT
159
160 Inst_FLAT__FLAT_LOAD_USHORT::~Inst_FLAT__FLAT_LOAD_USHORT()
161 {
162 } // ~Inst_FLAT__FLAT_LOAD_USHORT
163
164 // --- description from .arch file ---
165 // Untyped buffer load unsigned short (zero extend to VGPR destination).
166 void
167 Inst_FLAT__FLAT_LOAD_USHORT::execute(GPUDynInstPtr gpuDynInst)
168 {
169 Wavefront *wf = gpuDynInst->wavefront();
170
171 if (gpuDynInst->exec_mask.none()) {
172 wf->decVMemInstsIssued();
173 if (isFlat()) {
174 wf->decLGKMInstsIssued();
175 }
176 return;
177 }
178
179 gpuDynInst->execUnitId = wf->execUnitId;
180 gpuDynInst->latency.init(gpuDynInst->computeUnit());
181 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
182
183 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
184
185 issueRequestHelper(gpuDynInst);
186 } // execute
187
188 void
189 Inst_FLAT__FLAT_LOAD_USHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
190 {
191 initMemRead<VecElemU16>(gpuDynInst);
192 } // initiateAcc
193
194 void
195 Inst_FLAT__FLAT_LOAD_USHORT::completeAcc(GPUDynInstPtr gpuDynInst)
196 {
197 VecOperandU32 vdst(gpuDynInst, extData.VDST);
198
199 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
200 if (gpuDynInst->exec_mask[lane]) {
201 vdst[lane] = (VecElemU32)((reinterpret_cast<VecElemU16*>(
202 gpuDynInst->d_data))[lane]);
203 }
204 }
205 vdst.write();
206 } // execute
207
208 // --- Inst_FLAT__FLAT_LOAD_SSHORT class methods ---
209
210 Inst_FLAT__FLAT_LOAD_SSHORT::Inst_FLAT__FLAT_LOAD_SSHORT(InFmt_FLAT *iFmt)
211 : Inst_FLAT(iFmt, "flat_load_sshort")
212 {
213 setFlag(MemoryRef);
214 setFlag(Load);
215 } // Inst_FLAT__FLAT_LOAD_SSHORT
216
217 Inst_FLAT__FLAT_LOAD_SSHORT::~Inst_FLAT__FLAT_LOAD_SSHORT()
218 {
219 } // ~Inst_FLAT__FLAT_LOAD_SSHORT
220
221 // --- description from .arch file ---
222 // Untyped buffer load signed short (sign extend to VGPR destination).
223 void
228
229 void
230 Inst_FLAT__FLAT_LOAD_SSHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
231 {
232 } // initiateAcc
233
234 void
235 Inst_FLAT__FLAT_LOAD_SSHORT::completeAcc(GPUDynInstPtr gpuDynInst)
236 {
237 } // execute
238 // --- Inst_FLAT__FLAT_LOAD_DWORD class methods ---
239
240 Inst_FLAT__FLAT_LOAD_DWORD::Inst_FLAT__FLAT_LOAD_DWORD(InFmt_FLAT *iFmt)
241 : Inst_FLAT(iFmt, "flat_load_dword")
242 {
243 setFlag(MemoryRef);
244 setFlag(Load);
245 } // Inst_FLAT__FLAT_LOAD_DWORD
246
247 Inst_FLAT__FLAT_LOAD_DWORD::~Inst_FLAT__FLAT_LOAD_DWORD()
248 {
249 } // ~Inst_FLAT__FLAT_LOAD_DWORD
250
251 // --- description from .arch file ---
252 // Untyped buffer load dword.
253 void
254 Inst_FLAT__FLAT_LOAD_DWORD::execute(GPUDynInstPtr gpuDynInst)
255 {
256 Wavefront *wf = gpuDynInst->wavefront();
257
258 if (gpuDynInst->exec_mask.none()) {
259 wf->decVMemInstsIssued();
260 if (isFlat()) {
261 wf->decLGKMInstsIssued();
262 }
263 return;
264 }
265
266 gpuDynInst->execUnitId = wf->execUnitId;
267 gpuDynInst->latency.init(gpuDynInst->computeUnit());
268 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
269
270 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
271
272 issueRequestHelper(gpuDynInst);
273 } // execute
274
275 void
276 Inst_FLAT__FLAT_LOAD_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
277 {
278 initMemRead<VecElemU32>(gpuDynInst);
279 } // initiateAcc
280
281 void
282 Inst_FLAT__FLAT_LOAD_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
283 {
284 VecOperandU32 vdst(gpuDynInst, extData.VDST);
285
286 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
287 if (gpuDynInst->exec_mask[lane]) {
288 vdst[lane] = (reinterpret_cast<VecElemU32*>(
289 gpuDynInst->d_data))[lane];
290 }
291 }
292 vdst.write();
293 } // completeAcc
294 // --- Inst_FLAT__FLAT_LOAD_DWORDX2 class methods ---
295
296 Inst_FLAT__FLAT_LOAD_DWORDX2::Inst_FLAT__FLAT_LOAD_DWORDX2(
297 InFmt_FLAT *iFmt)
298 : Inst_FLAT(iFmt, "flat_load_dwordx2")
299 {
300 setFlag(MemoryRef);
301 setFlag(Load);
302 } // Inst_FLAT__FLAT_LOAD_DWORDX2
303
304 Inst_FLAT__FLAT_LOAD_DWORDX2::~Inst_FLAT__FLAT_LOAD_DWORDX2()
305 {
306 } // ~Inst_FLAT__FLAT_LOAD_DWORDX2
307
308 // --- description from .arch file ---
309 // Untyped buffer load 2 dwords.
310 void
311 Inst_FLAT__FLAT_LOAD_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
312 {
313 Wavefront *wf = gpuDynInst->wavefront();
314
315 if (gpuDynInst->exec_mask.none()) {
316 wf->decVMemInstsIssued();
317 if (isFlat()) {
318 wf->decLGKMInstsIssued();
319 }
320 return;
321 }
322
323 gpuDynInst->execUnitId = wf->execUnitId;
324 gpuDynInst->latency.init(gpuDynInst->computeUnit());
325 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
326
327 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
328
329 issueRequestHelper(gpuDynInst);
330 } // execute
331
332 void
333 Inst_FLAT__FLAT_LOAD_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
334 {
335 initMemRead<2>(gpuDynInst);
336 } // initiateAcc
337
338 void
339 Inst_FLAT__FLAT_LOAD_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
340 {
341 VecOperandU32 vdst0(gpuDynInst, extData.VDST);
342 VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
343
344 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
345 if (gpuDynInst->exec_mask[lane] && !isFlatScratch()) {
346 vdst0[lane] = (reinterpret_cast<VecElemU32*>(
347 gpuDynInst->d_data))[lane * 2];
348 vdst1[lane] = (reinterpret_cast<VecElemU32*>(
349 gpuDynInst->d_data))[lane * 2 + 1];
350 } else if (gpuDynInst->exec_mask[lane] && isFlatScratch()) {
351 // Unswizzle the data opposite of swizzleData. See swizzleData
352 // in src/arch/amdgpu/vega/insts/op_encodings.hh for details.
353 vdst0[lane] = (reinterpret_cast<VecElemU32*>(
354 gpuDynInst->d_data))[lane];
355 vdst1[lane] = (reinterpret_cast<VecElemU32*>(
356 gpuDynInst->d_data))[lane + NumVecElemPerVecReg];
357 }
358 }
359
360 vdst0.write();
361 vdst1.write();
362 } // completeAcc
363 // --- Inst_FLAT__FLAT_LOAD_DWORDX3 class methods ---
364
365 Inst_FLAT__FLAT_LOAD_DWORDX3::Inst_FLAT__FLAT_LOAD_DWORDX3(
366 InFmt_FLAT *iFmt)
367 : Inst_FLAT(iFmt, "flat_load_dwordx3")
368 {
369 setFlag(MemoryRef);
370 setFlag(Load);
371 } // Inst_FLAT__FLAT_LOAD_DWORDX3
372
373 Inst_FLAT__FLAT_LOAD_DWORDX3::~Inst_FLAT__FLAT_LOAD_DWORDX3()
374 {
375 } // ~Inst_FLAT__FLAT_LOAD_DWORDX3
376
377 // --- description from .arch file ---
378 // Untyped buffer load 3 dwords.
379 void
380 Inst_FLAT__FLAT_LOAD_DWORDX3::execute(GPUDynInstPtr gpuDynInst)
381 {
382 Wavefront *wf = gpuDynInst->wavefront();
383
384 if (gpuDynInst->exec_mask.none()) {
385 wf->decVMemInstsIssued();
386 if (isFlat()) {
387 wf->decLGKMInstsIssued();
388 }
389 return;
390 }
391
392 gpuDynInst->execUnitId = wf->execUnitId;
393 gpuDynInst->latency.init(gpuDynInst->computeUnit());
394 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
395
396 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
397
398 issueRequestHelper(gpuDynInst);
399 } // execute
400
401 void
402 Inst_FLAT__FLAT_LOAD_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
403 {
404 initMemRead<3>(gpuDynInst);
405 } // initiateAcc
406
407 void
408 Inst_FLAT__FLAT_LOAD_DWORDX3::completeAcc(GPUDynInstPtr gpuDynInst)
409 {
410 VecOperandU32 vdst0(gpuDynInst, extData.VDST);
411 VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
412 VecOperandU32 vdst2(gpuDynInst, extData.VDST + 2);
413
414 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
415 if (gpuDynInst->exec_mask[lane] && !isFlatScratch()) {
416 vdst0[lane] = (reinterpret_cast<VecElemU32*>(
417 gpuDynInst->d_data))[lane * 3];
418 vdst1[lane] = (reinterpret_cast<VecElemU32*>(
419 gpuDynInst->d_data))[lane * 3 + 1];
420 vdst2[lane] = (reinterpret_cast<VecElemU32*>(
421 gpuDynInst->d_data))[lane * 3 + 2];
422 } else if (gpuDynInst->exec_mask[lane] && isFlatScratch()) {
423 // Unswizzle the data opposite of swizzleData. See swizzleData
424 // in src/arch/amdgpu/vega/insts/op_encodings.hh for details.
425 vdst0[lane] = (reinterpret_cast<VecElemU32*>(
426 gpuDynInst->d_data))[lane];
427 vdst1[lane] = (reinterpret_cast<VecElemU32*>(
428 gpuDynInst->d_data))[lane + NumVecElemPerVecReg];
429 vdst2[lane] = (reinterpret_cast<VecElemU32*>(
430 gpuDynInst->d_data))[lane + 2*NumVecElemPerVecReg];
431 }
432 }
433
434 vdst0.write();
435 vdst1.write();
436 vdst2.write();
437 } // completeAcc
438 // --- Inst_FLAT__FLAT_LOAD_DWORDX4 class methods ---
439
440 Inst_FLAT__FLAT_LOAD_DWORDX4::Inst_FLAT__FLAT_LOAD_DWORDX4(
441 InFmt_FLAT *iFmt)
442 : Inst_FLAT(iFmt, "flat_load_dwordx4")
443 {
444 setFlag(MemoryRef);
445 setFlag(Load);
446 } // Inst_FLAT__FLAT_LOAD_DWORDX4
447
448 Inst_FLAT__FLAT_LOAD_DWORDX4::~Inst_FLAT__FLAT_LOAD_DWORDX4()
449 {
450 } // ~Inst_FLAT__FLAT_LOAD_DWORDX4
451
452 // --- description from .arch file ---
453 // Untyped buffer load 4 dwords.
454 void
455 Inst_FLAT__FLAT_LOAD_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
456 {
457 Wavefront *wf = gpuDynInst->wavefront();
458
459 if (gpuDynInst->exec_mask.none()) {
460 wf->decVMemInstsIssued();
461 if (isFlat()) {
462 wf->decLGKMInstsIssued();
463 }
464 return;
465 }
466
467 gpuDynInst->execUnitId = wf->execUnitId;
468 gpuDynInst->latency.init(gpuDynInst->computeUnit());
469 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
470
471 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
472
473 issueRequestHelper(gpuDynInst);
474 } // execute
475
476 void
477 Inst_FLAT__FLAT_LOAD_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
478 {
479 initMemRead<4>(gpuDynInst);
480 } // initiateAcc
481
482 void
483 Inst_FLAT__FLAT_LOAD_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
484 {
485 VecOperandU32 vdst0(gpuDynInst, extData.VDST);
486 VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
487 VecOperandU32 vdst2(gpuDynInst, extData.VDST + 2);
488 VecOperandU32 vdst3(gpuDynInst, extData.VDST + 3);
489
490 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
491 if (gpuDynInst->exec_mask[lane] && !isFlatScratch()) {
492 vdst0[lane] = (reinterpret_cast<VecElemU32*>(
493 gpuDynInst->d_data))[lane * 4];
494 vdst1[lane] = (reinterpret_cast<VecElemU32*>(
495 gpuDynInst->d_data))[lane * 4 + 1];
496 vdst2[lane] = (reinterpret_cast<VecElemU32*>(
497 gpuDynInst->d_data))[lane * 4 + 2];
498 vdst3[lane] = (reinterpret_cast<VecElemU32*>(
499 gpuDynInst->d_data))[lane * 4 + 3];
500 } else if (gpuDynInst->exec_mask[lane] && isFlatScratch()) {
501 // Unswizzle the data opposite of swizzleData. See swizzleData
502 // in src/arch/amdgpu/vega/insts/op_encodings.hh for details.
503 vdst0[lane] = (reinterpret_cast<VecElemU32*>(
504 gpuDynInst->d_data))[lane];
505 vdst1[lane] = (reinterpret_cast<VecElemU32*>(
506 gpuDynInst->d_data))[lane + NumVecElemPerVecReg];
507 vdst2[lane] = (reinterpret_cast<VecElemU32*>(
508 gpuDynInst->d_data))[lane + 2*NumVecElemPerVecReg];
509 vdst3[lane] = (reinterpret_cast<VecElemU32*>(
510 gpuDynInst->d_data))[lane + 3*NumVecElemPerVecReg];
511 }
512 }
513
514 vdst0.write();
515 vdst1.write();
516 vdst2.write();
517 vdst3.write();
518 } // completeAcc
519 // --- Inst_FLAT__FLAT_STORE_BYTE class methods ---
520
521 Inst_FLAT__FLAT_STORE_BYTE::Inst_FLAT__FLAT_STORE_BYTE(InFmt_FLAT *iFmt)
522 : Inst_FLAT(iFmt, "flat_store_byte")
523 {
524 setFlag(MemoryRef);
525 setFlag(Store);
526 } // Inst_FLAT__FLAT_STORE_BYTE
527
528 Inst_FLAT__FLAT_STORE_BYTE::~Inst_FLAT__FLAT_STORE_BYTE()
529 {
530 } // ~Inst_FLAT__FLAT_STORE_BYTE
531
532 // --- description from .arch file ---
533 // Untyped buffer store byte.
534 void
535 Inst_FLAT__FLAT_STORE_BYTE::execute(GPUDynInstPtr gpuDynInst)
536 {
537 Wavefront *wf = gpuDynInst->wavefront();
538
539 if (gpuDynInst->exec_mask.none()) {
540 wf->decVMemInstsIssued();
541 if (isFlat()) {
542 wf->decLGKMInstsIssued();
543 }
544 wf->decExpInstsIssued();
545 return;
546 }
547
548 gpuDynInst->execUnitId = wf->execUnitId;
549 gpuDynInst->latency.init(gpuDynInst->computeUnit());
550 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
551
552 ConstVecOperandU8 data(gpuDynInst, extData.DATA);
553
554 data.read();
555
556 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
557
558 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
559 if (gpuDynInst->exec_mask[lane]) {
560 (reinterpret_cast<VecElemU8*>(gpuDynInst->d_data))[lane]
561 = data[lane];
562 }
563 }
564
565 issueRequestHelper(gpuDynInst);
566 } // execute
567
568 void
569 Inst_FLAT__FLAT_STORE_BYTE::initiateAcc(GPUDynInstPtr gpuDynInst)
570 {
571 initMemWrite<VecElemU8>(gpuDynInst);
572 } // initiateAcc
573
574 void
575 Inst_FLAT__FLAT_STORE_BYTE::completeAcc(GPUDynInstPtr gpuDynInst)
576 {
577 } // execute
578 // --- Inst_FLAT__FLAT_STORE_SHORT class methods ---
579
580 Inst_FLAT__FLAT_STORE_SHORT::Inst_FLAT__FLAT_STORE_SHORT(InFmt_FLAT *iFmt)
581 : Inst_FLAT(iFmt, "flat_store_short")
582 {
583 setFlag(MemoryRef);
584 setFlag(Store);
585 } // Inst_FLAT__FLAT_STORE_SHORT
586
587 Inst_FLAT__FLAT_STORE_SHORT::~Inst_FLAT__FLAT_STORE_SHORT()
588 {
589 } // ~Inst_FLAT__FLAT_STORE_SHORT
590
591 // --- description from .arch file ---
592 // Untyped buffer store short.
593 void
594 Inst_FLAT__FLAT_STORE_SHORT::execute(GPUDynInstPtr gpuDynInst)
595 {
596 Wavefront *wf = gpuDynInst->wavefront();
597
598 if (gpuDynInst->exec_mask.none()) {
599 wf->decVMemInstsIssued();
600 if (isFlat()) {
601 wf->decLGKMInstsIssued();
602 }
603 wf->decExpInstsIssued();
604 return;
605 }
606
607 gpuDynInst->execUnitId = wf->execUnitId;
608 gpuDynInst->latency.init(gpuDynInst->computeUnit());
609 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
610
611 ConstVecOperandU16 data(gpuDynInst, extData.DATA);
612
613 data.read();
614
615 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
616
617 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
618 if (gpuDynInst->exec_mask[lane]) {
619 (reinterpret_cast<VecElemU16*>(gpuDynInst->d_data))[lane]
620 = data[lane];
621 }
622 }
623
624 issueRequestHelper(gpuDynInst);
625 } // execute
626
627 void
628 Inst_FLAT__FLAT_STORE_SHORT::initiateAcc(GPUDynInstPtr gpuDynInst)
629 {
630 initMemWrite<VecElemU16>(gpuDynInst);
631 } // initiateAcc
632
633 void
634 Inst_FLAT__FLAT_STORE_SHORT::completeAcc(GPUDynInstPtr gpuDynInst)
635 {
636 } // completeAcc
637 // --- Inst_FLAT__FLAT_STORE_SHORT_D16_HI class methods ---
638
639 Inst_FLAT__FLAT_STORE_SHORT_D16_HI::
640 Inst_FLAT__FLAT_STORE_SHORT_D16_HI(InFmt_FLAT *iFmt)
641 : Inst_FLAT(iFmt, "flat_store_short_d16_hi")
642 {
643 setFlag(MemoryRef);
644 setFlag(Store);
645 } // Inst_FLAT__FLAT_STORE_SHORT_D16_HI
646
647 Inst_FLAT__FLAT_STORE_SHORT_D16_HI::~Inst_FLAT__FLAT_STORE_SHORT_D16_HI()
648 {
649 } // ~Inst_FLAT__FLAT_STORE_SHORT_D16_HI
650
651 // --- description from .arch file ---
652 // Untyped buffer store short.
653 void
654 Inst_FLAT__FLAT_STORE_SHORT_D16_HI::execute(GPUDynInstPtr gpuDynInst)
655 {
656 Wavefront *wf = gpuDynInst->wavefront();
657
658 if (gpuDynInst->exec_mask.none()) {
659 wf->decVMemInstsIssued();
660 if (isFlat()) {
661 wf->decLGKMInstsIssued();
662 }
663 wf->decExpInstsIssued();
664 return;
665 }
666
667 gpuDynInst->execUnitId = wf->execUnitId;
668 gpuDynInst->latency.init(gpuDynInst->computeUnit());
669 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
670
671 ConstVecOperandU32 data(gpuDynInst, extData.DATA);
672
673 data.read();
674
675 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
676
677 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
678 if (gpuDynInst->exec_mask[lane]) {
679 (reinterpret_cast<VecElemU16*>(gpuDynInst->d_data))[lane]
680 = (data[lane] >> 16);
681 }
682 }
683
684 issueRequestHelper(gpuDynInst);
685 } // execute
686
687 void
688 Inst_FLAT__FLAT_STORE_SHORT_D16_HI::initiateAcc(GPUDynInstPtr gpuDynInst)
689 {
690 initMemWrite<VecElemU16>(gpuDynInst);
691 } // initiateAcc
692
693 void
697 // --- Inst_FLAT__FLAT_STORE_DWORD class methods ---
698
699 Inst_FLAT__FLAT_STORE_DWORD::Inst_FLAT__FLAT_STORE_DWORD(InFmt_FLAT *iFmt)
700 : Inst_FLAT(iFmt, "flat_store_dword")
701 {
702 setFlag(MemoryRef);
703 setFlag(Store);
704 } // Inst_FLAT__FLAT_STORE_DWORD
705
706 Inst_FLAT__FLAT_STORE_DWORD::~Inst_FLAT__FLAT_STORE_DWORD()
707 {
708 } // ~Inst_FLAT__FLAT_STORE_DWORD
709
710 // --- description from .arch file ---
711 // Untyped buffer store dword.
712 void
713 Inst_FLAT__FLAT_STORE_DWORD::execute(GPUDynInstPtr gpuDynInst)
714 {
715 Wavefront *wf = gpuDynInst->wavefront();
716
717 if (gpuDynInst->exec_mask.none()) {
718 wf->decVMemInstsIssued();
719 if (isFlat()) {
720 wf->decLGKMInstsIssued();
721 }
722 wf->decExpInstsIssued();
723 return;
724 }
725
726 gpuDynInst->execUnitId = wf->execUnitId;
727 gpuDynInst->latency.init(gpuDynInst->computeUnit());
728 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
729
730 ConstVecOperandU32 data(gpuDynInst, extData.DATA);
731
732 data.read();
733
734 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
735
736 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
737 if (gpuDynInst->exec_mask[lane]) {
738 (reinterpret_cast<VecElemU32*>(gpuDynInst->d_data))[lane]
739 = data[lane];
740 }
741 }
742
743 issueRequestHelper(gpuDynInst);
744 } // execute
745
746 void
747 Inst_FLAT__FLAT_STORE_DWORD::initiateAcc(GPUDynInstPtr gpuDynInst)
748 {
749 initMemWrite<VecElemU32>(gpuDynInst);
750 } // initiateAcc
751
752 void
753 Inst_FLAT__FLAT_STORE_DWORD::completeAcc(GPUDynInstPtr gpuDynInst)
754 {
755 } // completeAcc
756 // --- Inst_FLAT__FLAT_STORE_DWORDX2 class methods ---
757
758 Inst_FLAT__FLAT_STORE_DWORDX2::Inst_FLAT__FLAT_STORE_DWORDX2(
759 InFmt_FLAT *iFmt)
760 : Inst_FLAT(iFmt, "flat_store_dwordx2")
761 {
762 setFlag(MemoryRef);
763 setFlag(Store);
764 } // Inst_FLAT__FLAT_STORE_DWORDX2
765
766 Inst_FLAT__FLAT_STORE_DWORDX2::~Inst_FLAT__FLAT_STORE_DWORDX2()
767 {
768 } // ~Inst_FLAT__FLAT_STORE_DWORDX2
769
770 // --- description from .arch file ---
771 // Untyped buffer store 2 dwords.
772 void
773 Inst_FLAT__FLAT_STORE_DWORDX2::execute(GPUDynInstPtr gpuDynInst)
774 {
775 Wavefront *wf = gpuDynInst->wavefront();
776
777 if (gpuDynInst->exec_mask.none()) {
778 wf->decVMemInstsIssued();
779 if (isFlat()) {
780 wf->decLGKMInstsIssued();
781 }
782 wf->decExpInstsIssued();
783 return;
784 }
785
786 gpuDynInst->execUnitId = wf->execUnitId;
787 gpuDynInst->latency.init(gpuDynInst->computeUnit());
788 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
789
790 ConstVecOperandU64 data(gpuDynInst, extData.DATA);
791
792 data.read();
793
794 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
795
796 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
797 if (gpuDynInst->exec_mask[lane]) {
798 (reinterpret_cast<VecElemU64*>(gpuDynInst->d_data))[lane]
799 = data[lane];
800 }
801 }
802
803 issueRequestHelper(gpuDynInst);
804 } // execute
805
806 void
807 Inst_FLAT__FLAT_STORE_DWORDX2::initiateAcc(GPUDynInstPtr gpuDynInst)
808 {
809 initMemWrite<2>(gpuDynInst);
810 } // initiateAcc
811
812 void
813 Inst_FLAT__FLAT_STORE_DWORDX2::completeAcc(GPUDynInstPtr gpuDynInst)
814 {
815 } // completeAcc
816 // --- Inst_FLAT__FLAT_STORE_DWORDX3 class methods ---
817
818 Inst_FLAT__FLAT_STORE_DWORDX3::Inst_FLAT__FLAT_STORE_DWORDX3(
819 InFmt_FLAT *iFmt)
820 : Inst_FLAT(iFmt, "flat_store_dwordx3")
821 {
822 setFlag(MemoryRef);
823 setFlag(Store);
824 } // Inst_FLAT__FLAT_STORE_DWORDX3
825
826 Inst_FLAT__FLAT_STORE_DWORDX3::~Inst_FLAT__FLAT_STORE_DWORDX3()
827 {
828 } // ~Inst_FLAT__FLAT_STORE_DWORDX3
829
830 // --- description from .arch file ---
831 // Untyped buffer store 3 dwords.
832 void
833 Inst_FLAT__FLAT_STORE_DWORDX3::execute(GPUDynInstPtr gpuDynInst)
834 {
835 Wavefront *wf = gpuDynInst->wavefront();
836
837 if (gpuDynInst->exec_mask.none()) {
838 wf->decVMemInstsIssued();
839 if (isFlat()) {
840 wf->decLGKMInstsIssued();
841 }
842 wf->decExpInstsIssued();
843 return;
844 }
845
846 gpuDynInst->execUnitId = wf->execUnitId;
847 gpuDynInst->latency.init(gpuDynInst->computeUnit());
848 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
849
850 ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
851 ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
852 ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
853
854 data0.read();
855 data1.read();
856 data2.read();
857
858 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
859
860 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
861 if (gpuDynInst->exec_mask[lane]) {
862 (reinterpret_cast<VecElemU32*>(
863 gpuDynInst->d_data))[lane * 3] = data0[lane];
864 (reinterpret_cast<VecElemU32*>(
865 gpuDynInst->d_data))[lane * 3 + 1] = data1[lane];
866 (reinterpret_cast<VecElemU32*>(
867 gpuDynInst->d_data))[lane * 3 + 2] = data2[lane];
868 }
869 }
870
871 issueRequestHelper(gpuDynInst);
872 } // execute
873
874 void
875 Inst_FLAT__FLAT_STORE_DWORDX3::initiateAcc(GPUDynInstPtr gpuDynInst)
876 {
877 initMemWrite<3>(gpuDynInst);
878 } // initiateAcc
879
880 void
881 Inst_FLAT__FLAT_STORE_DWORDX3::completeAcc(GPUDynInstPtr gpuDynInst)
882 {
883 } // completeAcc
884 // --- Inst_FLAT__FLAT_STORE_DWORDX4 class methods ---
885
886 Inst_FLAT__FLAT_STORE_DWORDX4::Inst_FLAT__FLAT_STORE_DWORDX4(
887 InFmt_FLAT *iFmt)
888 : Inst_FLAT(iFmt, "flat_store_dwordx4")
889 {
890 setFlag(MemoryRef);
891 setFlag(Store);
892 } // Inst_FLAT__FLAT_STORE_DWORDX4
893
894 Inst_FLAT__FLAT_STORE_DWORDX4::~Inst_FLAT__FLAT_STORE_DWORDX4()
895 {
896 } // ~Inst_FLAT__FLAT_STORE_DWORDX4
897
898 // --- description from .arch file ---
899 // Untyped buffer store 4 dwords.
900 void
901 Inst_FLAT__FLAT_STORE_DWORDX4::execute(GPUDynInstPtr gpuDynInst)
902 {
903 Wavefront *wf = gpuDynInst->wavefront();
904
905 if (gpuDynInst->exec_mask.none()) {
906 wf->decVMemInstsIssued();
907 if (isFlat()) {
908 wf->decLGKMInstsIssued();
909 }
910 wf->decExpInstsIssued();
911 return;
912 }
913
914 gpuDynInst->execUnitId = wf->execUnitId;
915 gpuDynInst->latency.init(gpuDynInst->computeUnit());
916 gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
917
918 ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
919 ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
920 ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
921 ConstVecOperandU32 data3(gpuDynInst, extData.DATA + 3);
922
923 data0.read();
924 data1.read();
925 data2.read();
926 data3.read();
927
928 calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
929
930 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
931 if (gpuDynInst->exec_mask[lane]) {
932 (reinterpret_cast<VecElemU32*>(
933 gpuDynInst->d_data))[lane * 4] = data0[lane];
934 (reinterpret_cast<VecElemU32*>(
935 gpuDynInst->d_data))[lane * 4 + 1] = data1[lane];
936 (reinterpret_cast<VecElemU32*>(
937 gpuDynInst->d_data))[lane * 4 + 2] = data2[lane];
938 (reinterpret_cast<VecElemU32*>(
939 gpuDynInst->d_data))[lane * 4 + 3] = data3[lane];
940 }
941 }
942
943 issueRequestHelper(gpuDynInst);
944 } // execute
945
946 void
947 Inst_FLAT__FLAT_STORE_DWORDX4::initiateAcc(GPUDynInstPtr gpuDynInst)
948 {
949 initMemWrite<4>(gpuDynInst);
950 } // initiateAcc
951
952 void
953 Inst_FLAT__FLAT_STORE_DWORDX4::completeAcc(GPUDynInstPtr gpuDynInst)
954 {
955 } // completeAcc
956 // --- Inst_FLAT__FLAT_ATOMIC_SWAP class methods ---
957
958 Inst_FLAT__FLAT_ATOMIC_SWAP::Inst_FLAT__FLAT_ATOMIC_SWAP(InFmt_FLAT *iFmt)
959 : Inst_FLAT(iFmt, "flat_atomic_swap")
960 {
961 setFlag(AtomicExch);
962 if (instData.GLC) {
963 setFlag(AtomicReturn);
964 } else {
965 setFlag(AtomicNoReturn);
966 }
967 setFlag(MemoryRef);
968 } // Inst_FLAT__FLAT_ATOMIC_SWAP
969
970 Inst_FLAT__FLAT_ATOMIC_SWAP::~Inst_FLAT__FLAT_ATOMIC_SWAP()
971 {
972 } // ~Inst_FLAT__FLAT_ATOMIC_SWAP
973
974 // --- description from .arch file ---
975 // 32b:
976 // tmp = MEM[ADDR];
977 // MEM[ADDR] = DATA;
978 // RETURN_DATA = tmp.
979 void
980 Inst_FLAT__FLAT_ATOMIC_SWAP::execute(GPUDynInstPtr gpuDynInst)
981 {
982 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
983 } // execute
984
985 void
986 Inst_FLAT__FLAT_ATOMIC_SWAP::initiateAcc(GPUDynInstPtr gpuDynInst)
987 {
988 initAtomicAccess<VecElemU32>(gpuDynInst);
989 } // initiateAcc
990
991 void
992 Inst_FLAT__FLAT_ATOMIC_SWAP::completeAcc(GPUDynInstPtr gpuDynInst)
993 {
994 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
995 } // completeAcc
996
997 // --- Inst_FLAT__FLAT_ATOMIC_CMPSWAP class methods ---
998
999 Inst_FLAT__FLAT_ATOMIC_CMPSWAP
1000 ::Inst_FLAT__FLAT_ATOMIC_CMPSWAP(InFmt_FLAT *iFmt)
1001 : Inst_FLAT(iFmt, "flat_atomic_cmpswap")
1002 {
1003 setFlag(AtomicCAS);
1004 if (instData.GLC) {
1005 setFlag(AtomicReturn);
1006 } else {
1007 setFlag(AtomicNoReturn);
1008 }
1009 setFlag(MemoryRef);
1010 } // Inst_FLAT__FLAT_ATOMIC_CMPSWAP
1011
1012 Inst_FLAT__FLAT_ATOMIC_CMPSWAP::~Inst_FLAT__FLAT_ATOMIC_CMPSWAP()
1013 {
1014 } // ~Inst_FLAT__FLAT_ATOMIC_CMPSWAP
1015
1016 // --- description from .arch file ---
1017 // 32b:
1018 // tmp = MEM[ADDR];
1019 // src = DATA[0];
1020 // cmp = DATA[1];
1021 // MEM[ADDR] = (tmp == cmp) ? src : tmp;
1022 // RETURN_DATA[0] = tmp.
1023 void
1024 Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute(GPUDynInstPtr gpuDynInst)
1025 {
1026 atomicExecute<ConstVecOperandU32, VecElemU32, 1>(gpuDynInst);
1027 } // execute
1028
1029 void
1030 Inst_FLAT__FLAT_ATOMIC_CMPSWAP::initiateAcc(GPUDynInstPtr gpuDynInst)
1031 {
1032 initAtomicAccess<VecElemU32>(gpuDynInst);
1033 } // initiateAcc
1034
1035 void
1036 Inst_FLAT__FLAT_ATOMIC_CMPSWAP::completeAcc(GPUDynInstPtr gpuDynInst)
1037 {
1038 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1039 } // completeAcc
1040 // --- Inst_FLAT__FLAT_ATOMIC_ADD class methods ---
1041
1042 Inst_FLAT__FLAT_ATOMIC_ADD::Inst_FLAT__FLAT_ATOMIC_ADD(InFmt_FLAT *iFmt)
1043 : Inst_FLAT(iFmt, "flat_atomic_add")
1044 {
1045 setFlag(AtomicAdd);
1046 if (instData.GLC) {
1047 setFlag(AtomicReturn);
1048 } else {
1049 setFlag(AtomicNoReturn);
1050 }
1051 setFlag(MemoryRef);
1052 } // Inst_FLAT__FLAT_ATOMIC_ADD
1053
1054 Inst_FLAT__FLAT_ATOMIC_ADD::~Inst_FLAT__FLAT_ATOMIC_ADD()
1055 {
1056 } // ~Inst_FLAT__FLAT_ATOMIC_ADD
1057
1058 // --- description from .arch file ---
1059 // 32b:
1060 // tmp = MEM[ADDR];
1061 // MEM[ADDR] += DATA;
1062 // RETURN_DATA = tmp.
1063 void
1064 Inst_FLAT__FLAT_ATOMIC_ADD::execute(GPUDynInstPtr gpuDynInst)
1065 {
1066 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1067 } // execute
1068
1069 void
1070 Inst_FLAT__FLAT_ATOMIC_ADD::initiateAcc(GPUDynInstPtr gpuDynInst)
1071 {
1072 initAtomicAccess<VecElemU32>(gpuDynInst);
1073 } // initiateAcc
1074
1075 void
1076 Inst_FLAT__FLAT_ATOMIC_ADD::completeAcc(GPUDynInstPtr gpuDynInst)
1077 {
1078 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1079 } // completeAcc
1080 // --- Inst_FLAT__FLAT_ATOMIC_SUB class methods ---
1081
1082 Inst_FLAT__FLAT_ATOMIC_SUB::Inst_FLAT__FLAT_ATOMIC_SUB(InFmt_FLAT *iFmt)
1083 : Inst_FLAT(iFmt, "flat_atomic_sub")
1084 {
1085 setFlag(AtomicSub);
1086 if (instData.GLC) {
1087 setFlag(AtomicReturn);
1088 } else {
1089 setFlag(AtomicNoReturn);
1090 }
1091 setFlag(MemoryRef);
1092 } // Inst_FLAT__FLAT_ATOMIC_SUB
1093
1094 Inst_FLAT__FLAT_ATOMIC_SUB::~Inst_FLAT__FLAT_ATOMIC_SUB()
1095 {
1096 } // ~Inst_FLAT__FLAT_ATOMIC_SUB
1097
1098 // --- description from .arch file ---
1099 // 32b:
1100 // tmp = MEM[ADDR];
1101 // MEM[ADDR] -= DATA;
1102 // RETURN_DATA = tmp.
1103 void
1104 Inst_FLAT__FLAT_ATOMIC_SUB::execute(GPUDynInstPtr gpuDynInst)
1105 {
1106 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1107 } // execute
1108
1109 void
1110 Inst_FLAT__FLAT_ATOMIC_SUB::initiateAcc(GPUDynInstPtr gpuDynInst)
1111 {
1112 initAtomicAccess<VecElemU32>(gpuDynInst);
1113 } // initiateAcc
1114
1115 void
1116 Inst_FLAT__FLAT_ATOMIC_SUB::completeAcc(GPUDynInstPtr gpuDynInst)
1117 {
1118 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1119 } // completeAcc
1120 // --- Inst_FLAT__FLAT_ATOMIC_SMIN class methods ---
1121
1122 Inst_FLAT__FLAT_ATOMIC_SMIN::Inst_FLAT__FLAT_ATOMIC_SMIN(InFmt_FLAT *iFmt)
1123 : Inst_FLAT(iFmt, "flat_atomic_smin")
1124 {
1125 setFlag(AtomicMin);
1126 if (instData.GLC) {
1127 setFlag(AtomicReturn);
1128 } else {
1129 setFlag(AtomicNoReturn);
1130 }
1131 setFlag(MemoryRef);
1132 } // Inst_FLAT__FLAT_ATOMIC_SMIN
1133
1134 Inst_FLAT__FLAT_ATOMIC_SMIN::~Inst_FLAT__FLAT_ATOMIC_SMIN()
1135 {
1136 } // ~Inst_FLAT__FLAT_ATOMIC_SMIN
1137
1138 // --- description from .arch file ---
1139 // 32b:
1140 // tmp = MEM[ADDR];
1141 // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (signed compare);
1142 // RETURN_DATA = tmp.
1143 void
1144 Inst_FLAT__FLAT_ATOMIC_SMIN::execute(GPUDynInstPtr gpuDynInst)
1145 {
1146 atomicExecute<ConstVecOperandI32, VecElemI32>(gpuDynInst);
1147 } // execute
1148
1149 void
1150 Inst_FLAT__FLAT_ATOMIC_SMIN::initiateAcc(GPUDynInstPtr gpuDynInst)
1151 {
1152 initAtomicAccess<VecElemI32>(gpuDynInst);
1153 } // initiateAcc
1154
1155 void
1156 Inst_FLAT__FLAT_ATOMIC_SMIN::completeAcc(GPUDynInstPtr gpuDynInst)
1157 {
1158 atomicComplete<VecOperandI32, VecElemI32>(gpuDynInst);
1159 } // completeAcc
1160 // --- Inst_FLAT__FLAT_ATOMIC_UMIN class methods ---
1161
1162 Inst_FLAT__FLAT_ATOMIC_UMIN::Inst_FLAT__FLAT_ATOMIC_UMIN(InFmt_FLAT *iFmt)
1163 : Inst_FLAT(iFmt, "flat_atomic_umin")
1164 {
1165 setFlag(AtomicMin);
1166 if (instData.GLC) {
1167 setFlag(AtomicReturn);
1168 } else {
1169 setFlag(AtomicNoReturn);
1170 }
1171 setFlag(MemoryRef);
1172 } // Inst_FLAT__FLAT_ATOMIC_UMIN
1173
1174 Inst_FLAT__FLAT_ATOMIC_UMIN::~Inst_FLAT__FLAT_ATOMIC_UMIN()
1175 {
1176 } // ~Inst_FLAT__FLAT_ATOMIC_UMIN
1177
1178 // --- description from .arch file ---
1179 // 32b:
1180 // tmp = MEM[ADDR];
1181 // MEM[ADDR] = (DATA < tmp) ? DATA : tmp (unsigned compare);
1182 // RETURN_DATA = tmp.
1183 void
1184 Inst_FLAT__FLAT_ATOMIC_UMIN::execute(GPUDynInstPtr gpuDynInst)
1185 {
1186 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1187 } // execute
1188
1189 void
1190 Inst_FLAT__FLAT_ATOMIC_UMIN::initiateAcc(GPUDynInstPtr gpuDynInst)
1191 {
1192 initAtomicAccess<VecElemU32>(gpuDynInst);
1193 } // initiateAcc
1194
1195 void
1196 Inst_FLAT__FLAT_ATOMIC_UMIN::completeAcc(GPUDynInstPtr gpuDynInst)
1197 {
1198 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1199 } // completeAcc
1200 // --- Inst_FLAT__FLAT_ATOMIC_SMAX class methods ---
1201
1202 Inst_FLAT__FLAT_ATOMIC_SMAX::Inst_FLAT__FLAT_ATOMIC_SMAX(InFmt_FLAT *iFmt)
1203 : Inst_FLAT(iFmt, "flat_atomic_smax")
1204 {
1205 setFlag(AtomicMax);
1206 if (instData.GLC) {
1207 setFlag(AtomicReturn);
1208 } else {
1209 setFlag(AtomicNoReturn);
1210 }
1211 setFlag(MemoryRef);
1212 } // Inst_FLAT__FLAT_ATOMIC_SMAX
1213
1214 Inst_FLAT__FLAT_ATOMIC_SMAX::~Inst_FLAT__FLAT_ATOMIC_SMAX()
1215 {
1216 } // ~Inst_FLAT__FLAT_ATOMIC_SMAX
1217
1218 // --- description from .arch file ---
1219 // 32b:
1220 // tmp = MEM[ADDR];
1221 // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (signed compare);
1222 // RETURN_DATA = tmp.
1223 void
1224 Inst_FLAT__FLAT_ATOMIC_SMAX::execute(GPUDynInstPtr gpuDynInst)
1225 {
1226 atomicExecute<ConstVecOperandI32, VecElemI32>(gpuDynInst);
1227 } // execute
1228
1229 void
1230 Inst_FLAT__FLAT_ATOMIC_SMAX::initiateAcc(GPUDynInstPtr gpuDynInst)
1231 {
1232 initAtomicAccess<VecElemI32>(gpuDynInst);
1233 } // initiateAcc
1234
1235 void
1236 Inst_FLAT__FLAT_ATOMIC_SMAX::completeAcc(GPUDynInstPtr gpuDynInst)
1237 {
1238 atomicComplete<VecOperandI32, VecElemI32>(gpuDynInst);
1239 } // completeAcc
1240 // --- Inst_FLAT__FLAT_ATOMIC_UMAX class methods ---
1241
1242 Inst_FLAT__FLAT_ATOMIC_UMAX::Inst_FLAT__FLAT_ATOMIC_UMAX(InFmt_FLAT *iFmt)
1243 : Inst_FLAT(iFmt, "flat_atomic_umax")
1244 {
1245 setFlag(AtomicMax);
1246 if (instData.GLC) {
1247 setFlag(AtomicReturn);
1248 } else {
1249 setFlag(AtomicNoReturn);
1250 }
1251 setFlag(MemoryRef);
1252 } // Inst_FLAT__FLAT_ATOMIC_UMAX
1253
1254 Inst_FLAT__FLAT_ATOMIC_UMAX::~Inst_FLAT__FLAT_ATOMIC_UMAX()
1255 {
1256 } // ~Inst_FLAT__FLAT_ATOMIC_UMAX
1257
1258 // --- description from .arch file ---
1259 // 32b:
1260 // tmp = MEM[ADDR];
1261 // MEM[ADDR] = (DATA > tmp) ? DATA : tmp (unsigned compare);
1262 // RETURN_DATA = tmp.
1263 void
1264 Inst_FLAT__FLAT_ATOMIC_UMAX::execute(GPUDynInstPtr gpuDynInst)
1265 {
1266 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1267 } // execute
1268
1269 void
1270 Inst_FLAT__FLAT_ATOMIC_UMAX::initiateAcc(GPUDynInstPtr gpuDynInst)
1271 {
1272 initAtomicAccess<VecElemU32>(gpuDynInst);
1273 } // initiateAcc
1274
1275 void
1276 Inst_FLAT__FLAT_ATOMIC_UMAX::completeAcc(GPUDynInstPtr gpuDynInst)
1277 {
1278 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1279 } // completeAcc
1280 // --- Inst_FLAT__FLAT_ATOMIC_AND class methods ---
1281
1282 Inst_FLAT__FLAT_ATOMIC_AND::Inst_FLAT__FLAT_ATOMIC_AND(InFmt_FLAT *iFmt)
1283 : Inst_FLAT(iFmt, "flat_atomic_and")
1284 {
1285 setFlag(AtomicAnd);
1286 if (instData.GLC) {
1287 setFlag(AtomicReturn);
1288 } else {
1289 setFlag(AtomicNoReturn);
1290 }
1291 setFlag(MemoryRef);
1292 } // Inst_FLAT__FLAT_ATOMIC_AND
1293
1294 Inst_FLAT__FLAT_ATOMIC_AND::~Inst_FLAT__FLAT_ATOMIC_AND()
1295 {
1296 } // ~Inst_FLAT__FLAT_ATOMIC_AND
1297
1298 // --- description from .arch file ---
1299 // 32b:
1300 // tmp = MEM[ADDR];
1301 // MEM[ADDR] &= DATA;
1302 // RETURN_DATA = tmp.
1303 void
1304 Inst_FLAT__FLAT_ATOMIC_AND::execute(GPUDynInstPtr gpuDynInst)
1305 {
1306 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1307 } // execute
1308
1309 void
1310 Inst_FLAT__FLAT_ATOMIC_AND::initiateAcc(GPUDynInstPtr gpuDynInst)
1311 {
1312 initAtomicAccess<VecElemU32>(gpuDynInst);
1313 } // initiateAcc
1314
1315 void
1316 Inst_FLAT__FLAT_ATOMIC_AND::completeAcc(GPUDynInstPtr gpuDynInst)
1317 {
1318 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1319 } // completeAcc
1320 // --- Inst_FLAT__FLAT_ATOMIC_OR class methods ---
1321
1322 Inst_FLAT__FLAT_ATOMIC_OR::Inst_FLAT__FLAT_ATOMIC_OR(InFmt_FLAT *iFmt)
1323 : Inst_FLAT(iFmt, "flat_atomic_or")
1324 {
1325 setFlag(AtomicOr);
1326 if (instData.GLC) {
1327 setFlag(AtomicReturn);
1328 } else {
1329 setFlag(AtomicNoReturn);
1330 }
1331 setFlag(MemoryRef);
1332 } // Inst_FLAT__FLAT_ATOMIC_OR
1333
1334 Inst_FLAT__FLAT_ATOMIC_OR::~Inst_FLAT__FLAT_ATOMIC_OR()
1335 {
1336 } // ~Inst_FLAT__FLAT_ATOMIC_OR
1337
1338 // --- description from .arch file ---
1339 // 32b:
1340 // tmp = MEM[ADDR];
1341 // MEM[ADDR] |= DATA;
1342 // RETURN_DATA = tmp.
1343 void
1344 Inst_FLAT__FLAT_ATOMIC_OR::execute(GPUDynInstPtr gpuDynInst)
1345 {
1346 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1347 } // execute
1348
1349 void
1350 Inst_FLAT__FLAT_ATOMIC_OR::initiateAcc(GPUDynInstPtr gpuDynInst)
1351 {
1352 initAtomicAccess<VecElemU32>(gpuDynInst);
1353 } // initiateAcc
1354
1355 void
1356 Inst_FLAT__FLAT_ATOMIC_OR::completeAcc(GPUDynInstPtr gpuDynInst)
1357 {
1358 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1359 } // completeAcc
1360
1361 // --- Inst_FLAT__FLAT_ATOMIC_XOR class methods ---
1362
1363 Inst_FLAT__FLAT_ATOMIC_XOR::Inst_FLAT__FLAT_ATOMIC_XOR(InFmt_FLAT *iFmt)
1364 : Inst_FLAT(iFmt, "flat_atomic_xor")
1365 {
1366 setFlag(AtomicXor);
1367 if (instData.GLC) {
1368 setFlag(AtomicReturn);
1369 } else {
1370 setFlag(AtomicNoReturn);
1371 }
1372 setFlag(MemoryRef);
1373 } // Inst_FLAT__FLAT_ATOMIC_XOR
1374
1375 Inst_FLAT__FLAT_ATOMIC_XOR::~Inst_FLAT__FLAT_ATOMIC_XOR()
1376 {
1377 } // ~Inst_FLAT__FLAT_ATOMIC_XOR
1378
1379 // --- description from .arch file ---
1380 // 32b:
1381 // tmp = MEM[ADDR];
1382 // MEM[ADDR] ^= DATA;
1383 // RETURN_DATA = tmp.
1384 void
1385 Inst_FLAT__FLAT_ATOMIC_XOR::execute(GPUDynInstPtr gpuDynInst)
1386 {
1387 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1388 } // execute
1389
1390 void
1391 Inst_FLAT__FLAT_ATOMIC_XOR::initiateAcc(GPUDynInstPtr gpuDynInst)
1392 {
1393 initAtomicAccess<VecElemU32>(gpuDynInst);
1394 } // initiateAcc
1395
1396 void
1397 Inst_FLAT__FLAT_ATOMIC_XOR::completeAcc(GPUDynInstPtr gpuDynInst)
1398 {
1399 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1400 } // completeAcc
1401 // --- Inst_FLAT__FLAT_ATOMIC_INC class methods ---
1402
1403 Inst_FLAT__FLAT_ATOMIC_INC::Inst_FLAT__FLAT_ATOMIC_INC(InFmt_FLAT *iFmt)
1404 : Inst_FLAT(iFmt, "flat_atomic_inc")
1405 {
1406 setFlag(AtomicInc);
1407 if (instData.GLC) {
1408 setFlag(AtomicReturn);
1409 } else {
1410 setFlag(AtomicNoReturn);
1411 }
1412 setFlag(MemoryRef);
1413 } // Inst_FLAT__FLAT_ATOMIC_INC
1414
1415 Inst_FLAT__FLAT_ATOMIC_INC::~Inst_FLAT__FLAT_ATOMIC_INC()
1416 {
1417 } // ~Inst_FLAT__FLAT_ATOMIC_INC
1418
1419 // --- description from .arch file ---
1420 // 32b:
1421 // tmp = MEM[ADDR];
1422 // MEM[ADDR] = (tmp >= DATA) ? 0 : tmp + 1 (unsigned compare);
1423 // RETURN_DATA = tmp.
1424 void
1425 Inst_FLAT__FLAT_ATOMIC_INC::execute(GPUDynInstPtr gpuDynInst)
1426 {
1427 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1428 } // execute
1429
1430 void
1431 Inst_FLAT__FLAT_ATOMIC_INC::initiateAcc(GPUDynInstPtr gpuDynInst)
1432 {
1433 initAtomicAccess<VecElemU32>(gpuDynInst);
1434 } // initiateAcc
1435
1436 void
1437 Inst_FLAT__FLAT_ATOMIC_INC::completeAcc(GPUDynInstPtr gpuDynInst)
1438 {
1439 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1440 } // completeAcc
1441 // --- Inst_FLAT__FLAT_ATOMIC_DEC class methods ---
1442
1443 Inst_FLAT__FLAT_ATOMIC_DEC::Inst_FLAT__FLAT_ATOMIC_DEC(InFmt_FLAT *iFmt)
1444 : Inst_FLAT(iFmt, "flat_atomic_dec")
1445 {
1446 setFlag(AtomicDec);
1447 if (instData.GLC) {
1448 setFlag(AtomicReturn);
1449 } else {
1450 setFlag(AtomicNoReturn);
1451 }
1452 setFlag(MemoryRef);
1453 } // Inst_FLAT__FLAT_ATOMIC_DEC
1454
1455 Inst_FLAT__FLAT_ATOMIC_DEC::~Inst_FLAT__FLAT_ATOMIC_DEC()
1456 {
1457 } // ~Inst_FLAT__FLAT_ATOMIC_DEC
1458
1459 // --- description from .arch file ---
1460 // 32b:
1461 // tmp = MEM[ADDR];
1462 // MEM[ADDR] = (tmp == 0 || tmp > DATA) ? DATA : tmp - 1
1463 // (unsigned compare); RETURN_DATA = tmp.
1464 void
1465 Inst_FLAT__FLAT_ATOMIC_DEC::execute(GPUDynInstPtr gpuDynInst)
1466 {
1467 atomicExecute<ConstVecOperandU32, VecElemU32>(gpuDynInst);
1468 } // execute
1469
1470 void
1471 Inst_FLAT__FLAT_ATOMIC_DEC::initiateAcc(GPUDynInstPtr gpuDynInst)
1472 {
1473 initAtomicAccess<VecElemU32>(gpuDynInst);
1474 } // initiateAcc
1475
1476 void
1477 Inst_FLAT__FLAT_ATOMIC_DEC::completeAcc(GPUDynInstPtr gpuDynInst)
1478 {
1479 atomicComplete<VecOperandU32, VecElemU32>(gpuDynInst);
1480 } // completeAcc
1481 // --- Inst_FLAT__FLAT_ATOMIC_SWAP_X2 class methods ---
1482
1483 Inst_FLAT__FLAT_ATOMIC_SWAP_X2::Inst_FLAT__FLAT_ATOMIC_SWAP_X2(
1484 InFmt_FLAT *iFmt)
1485 : Inst_FLAT(iFmt, "flat_atomic_swap_x2")
1486 {
1487 setFlag(AtomicExch);
1488 if (instData.GLC) {
1489 setFlag(AtomicReturn);
1490 } else {
1491 setFlag(AtomicNoReturn);
1492 }
1493 setFlag(MemoryRef);
1494 } // Inst_FLAT__FLAT_ATOMIC_SWAP_X2
1495
1496 Inst_FLAT__FLAT_ATOMIC_SWAP_X2::~Inst_FLAT__FLAT_ATOMIC_SWAP_X2()
1497 {
1498 } // ~Inst_FLAT__FLAT_ATOMIC_SWAP_X2
1499
1500 // --- description from .arch file ---
1501 // 64b:
1502 // tmp = MEM[ADDR];
1503 // MEM[ADDR] = DATA[0:1];
1504 // RETURN_DATA[0:1] = tmp.
1505 void
1506 Inst_FLAT__FLAT_ATOMIC_SWAP_X2::execute(GPUDynInstPtr gpuDynInst)
1507 {
1508 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1509 } // execute
1510
1511 void
1512 Inst_FLAT__FLAT_ATOMIC_SWAP_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1513 {
1514 initAtomicAccess<VecElemU64>(gpuDynInst);
1515 } // initiateAcc
1516
1517 void
1518 Inst_FLAT__FLAT_ATOMIC_SWAP_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1519 {
1520 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1521 } // completeAcc
1522 // --- Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2 class methods ---
1523
1524 Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(
1525 InFmt_FLAT *iFmt)
1526 : Inst_FLAT(iFmt, "flat_atomic_cmpswap_x2")
1527 {
1528 setFlag(AtomicCAS);
1529 if (instData.GLC) {
1530 setFlag(AtomicReturn);
1531 } else {
1532 setFlag(AtomicNoReturn);
1533 }
1534 setFlag(MemoryRef);
1535 } // Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
1536
1537 Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2()
1538 {
1539 } // ~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
1540
1541 // --- description from .arch file ---
1542 // 64b:
1543 // tmp = MEM[ADDR];
1544 // src = DATA[0:1];
1545 // cmp = DATA[2:3];
1546 // MEM[ADDR] = (tmp == cmp) ? src : tmp;
1547 // RETURN_DATA[0:1] = tmp.
1548 void
1549 Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute(GPUDynInstPtr gpuDynInst)
1550 {
1551 atomicExecute<ConstVecOperandU64, VecElemU64, 2>(gpuDynInst);
1552 } // execute
1553
1554 void
1555 Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1556 {
1557 initAtomicAccess<VecElemU64>(gpuDynInst);
1558 } // initiateAcc
1559
1560 void
1561 Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1562 {
1563 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1564 } // completeAcc
1565 // --- Inst_FLAT__FLAT_ATOMIC_ADD_X2 class methods ---
1566
1567 Inst_FLAT__FLAT_ATOMIC_ADD_X2::Inst_FLAT__FLAT_ATOMIC_ADD_X2(
1568 InFmt_FLAT *iFmt)
1569 : Inst_FLAT(iFmt, "flat_atomic_add_x2")
1570 {
1571 setFlag(AtomicAdd);
1572 if (instData.GLC) {
1573 setFlag(AtomicReturn);
1574 } else {
1575 setFlag(AtomicNoReturn);
1576 }
1577 setFlag(MemoryRef);
1578 } // Inst_FLAT__FLAT_ATOMIC_ADD_X2
1579
1580 Inst_FLAT__FLAT_ATOMIC_ADD_X2::~Inst_FLAT__FLAT_ATOMIC_ADD_X2()
1581 {
1582 } // ~Inst_FLAT__FLAT_ATOMIC_ADD_X2
1583
1584 // --- description from .arch file ---
1585 // 64b:
1586 // tmp = MEM[ADDR];
1587 // MEM[ADDR] += DATA[0:1];
1588 // RETURN_DATA[0:1] = tmp.
1589 void
1590 Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute(GPUDynInstPtr gpuDynInst)
1591 {
1592 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1593 } // execute
1594
1595 void
1596 Inst_FLAT__FLAT_ATOMIC_ADD_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1597 {
1598 initAtomicAccess<VecElemU64>(gpuDynInst);
1599 } // initiateAcc
1600
1601 void
1602 Inst_FLAT__FLAT_ATOMIC_ADD_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1603 {
1604 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1605 } // completeAcc
1606 // --- Inst_FLAT__FLAT_ATOMIC_SUB_X2 class methods ---
1607
1608 Inst_FLAT__FLAT_ATOMIC_SUB_X2::Inst_FLAT__FLAT_ATOMIC_SUB_X2(
1609 InFmt_FLAT *iFmt)
1610 : Inst_FLAT(iFmt, "flat_atomic_sub_x2")
1611 {
1612 setFlag(AtomicSub);
1613 if (instData.GLC) {
1614 setFlag(AtomicReturn);
1615 } else {
1616 setFlag(AtomicNoReturn);
1617 }
1618 setFlag(MemoryRef);
1619 } // Inst_FLAT__FLAT_ATOMIC_SUB_X2
1620
1621 Inst_FLAT__FLAT_ATOMIC_SUB_X2::~Inst_FLAT__FLAT_ATOMIC_SUB_X2()
1622 {
1623 } // ~Inst_FLAT__FLAT_ATOMIC_SUB_X2
1624
1625 // --- description from .arch file ---
1626 // 64b:
1627 // tmp = MEM[ADDR];
1628 // MEM[ADDR] -= DATA[0:1];
1629 // RETURN_DATA[0:1] = tmp.
1630 void
1631 Inst_FLAT__FLAT_ATOMIC_SUB_X2::execute(GPUDynInstPtr gpuDynInst)
1632 {
1633 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1634 } // execute
1635
1636 void
1637 Inst_FLAT__FLAT_ATOMIC_SUB_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1638 {
1639 initAtomicAccess<VecElemU64>(gpuDynInst);
1640 } // initiateAcc
1641
1642 void
1643 Inst_FLAT__FLAT_ATOMIC_SUB_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1644 {
1645 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1646 } // completeAcc
1647 // --- Inst_FLAT__FLAT_ATOMIC_SMIN_X2 class methods ---
1648
1649 Inst_FLAT__FLAT_ATOMIC_SMIN_X2::Inst_FLAT__FLAT_ATOMIC_SMIN_X2(
1650 InFmt_FLAT *iFmt)
1651 : Inst_FLAT(iFmt, "flat_atomic_smin_x2")
1652 {
1653 setFlag(AtomicMin);
1654 if (instData.GLC) {
1655 setFlag(AtomicReturn);
1656 } else {
1657 setFlag(AtomicNoReturn);
1658 }
1659 setFlag(MemoryRef);
1660 } // Inst_FLAT__FLAT_ATOMIC_SMIN_X2
1661
1662 Inst_FLAT__FLAT_ATOMIC_SMIN_X2::~Inst_FLAT__FLAT_ATOMIC_SMIN_X2()
1663 {
1664 } // ~Inst_FLAT__FLAT_ATOMIC_SMIN_X2
1665
1666 // --- description from .arch file ---
1667 // 64b:
1668 // tmp = MEM[ADDR];
1669 // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (signed compare);
1670 // RETURN_DATA[0:1] = tmp.
1671 void
1672 Inst_FLAT__FLAT_ATOMIC_SMIN_X2::execute(GPUDynInstPtr gpuDynInst)
1673 {
1674 atomicExecute<ConstVecOperandI64, VecElemI64>(gpuDynInst);
1675 } // execute
1676
1677 void
1678 Inst_FLAT__FLAT_ATOMIC_SMIN_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1679 {
1680 initAtomicAccess<VecElemI64>(gpuDynInst);
1681 } // initiateAcc
1682
1683 void
1684 Inst_FLAT__FLAT_ATOMIC_SMIN_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1685 {
1686 atomicComplete<VecOperandI64, VecElemI64>(gpuDynInst);
1687 } // completeAcc
1688 // --- Inst_FLAT__FLAT_ATOMIC_UMIN_X2 class methods ---
1689
1690 Inst_FLAT__FLAT_ATOMIC_UMIN_X2::Inst_FLAT__FLAT_ATOMIC_UMIN_X2(
1691 InFmt_FLAT *iFmt)
1692 : Inst_FLAT(iFmt, "flat_atomic_umin_x2")
1693 {
1694 setFlag(AtomicMin);
1695 if (instData.GLC) {
1696 setFlag(AtomicReturn);
1697 } else {
1698 setFlag(AtomicNoReturn);
1699 }
1700 setFlag(MemoryRef);
1701 } // Inst_FLAT__FLAT_ATOMIC_UMIN_X2
1702
1703 Inst_FLAT__FLAT_ATOMIC_UMIN_X2::~Inst_FLAT__FLAT_ATOMIC_UMIN_X2()
1704 {
1705 } // ~Inst_FLAT__FLAT_ATOMIC_UMIN_X2
1706
1707 // --- description from .arch file ---
1708 // 64b:
1709 // tmp = MEM[ADDR];
1710 // MEM[ADDR] -= (DATA[0:1] < tmp) ? DATA[0:1] : tmp (unsigned compare);
1711 // RETURN_DATA[0:1] = tmp.
1712 void
1713 Inst_FLAT__FLAT_ATOMIC_UMIN_X2::execute(GPUDynInstPtr gpuDynInst)
1714 {
1715 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1716 } // execute
1717
1718 void
1719 Inst_FLAT__FLAT_ATOMIC_UMIN_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1720 {
1721 initAtomicAccess<VecElemU64>(gpuDynInst);
1722 } // initiateAcc
1723
1724 void
1725 Inst_FLAT__FLAT_ATOMIC_UMIN_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1726 {
1727 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1728 } // completeAcc
1729 // --- Inst_FLAT__FLAT_ATOMIC_SMAX_X2 class methods ---
1730
1731 Inst_FLAT__FLAT_ATOMIC_SMAX_X2::Inst_FLAT__FLAT_ATOMIC_SMAX_X2(
1732 InFmt_FLAT *iFmt)
1733 : Inst_FLAT(iFmt, "flat_atomic_smax_x2")
1734 {
1735 setFlag(AtomicMax);
1736 if (instData.GLC) {
1737 setFlag(AtomicReturn);
1738 } else {
1739 setFlag(AtomicNoReturn);
1740 }
1741 setFlag(MemoryRef);
1742 } // Inst_FLAT__FLAT_ATOMIC_SMAX_X2
1743
1744 Inst_FLAT__FLAT_ATOMIC_SMAX_X2::~Inst_FLAT__FLAT_ATOMIC_SMAX_X2()
1745 {
1746 } // ~Inst_FLAT__FLAT_ATOMIC_SMAX_X2
1747
1748 // --- description from .arch file ---
1749 // 64b:
1750 // tmp = MEM[ADDR];
1751 // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (signed compare);
1752 // RETURN_DATA[0:1] = tmp.
1753 void
1754 Inst_FLAT__FLAT_ATOMIC_SMAX_X2::execute(GPUDynInstPtr gpuDynInst)
1755 {
1756 atomicExecute<ConstVecOperandI64, VecElemI64>(gpuDynInst);
1757 } // execute
1758
1759 void
1760 Inst_FLAT__FLAT_ATOMIC_SMAX_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1761 {
1762 initAtomicAccess<VecElemI64>(gpuDynInst);
1763 } // initiateAcc
1764
1765 void
1766 Inst_FLAT__FLAT_ATOMIC_SMAX_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1767 {
1768 atomicComplete<VecOperandI64, VecElemI64>(gpuDynInst);
1769 } // completeAcc
1770 // --- Inst_FLAT__FLAT_ATOMIC_UMAX_X2 class methods ---
1771
1772 Inst_FLAT__FLAT_ATOMIC_UMAX_X2::Inst_FLAT__FLAT_ATOMIC_UMAX_X2(
1773 InFmt_FLAT *iFmt)
1774 : Inst_FLAT(iFmt, "flat_atomic_umax_x2")
1775 {
1776 setFlag(AtomicMax);
1777 if (instData.GLC) {
1778 setFlag(AtomicReturn);
1779 } else {
1780 setFlag(AtomicNoReturn);
1781 }
1782 setFlag(MemoryRef);
1783 } // Inst_FLAT__FLAT_ATOMIC_UMAX_X2
1784
1785 Inst_FLAT__FLAT_ATOMIC_UMAX_X2::~Inst_FLAT__FLAT_ATOMIC_UMAX_X2()
1786 {
1787 } // ~Inst_FLAT__FLAT_ATOMIC_UMAX_X2
1788
1789 // --- description from .arch file ---
1790 // 64b:
1791 // tmp = MEM[ADDR];
1792 // MEM[ADDR] -= (DATA[0:1] > tmp) ? DATA[0:1] : tmp (unsigned compare);
1793 // RETURN_DATA[0:1] = tmp.
1794 void
1795 Inst_FLAT__FLAT_ATOMIC_UMAX_X2::execute(GPUDynInstPtr gpuDynInst)
1796 {
1797 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1798 } // execute
1799
1800 void
1801 Inst_FLAT__FLAT_ATOMIC_UMAX_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1802 {
1803 initAtomicAccess<VecElemU64>(gpuDynInst);
1804 } // initiateAcc
1805
1806 void
1807 Inst_FLAT__FLAT_ATOMIC_UMAX_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1808 {
1809 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1810 } // completeAcc
1811 // --- Inst_FLAT__FLAT_ATOMIC_AND_X2 class methods ---
1812
1813 Inst_FLAT__FLAT_ATOMIC_AND_X2::Inst_FLAT__FLAT_ATOMIC_AND_X2(
1814 InFmt_FLAT *iFmt)
1815 : Inst_FLAT(iFmt, "flat_atomic_and_x2")
1816 {
1817 setFlag(AtomicAnd);
1818 if (instData.GLC) {
1819 setFlag(AtomicReturn);
1820 } else {
1821 setFlag(AtomicNoReturn);
1822 }
1823 setFlag(MemoryRef);
1824 } // Inst_FLAT__FLAT_ATOMIC_AND_X2
1825
1826 Inst_FLAT__FLAT_ATOMIC_AND_X2::~Inst_FLAT__FLAT_ATOMIC_AND_X2()
1827 {
1828 } // ~Inst_FLAT__FLAT_ATOMIC_AND_X2
1829
1830 // --- description from .arch file ---
1831 // 64b:
1832 // tmp = MEM[ADDR];
1833 // MEM[ADDR] &= DATA[0:1];
1834 // RETURN_DATA[0:1] = tmp.
1835 void
1836 Inst_FLAT__FLAT_ATOMIC_AND_X2::execute(GPUDynInstPtr gpuDynInst)
1837 {
1838 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1839 } // execute
1840
1841 void
1842 Inst_FLAT__FLAT_ATOMIC_AND_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1843 {
1844 initAtomicAccess<VecElemU64>(gpuDynInst);
1845 } // initiateAcc
1846
1847 void
1848 Inst_FLAT__FLAT_ATOMIC_AND_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1849 {
1850 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1851 } // completeAcc
1852 // --- Inst_FLAT__FLAT_ATOMIC_OR_X2 class methods ---
1853
1854 Inst_FLAT__FLAT_ATOMIC_OR_X2::Inst_FLAT__FLAT_ATOMIC_OR_X2(
1855 InFmt_FLAT *iFmt)
1856 : Inst_FLAT(iFmt, "flat_atomic_or_x2")
1857 {
1858 setFlag(AtomicOr);
1859 if (instData.GLC) {
1860 setFlag(AtomicReturn);
1861 } else {
1862 setFlag(AtomicNoReturn);
1863 }
1864 setFlag(MemoryRef);
1865 } // Inst_FLAT__FLAT_ATOMIC_OR_X2
1866
1867 Inst_FLAT__FLAT_ATOMIC_OR_X2::~Inst_FLAT__FLAT_ATOMIC_OR_X2()
1868 {
1869 } // ~Inst_FLAT__FLAT_ATOMIC_OR_X2
1870
1871 // --- description from .arch file ---
1872 // 64b:
1873 // tmp = MEM[ADDR];
1874 // MEM[ADDR] |= DATA[0:1];
1875 // RETURN_DATA[0:1] = tmp.
1876 void
1877 Inst_FLAT__FLAT_ATOMIC_OR_X2::execute(GPUDynInstPtr gpuDynInst)
1878 {
1879 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1880 } // execute
1881
1882 void
1883 Inst_FLAT__FLAT_ATOMIC_OR_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1884 {
1885 initAtomicAccess<VecElemU64>(gpuDynInst);
1886 } // initiateAcc
1887
1888 void
1889 Inst_FLAT__FLAT_ATOMIC_OR_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1890 {
1891 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1892 } // completeAcc
1893 // --- Inst_FLAT__FLAT_ATOMIC_XOR_X2 class methods ---
1894
1895 Inst_FLAT__FLAT_ATOMIC_XOR_X2::Inst_FLAT__FLAT_ATOMIC_XOR_X2(
1896 InFmt_FLAT *iFmt)
1897 : Inst_FLAT(iFmt, "flat_atomic_xor_x2")
1898 {
1899 setFlag(AtomicXor);
1900 if (instData.GLC) {
1901 setFlag(AtomicReturn);
1902 } else {
1903 setFlag(AtomicNoReturn);
1904 }
1905 setFlag(MemoryRef);
1906 } // Inst_FLAT__FLAT_ATOMIC_XOR_X2
1907
1908 Inst_FLAT__FLAT_ATOMIC_XOR_X2::~Inst_FLAT__FLAT_ATOMIC_XOR_X2()
1909 {
1910 } // ~Inst_FLAT__FLAT_ATOMIC_XOR_X2
1911
1912 // --- description from .arch file ---
1913 // 64b:
1914 // tmp = MEM[ADDR];
1915 // MEM[ADDR] ^= DATA[0:1];
1916 // RETURN_DATA[0:1] = tmp.
1917 void
1918 Inst_FLAT__FLAT_ATOMIC_XOR_X2::execute(GPUDynInstPtr gpuDynInst)
1919 {
1920 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1921 } // execute
1922
1923 void
1924 Inst_FLAT__FLAT_ATOMIC_XOR_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1925 {
1926 initAtomicAccess<VecElemU64>(gpuDynInst);
1927 } // initiateAcc
1928
1929 void
1930 Inst_FLAT__FLAT_ATOMIC_XOR_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1931 {
1932 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1933 } // completeAcc
1934 // --- Inst_FLAT__FLAT_ATOMIC_INC_X2 class methods ---
1935
1936 Inst_FLAT__FLAT_ATOMIC_INC_X2::Inst_FLAT__FLAT_ATOMIC_INC_X2(
1937 InFmt_FLAT *iFmt)
1938 : Inst_FLAT(iFmt, "flat_atomic_inc_x2")
1939 {
1940 setFlag(AtomicInc);
1941 if (instData.GLC) {
1942 setFlag(AtomicReturn);
1943 } else {
1944 setFlag(AtomicNoReturn);
1945 }
1946 setFlag(MemoryRef);
1947 } // Inst_FLAT__FLAT_ATOMIC_INC_X2
1948
1949 Inst_FLAT__FLAT_ATOMIC_INC_X2::~Inst_FLAT__FLAT_ATOMIC_INC_X2()
1950 {
1951 } // ~Inst_FLAT__FLAT_ATOMIC_INC_X2
1952
1953 // --- description from .arch file ---
1954 // 64b:
1955 // tmp = MEM[ADDR];
1956 // MEM[ADDR] = (tmp >= DATA[0:1]) ? 0 : tmp + 1 (unsigned compare);
1957 // RETURN_DATA[0:1] = tmp.
1958 void
1959 Inst_FLAT__FLAT_ATOMIC_INC_X2::execute(GPUDynInstPtr gpuDynInst)
1960 {
1961 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
1962 } // execute
1963
1964 void
1965 Inst_FLAT__FLAT_ATOMIC_INC_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
1966 {
1967 initAtomicAccess<VecElemU64>(gpuDynInst);
1968 } // initiateAcc
1969
1970 void
1971 Inst_FLAT__FLAT_ATOMIC_INC_X2::completeAcc(GPUDynInstPtr gpuDynInst)
1972 {
1973 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
1974 } // completeAcc
1975 // --- Inst_FLAT__FLAT_ATOMIC_DEC_X2 class methods ---
1976
1977 Inst_FLAT__FLAT_ATOMIC_DEC_X2::Inst_FLAT__FLAT_ATOMIC_DEC_X2(
1978 InFmt_FLAT *iFmt)
1979 : Inst_FLAT(iFmt, "flat_atomic_dec_x2")
1980 {
1981 setFlag(AtomicDec);
1982 if (instData.GLC) {
1983 setFlag(AtomicReturn);
1984 } else {
1985 setFlag(AtomicNoReturn);
1986 }
1987 setFlag(MemoryRef);
1988 } // Inst_FLAT__FLAT_ATOMIC_DEC_X2
1989
1990 Inst_FLAT__FLAT_ATOMIC_DEC_X2::~Inst_FLAT__FLAT_ATOMIC_DEC_X2()
1991 {
1992 } // ~Inst_FLAT__FLAT_ATOMIC_DEC_X2
1993
1994 // --- description from .arch file ---
1995 // 64b:
1996 // tmp = MEM[ADDR];
1997 // MEM[ADDR] = (tmp == 0 || tmp > DATA[0:1]) ? DATA[0:1] : tmp - 1
1998 // (unsigned compare);
1999 // RETURN_DATA[0:1] = tmp.
2000 void
2001 Inst_FLAT__FLAT_ATOMIC_DEC_X2::execute(GPUDynInstPtr gpuDynInst)
2002 {
2003 atomicExecute<ConstVecOperandU64, VecElemU64>(gpuDynInst);
2004 } // execute
2005
2006 void
2007 Inst_FLAT__FLAT_ATOMIC_DEC_X2::initiateAcc(GPUDynInstPtr gpuDynInst)
2008 {
2009 initAtomicAccess<VecElemU64>(gpuDynInst);
2010 } // initiateAcc
2011
2012 void
2013 Inst_FLAT__FLAT_ATOMIC_DEC_X2::completeAcc(GPUDynInstPtr gpuDynInst)
2014 {
2015 atomicComplete<VecOperandU64, VecElemU64>(gpuDynInst);
2016 } // completeAcc
2017 // --- Inst_FLAT__FLAT_ATOMIC_ADD_F32 class methods ---
2018
2019 Inst_FLAT__FLAT_ATOMIC_ADD_F32::Inst_FLAT__FLAT_ATOMIC_ADD_F32(
2020 InFmt_FLAT *iFmt)
2021 : Inst_FLAT(iFmt, "flat_atomic_add_f32")
2022 {
2023 setFlag(AtomicAdd);
2024 if (instData.GLC) {
2025 setFlag(AtomicReturn);
2026 } else {
2027 setFlag(AtomicNoReturn);
2028 }
2029 setFlag(MemoryRef);
2030 } // Inst_FLAT__FLAT_ATOMIC_ADD_F32
2031
2032 Inst_FLAT__FLAT_ATOMIC_ADD_F32::~Inst_FLAT__FLAT_ATOMIC_ADD_F32()
2033 {
2034 } // ~Inst_FLAT__FLAT_ATOMIC_ADD_F32
2035
2036 void
2037 Inst_FLAT__FLAT_ATOMIC_ADD_F32::execute(GPUDynInstPtr gpuDynInst)
2038 {
2039 atomicExecute<ConstVecOperandF32, VecElemF32>(gpuDynInst);
2040 } // execute
2041
2042 void
2043 Inst_FLAT__FLAT_ATOMIC_ADD_F32::initiateAcc(GPUDynInstPtr gpuDynInst)
2044 {
2045 initAtomicAccess<VecElemF32>(gpuDynInst);
2046 } // initiateAcc
2047
2048 void
2049 Inst_FLAT__FLAT_ATOMIC_ADD_F32::completeAcc(GPUDynInstPtr gpuDynInst)
2050 {
2051 atomicComplete<VecOperandF32, VecElemF32>(gpuDynInst);
2052 } // completeAcc
2053 // --- Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16 class methods ---
2054
2055 Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16(
2056 InFmt_FLAT *iFmt)
2057 : Inst_FLAT(iFmt, "flat_atomic_pk_add_f16")
2058 {
2059 setFlag(AtomicAdd);
2060 if (instData.GLC) {
2061 setFlag(AtomicReturn);
2062 } else {
2063 setFlag(AtomicNoReturn);
2064 }
2065 setFlag(MemoryRef);
2066 } // Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16
2067
2068 Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::~Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16()
2069 {
2070 } // ~Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16
2071
2072 void
2077
2078 void
2079 Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::initiateAcc(GPUDynInstPtr gpuDynInst)
2080 {
2081 } // initiateAcc
2082
2083 void
2084 Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::completeAcc(GPUDynInstPtr gpuDynInst)
2085 {
2086 } // completeAcc
2087 // --- Inst_FLAT__FLAT_ATOMIC_ADD_F64 class methods ---
2088
2089 Inst_FLAT__FLAT_ATOMIC_ADD_F64::Inst_FLAT__FLAT_ATOMIC_ADD_F64(
2090 InFmt_FLAT *iFmt)
2091 : Inst_FLAT(iFmt, "flat_atomic_add_f64")
2092 {
2093 setFlag(AtomicAdd);
2094 if (instData.GLC) {
2095 setFlag(AtomicReturn);
2096 } else {
2097 setFlag(AtomicNoReturn);
2098 }
2099 setFlag(MemoryRef);
2100 } // Inst_FLAT__FLAT_ATOMIC_ADD_F64
2101
2102 Inst_FLAT__FLAT_ATOMIC_ADD_F64::~Inst_FLAT__FLAT_ATOMIC_ADD_F64()
2103 {
2104 } // ~Inst_FLAT__FLAT_ATOMIC_ADD_F64
2105
2106 void
2107 Inst_FLAT__FLAT_ATOMIC_ADD_F64::execute(GPUDynInstPtr gpuDynInst)
2108 {
2109 atomicExecute<ConstVecOperandF64, VecElemF64>(gpuDynInst);
2110 } // execute
2111
2112 void
2113 Inst_FLAT__FLAT_ATOMIC_ADD_F64::initiateAcc(GPUDynInstPtr gpuDynInst)
2114 {
2115 initAtomicAccess<VecElemF64>(gpuDynInst);
2116 } // initiateAcc
2117
2118 void
2119 Inst_FLAT__FLAT_ATOMIC_ADD_F64::completeAcc(GPUDynInstPtr gpuDynInst)
2120 {
2121 atomicComplete<VecOperandF64, VecElemF64>(gpuDynInst);
2122 } // completeAcc
2123 // --- Inst_FLAT__FLAT_ATOMIC_MIN_F64 class methods ---
2124
2125 Inst_FLAT__FLAT_ATOMIC_MIN_F64::Inst_FLAT__FLAT_ATOMIC_MIN_F64(
2126 InFmt_FLAT *iFmt)
2127 : Inst_FLAT(iFmt, "flat_atomic_min_f64")
2128 {
2129 setFlag(AtomicMin);
2130 if (instData.GLC) {
2131 setFlag(AtomicReturn);
2132 } else {
2133 setFlag(AtomicNoReturn);
2134 }
2135 setFlag(MemoryRef);
2136 } // Inst_FLAT__FLAT_ATOMIC_MIN_F64
2137
2138 Inst_FLAT__FLAT_ATOMIC_MIN_F64::~Inst_FLAT__FLAT_ATOMIC_MIN_F64()
2139 {
2140 } // ~Inst_FLAT__FLAT_ATOMIC_MIN_F64
2141
2142 void
2143 Inst_FLAT__FLAT_ATOMIC_MIN_F64::execute(GPUDynInstPtr gpuDynInst)
2144 {
2145 atomicExecute<ConstVecOperandF64, VecElemF64>(gpuDynInst);
2146 } // execute
2147
2148 void
2149 Inst_FLAT__FLAT_ATOMIC_MIN_F64::initiateAcc(GPUDynInstPtr gpuDynInst)
2150 {
2151 initAtomicAccess<VecElemF64>(gpuDynInst);
2152 } // initiateAcc
2153
2154 void
2155 Inst_FLAT__FLAT_ATOMIC_MIN_F64::completeAcc(GPUDynInstPtr gpuDynInst)
2156 {
2157 atomicComplete<VecOperandF64, VecElemF64>(gpuDynInst);
2158 } // completeAcc
2159 // --- Inst_FLAT__FLAT_ATOMIC_MAX_F64 class methods ---
2160
2161 Inst_FLAT__FLAT_ATOMIC_MAX_F64::Inst_FLAT__FLAT_ATOMIC_MAX_F64(
2162 InFmt_FLAT *iFmt)
2163 : Inst_FLAT(iFmt, "flat_atomic_max_f64")
2164 {
2165 setFlag(AtomicMax);
2166 if (instData.GLC) {
2167 setFlag(AtomicReturn);
2168 } else {
2169 setFlag(AtomicNoReturn);
2170 }
2171 setFlag(MemoryRef);
2172 } // Inst_FLAT__FLAT_ATOMIC_MAX_F64
2173
2174 Inst_FLAT__FLAT_ATOMIC_MAX_F64::~Inst_FLAT__FLAT_ATOMIC_MAX_F64()
2175 {
2176 } // ~Inst_FLAT__FLAT_ATOMIC_MAX_F64
2177
2178 void
2179 Inst_FLAT__FLAT_ATOMIC_MAX_F64::execute(GPUDynInstPtr gpuDynInst)
2180 {
2181 atomicExecute<ConstVecOperandF64, VecElemF64>(gpuDynInst);
2182 } // execute
2183
2184 void
2185 Inst_FLAT__FLAT_ATOMIC_MAX_F64::initiateAcc(GPUDynInstPtr gpuDynInst)
2186 {
2187 initAtomicAccess<VecElemF64>(gpuDynInst);
2188 } // initiateAcc
2189
2190 void
2191 Inst_FLAT__FLAT_ATOMIC_MAX_F64::completeAcc(GPUDynInstPtr gpuDynInst)
2192 {
2193 atomicComplete<VecOperandF64, VecElemF64>(gpuDynInst);
2194 } // completeAcc
2195} // namespace VegaISA
2196} // namespace gem5
data
const char data[]
Definition circlebuf.test.cc:48
gem5::GPUStaticInst::setFlag
void setFlag(Flags flag)
Definition gpu_static_inst.hh:250
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F32::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:2049
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F32::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:2043
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F32::~Inst_FLAT__FLAT_ATOMIC_ADD_F32
~Inst_FLAT__FLAT_ATOMIC_ADD_F32()
Definition flat.cc:2032
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F32::Inst_FLAT__FLAT_ATOMIC_ADD_F32
Inst_FLAT__FLAT_ATOMIC_ADD_F32(InFmt_FLAT *)
Definition flat.cc:2019
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F32::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:2037
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F64::~Inst_FLAT__FLAT_ATOMIC_ADD_F64
~Inst_FLAT__FLAT_ATOMIC_ADD_F64()
Definition flat.cc:2102
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F64::Inst_FLAT__FLAT_ATOMIC_ADD_F64
Inst_FLAT__FLAT_ATOMIC_ADD_F64(InFmt_FLAT *)
Definition flat.cc:2089
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F64::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:2119
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F64::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:2113
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_F64::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:2107
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1602
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::~Inst_FLAT__FLAT_ATOMIC_ADD_X2
~Inst_FLAT__FLAT_ATOMIC_ADD_X2()
Definition flat.cc:1580
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1590
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Inst_FLAT__FLAT_ATOMIC_ADD_X2(InFmt_FLAT *)
Definition flat.cc:1567
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1596
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD::Inst_FLAT__FLAT_ATOMIC_ADD
Inst_FLAT__FLAT_ATOMIC_ADD(InFmt_FLAT *)
Definition flat.cc:1042
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD::~Inst_FLAT__FLAT_ATOMIC_ADD
~Inst_FLAT__FLAT_ATOMIC_ADD()
Definition flat.cc:1054
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1064
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1076
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1070
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2::~Inst_FLAT__FLAT_ATOMIC_AND_X2
~Inst_FLAT__FLAT_ATOMIC_AND_X2()
Definition flat.cc:1826
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1842
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1848
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1836
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2::Inst_FLAT__FLAT_ATOMIC_AND_X2
Inst_FLAT__FLAT_ATOMIC_AND_X2(InFmt_FLAT *)
Definition flat.cc:1813
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1304
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1310
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1316
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND::~Inst_FLAT__FLAT_ATOMIC_AND
~Inst_FLAT__FLAT_ATOMIC_AND()
Definition flat.cc:1294
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND::Inst_FLAT__FLAT_ATOMIC_AND
Inst_FLAT__FLAT_ATOMIC_AND(InFmt_FLAT *)
Definition flat.cc:1282
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1549
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
~Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2()
Definition flat.cc:1537
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1555
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1561
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(InFmt_FLAT *)
Definition flat.cc:1524
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1036
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1024
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::~Inst_FLAT__FLAT_ATOMIC_CMPSWAP
~Inst_FLAT__FLAT_ATOMIC_CMPSWAP()
Definition flat.cc:1012
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1030
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::~Inst_FLAT__FLAT_ATOMIC_DEC_X2
~Inst_FLAT__FLAT_ATOMIC_DEC_X2()
Definition flat.cc:1990
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:2013
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:2001
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:2007
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Inst_FLAT__FLAT_ATOMIC_DEC_X2(InFmt_FLAT *)
Definition flat.cc:1977
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1471
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1465
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC::Inst_FLAT__FLAT_ATOMIC_DEC
Inst_FLAT__FLAT_ATOMIC_DEC(InFmt_FLAT *)
Definition flat.cc:1443
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC::~Inst_FLAT__FLAT_ATOMIC_DEC
~Inst_FLAT__FLAT_ATOMIC_DEC()
Definition flat.cc:1455
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1477
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::~Inst_FLAT__FLAT_ATOMIC_INC_X2
~Inst_FLAT__FLAT_ATOMIC_INC_X2()
Definition flat.cc:1949
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1971
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1965
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::Inst_FLAT__FLAT_ATOMIC_INC_X2
Inst_FLAT__FLAT_ATOMIC_INC_X2(InFmt_FLAT *)
Definition flat.cc:1936
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1959
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC::Inst_FLAT__FLAT_ATOMIC_INC
Inst_FLAT__FLAT_ATOMIC_INC(InFmt_FLAT *)
Definition flat.cc:1403
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC::~Inst_FLAT__FLAT_ATOMIC_INC
~Inst_FLAT__FLAT_ATOMIC_INC()
Definition flat.cc:1415
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1425
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1431
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1437
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MAX_F64::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:2185
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MAX_F64::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:2179
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MAX_F64::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:2191
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MAX_F64::Inst_FLAT__FLAT_ATOMIC_MAX_F64
Inst_FLAT__FLAT_ATOMIC_MAX_F64(InFmt_FLAT *)
Definition flat.cc:2161
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MAX_F64::~Inst_FLAT__FLAT_ATOMIC_MAX_F64
~Inst_FLAT__FLAT_ATOMIC_MAX_F64()
Definition flat.cc:2174
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MIN_F64::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:2143
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MIN_F64::~Inst_FLAT__FLAT_ATOMIC_MIN_F64
~Inst_FLAT__FLAT_ATOMIC_MIN_F64()
Definition flat.cc:2138
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MIN_F64::Inst_FLAT__FLAT_ATOMIC_MIN_F64
Inst_FLAT__FLAT_ATOMIC_MIN_F64(InFmt_FLAT *)
Definition flat.cc:2125
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MIN_F64::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:2149
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_MIN_F64::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:2155
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1877
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2::Inst_FLAT__FLAT_ATOMIC_OR_X2
Inst_FLAT__FLAT_ATOMIC_OR_X2(InFmt_FLAT *)
Definition flat.cc:1854
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2::~Inst_FLAT__FLAT_ATOMIC_OR_X2
~Inst_FLAT__FLAT_ATOMIC_OR_X2()
Definition flat.cc:1867
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1889
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1883
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::~Inst_FLAT__FLAT_ATOMIC_OR
~Inst_FLAT__FLAT_ATOMIC_OR()
Definition flat.cc:1334
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1356
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1344
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::Inst_FLAT__FLAT_ATOMIC_OR
Inst_FLAT__FLAT_ATOMIC_OR(InFmt_FLAT *)
Definition flat.cc:1322
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1350
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::~Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16
~Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16()
Definition flat.cc:2068
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:2079
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:2084
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:2073
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16::Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16
Inst_FLAT__FLAT_ATOMIC_PK_ADD_F16(InFmt_FLAT *)
Definition flat.cc:2055
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1760
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2::~Inst_FLAT__FLAT_ATOMIC_SMAX_X2
~Inst_FLAT__FLAT_ATOMIC_SMAX_X2()
Definition flat.cc:1744
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Inst_FLAT__FLAT_ATOMIC_SMAX_X2(InFmt_FLAT *)
Definition flat.cc:1731
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1766
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1754
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1224
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::Inst_FLAT__FLAT_ATOMIC_SMAX
Inst_FLAT__FLAT_ATOMIC_SMAX(InFmt_FLAT *)
Definition flat.cc:1202
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1236
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1230
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX::~Inst_FLAT__FLAT_ATOMIC_SMAX
~Inst_FLAT__FLAT_ATOMIC_SMAX()
Definition flat.cc:1214
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1672
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Inst_FLAT__FLAT_ATOMIC_SMIN_X2(InFmt_FLAT *)
Definition flat.cc:1649
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1684
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2::~Inst_FLAT__FLAT_ATOMIC_SMIN_X2
~Inst_FLAT__FLAT_ATOMIC_SMIN_X2()
Definition flat.cc:1662
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1678
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::Inst_FLAT__FLAT_ATOMIC_SMIN
Inst_FLAT__FLAT_ATOMIC_SMIN(InFmt_FLAT *)
Definition flat.cc:1122
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1156
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::~Inst_FLAT__FLAT_ATOMIC_SMIN
~Inst_FLAT__FLAT_ATOMIC_SMIN()
Definition flat.cc:1134
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1150
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1144
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Inst_FLAT__FLAT_ATOMIC_SUB_X2(InFmt_FLAT *)
Definition flat.cc:1608
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1637
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1643
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1631
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::~Inst_FLAT__FLAT_ATOMIC_SUB_X2
~Inst_FLAT__FLAT_ATOMIC_SUB_X2()
Definition flat.cc:1621
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1116
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB::~Inst_FLAT__FLAT_ATOMIC_SUB
~Inst_FLAT__FLAT_ATOMIC_SUB()
Definition flat.cc:1094
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB::Inst_FLAT__FLAT_ATOMIC_SUB
Inst_FLAT__FLAT_ATOMIC_SUB(InFmt_FLAT *)
Definition flat.cc:1082
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1110
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1104
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Inst_FLAT__FLAT_ATOMIC_SWAP_X2(InFmt_FLAT *)
Definition flat.cc:1483
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2::~Inst_FLAT__FLAT_ATOMIC_SWAP_X2
~Inst_FLAT__FLAT_ATOMIC_SWAP_X2()
Definition flat.cc:1496
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1506
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1518
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1512
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:980
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP::~Inst_FLAT__FLAT_ATOMIC_SWAP
~Inst_FLAT__FLAT_ATOMIC_SWAP()
Definition flat.cc:970
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:986
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP::Inst_FLAT__FLAT_ATOMIC_SWAP
Inst_FLAT__FLAT_ATOMIC_SWAP(InFmt_FLAT *)
Definition flat.cc:958
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:992
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1795
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2::~Inst_FLAT__FLAT_ATOMIC_UMAX_X2
~Inst_FLAT__FLAT_ATOMIC_UMAX_X2()
Definition flat.cc:1785
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1801
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1807
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Inst_FLAT__FLAT_ATOMIC_UMAX_X2(InFmt_FLAT *)
Definition flat.cc:1772
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX::~Inst_FLAT__FLAT_ATOMIC_UMAX
~Inst_FLAT__FLAT_ATOMIC_UMAX()
Definition flat.cc:1254
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1270
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1264
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX::Inst_FLAT__FLAT_ATOMIC_UMAX
Inst_FLAT__FLAT_ATOMIC_UMAX(InFmt_FLAT *)
Definition flat.cc:1242
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1276
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1713
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1719
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Inst_FLAT__FLAT_ATOMIC_UMIN_X2(InFmt_FLAT *)
Definition flat.cc:1690
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1725
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2::~Inst_FLAT__FLAT_ATOMIC_UMIN_X2
~Inst_FLAT__FLAT_ATOMIC_UMIN_X2()
Definition flat.cc:1703
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN::~Inst_FLAT__FLAT_ATOMIC_UMIN
~Inst_FLAT__FLAT_ATOMIC_UMIN()
Definition flat.cc:1174
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN::Inst_FLAT__FLAT_ATOMIC_UMIN
Inst_FLAT__FLAT_ATOMIC_UMIN(InFmt_FLAT *)
Definition flat.cc:1162
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1190
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1184
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1196
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Inst_FLAT__FLAT_ATOMIC_XOR_X2(InFmt_FLAT *)
Definition flat.cc:1895
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1930
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2::~Inst_FLAT__FLAT_ATOMIC_XOR_X2
~Inst_FLAT__FLAT_ATOMIC_XOR_X2()
Definition flat.cc:1908
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1924
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1918
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR::~Inst_FLAT__FLAT_ATOMIC_XOR
~Inst_FLAT__FLAT_ATOMIC_XOR()
Definition flat.cc:1375
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:1397
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:1385
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR::Inst_FLAT__FLAT_ATOMIC_XOR
Inst_FLAT__FLAT_ATOMIC_XOR(InFmt_FLAT *)
Definition flat.cc:1363
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:1391
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:339
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:311
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:333
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::~Inst_FLAT__FLAT_LOAD_DWORDX2
~Inst_FLAT__FLAT_LOAD_DWORDX2()
Definition flat.cc:304
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::Inst_FLAT__FLAT_LOAD_DWORDX2
Inst_FLAT__FLAT_LOAD_DWORDX2(InFmt_FLAT *)
Definition flat.cc:296
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::Inst_FLAT__FLAT_LOAD_DWORDX3
Inst_FLAT__FLAT_LOAD_DWORDX3(InFmt_FLAT *)
Definition flat.cc:365
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:402
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:380
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:408
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::~Inst_FLAT__FLAT_LOAD_DWORDX3
~Inst_FLAT__FLAT_LOAD_DWORDX3()
Definition flat.cc:373
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:455
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:477
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::~Inst_FLAT__FLAT_LOAD_DWORDX4
~Inst_FLAT__FLAT_LOAD_DWORDX4()
Definition flat.cc:448
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::Inst_FLAT__FLAT_LOAD_DWORDX4
Inst_FLAT__FLAT_LOAD_DWORDX4(InFmt_FLAT *)
Definition flat.cc:440
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:483
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:276
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:282
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:254
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::Inst_FLAT__FLAT_LOAD_DWORD
Inst_FLAT__FLAT_LOAD_DWORD(InFmt_FLAT *)
Definition flat.cc:240
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::~Inst_FLAT__FLAT_LOAD_DWORD
~Inst_FLAT__FLAT_LOAD_DWORD()
Definition flat.cc:247
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:111
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:133
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE::Inst_FLAT__FLAT_LOAD_SBYTE
Inst_FLAT__FLAT_LOAD_SBYTE(InFmt_FLAT *)
Definition flat.cc:97
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE::~Inst_FLAT__FLAT_LOAD_SBYTE
~Inst_FLAT__FLAT_LOAD_SBYTE()
Definition flat.cc:104
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:139
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:235
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:230
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:224
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT::Inst_FLAT__FLAT_LOAD_SSHORT
Inst_FLAT__FLAT_LOAD_SSHORT(InFmt_FLAT *)
Definition flat.cc:210
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT::~Inst_FLAT__FLAT_LOAD_SSHORT
~Inst_FLAT__FLAT_LOAD_SSHORT()
Definition flat.cc:217
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::Inst_FLAT__FLAT_LOAD_UBYTE
Inst_FLAT__FLAT_LOAD_UBYTE(InFmt_FLAT *)
Definition flat.cc:41
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:77
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:83
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:55
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::~Inst_FLAT__FLAT_LOAD_UBYTE
~Inst_FLAT__FLAT_LOAD_UBYTE()
Definition flat.cc:48
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:189
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::~Inst_FLAT__FLAT_LOAD_USHORT
~Inst_FLAT__FLAT_LOAD_USHORT()
Definition flat.cc:160
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:167
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:195
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::Inst_FLAT__FLAT_LOAD_USHORT
Inst_FLAT__FLAT_LOAD_USHORT(InFmt_FLAT *)
Definition flat.cc:153
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:575
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::Inst_FLAT__FLAT_STORE_BYTE
Inst_FLAT__FLAT_STORE_BYTE(InFmt_FLAT *)
Definition flat.cc:521
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:535
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::~Inst_FLAT__FLAT_STORE_BYTE
~Inst_FLAT__FLAT_STORE_BYTE()
Definition flat.cc:528
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:569
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:813
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:807
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:773
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::~Inst_FLAT__FLAT_STORE_DWORDX2
~Inst_FLAT__FLAT_STORE_DWORDX2()
Definition flat.cc:766
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::Inst_FLAT__FLAT_STORE_DWORDX2
Inst_FLAT__FLAT_STORE_DWORDX2(InFmt_FLAT *)
Definition flat.cc:758
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:881
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:875
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::Inst_FLAT__FLAT_STORE_DWORDX3
Inst_FLAT__FLAT_STORE_DWORDX3(InFmt_FLAT *)
Definition flat.cc:818
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:833
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::~Inst_FLAT__FLAT_STORE_DWORDX3
~Inst_FLAT__FLAT_STORE_DWORDX3()
Definition flat.cc:826
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:953
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:947
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::~Inst_FLAT__FLAT_STORE_DWORDX4
~Inst_FLAT__FLAT_STORE_DWORDX4()
Definition flat.cc:894
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::Inst_FLAT__FLAT_STORE_DWORDX4
Inst_FLAT__FLAT_STORE_DWORDX4(InFmt_FLAT *)
Definition flat.cc:886
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:901
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:747
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::Inst_FLAT__FLAT_STORE_DWORD
Inst_FLAT__FLAT_STORE_DWORD(InFmt_FLAT *)
Definition flat.cc:699
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:713
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:753
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::~Inst_FLAT__FLAT_STORE_DWORD
~Inst_FLAT__FLAT_STORE_DWORD()
Definition flat.cc:706
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT_D16_HI::~Inst_FLAT__FLAT_STORE_SHORT_D16_HI
~Inst_FLAT__FLAT_STORE_SHORT_D16_HI()
Definition flat.cc:647
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT_D16_HI::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:694
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT_D16_HI::Inst_FLAT__FLAT_STORE_SHORT_D16_HI
Inst_FLAT__FLAT_STORE_SHORT_D16_HI(InFmt_FLAT *)
Definition flat.cc:640
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT_D16_HI::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:654
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT_D16_HI::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:688
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::execute
void execute(GPUDynInstPtr) override
Definition flat.cc:594
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::~Inst_FLAT__FLAT_STORE_SHORT
~Inst_FLAT__FLAT_STORE_SHORT()
Definition flat.cc:587
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::Inst_FLAT__FLAT_STORE_SHORT
Inst_FLAT__FLAT_STORE_SHORT(InFmt_FLAT *)
Definition flat.cc:580
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::completeAcc
void completeAcc(GPUDynInstPtr) override
Definition flat.cc:634
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::initiateAcc
void initiateAcc(GPUDynInstPtr) override
Definition flat.cc:628
gem5::VegaISA::Inst_FLAT
Definition op_encodings.hh:1297
gem5::VegaISA::Inst_FLAT::instData
InFmt_FLAT instData
Definition op_encodings.hh:1665
gem5::VegaISA::Inst_FLAT::calcAddr
void calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr, ScalarRegU32 saddr, ScalarRegI32 offset)
Definition op_encodings.hh:1435
gem5::VegaISA::Inst_FLAT::extData
InFmt_FLAT_1 extData
Definition op_encodings.hh:1667
gem5::VegaISA::Inst_FLAT::issueRequestHelper
void issueRequestHelper(GPUDynInstPtr gpuDynInst)
Definition op_encodings.hh:1542
gem5::VegaISA::VecOperand::read
void read() override
read from the vrf.
Definition operand.hh:147
gem5::VegaISA::VecOperand::write
void write() override
write to the vrf.
Definition operand.hh:199
gem5::Wavefront::decExpInstsIssued
void decExpInstsIssued()
Definition wavefront.cc:1427
gem5::Wavefront::decVMemInstsIssued
void decVMemInstsIssued()
Definition wavefront.cc:1421
gem5::Wavefront::decLGKMInstsIssued
void decLGKMInstsIssued()
Definition wavefront.cc:1433
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition vec.hh:61
gem5::VegaISA::VecElemU16
uint16_t VecElemU16
Definition gpu_registers.hh:163
gem5::VegaISA::VecElemU32
uint32_t VecElemU32
Definition gpu_registers.hh:165
gem5::VegaISA::VecElemU64
uint64_t VecElemU64
Definition gpu_registers.hh:168
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition misc.hh:49
gem5::VegaISA::InFmt_FLAT_1::VDST
unsigned int VDST
Definition gpu_decoder.hh:1731
gem5::VegaISA::InFmt_FLAT_1::DATA
unsigned int DATA
Definition gpu_decoder.hh:1728
gem5::VegaISA::InFmt_FLAT_1::ADDR
unsigned int ADDR
Definition gpu_decoder.hh:1727
gem5::VegaISA::InFmt_FLAT_1::SADDR
unsigned int SADDR
Definition gpu_decoder.hh:1729
gem5::VegaISA::InFmt_FLAT
Definition gpu_decoder.hh:1715
gem5::VegaISA::InFmt_FLAT::OFFSET
unsigned int OFFSET
Definition gpu_decoder.hh:1716
gem5::VegaISA::InFmt_FLAT::GLC
unsigned int GLC
Definition gpu_decoder.hh:1719
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