fp8_e4m3.hh

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#ifndef __ARCH_AMDGPU_COMMON_DTYPE_FP8_E4M3_HH__
#define __ARCH_AMDGPU_COMMON_DTYPE_FP8_E4M3_HH__
 
#include <cassert>
 
namespace gem5
{
 
namespace AMDGPU
{
 
typedef union
{
    enum bitSizes
    {
        ebits = 4,
        mbits = 3,
        sbits = 1,
        zbits = 24,
        bias = 7,
 
        inf = (0x7f << zbits),
        nan = (0xff << zbits),
        max = (0x7f << zbits)
    };
    enum bitSizes {…};
 
    uint32_t storage;
    struct
    {
        unsigned zero : zbits;
        unsigned mant : mbits;
        unsigned exp  : ebits;
        unsigned sign : sbits;
    };
} fp8_e4m3_info;
typedef union {…};
static_assert(sizeof(fp8_e4m3_info) == 4);
 
} // namespace AMDGPU
 
} // namespace gem5
 
 
// std library cmath definitions
namespace std
{
 
// Inf not defined
constexpr bool isinf(gem5::AMDGPU::fp8_e4m3_info a) { return false; }
 
constexpr bool isnan(gem5::AMDGPU::fp8_e4m3_info a)
{
    return a.exp == 0xF && a.mant == 0x7;
}
constexpr bool isnan(gem5::AMDGPU::fp8_e4m3_info a) {…}
 
constexpr bool isnormal(gem5::AMDGPU::fp8_e4m3_info a)
{
    return !(a.exp == 0 && a.mant != 0);
}
constexpr bool isnormal(gem5::AMDGPU::fp8_e4m3_info a) {…}
 
 
template<>
class numeric_limits<gem5::AMDGPU::fp8_e4m3_info>
{
  public:
    static constexpr bool has_quiet_NaN = true;
    static gem5::AMDGPU::fp8_e4m3_info quiet_NaN()
    {
        assert(has_quiet_NaN);
        gem5::AMDGPU::fp8_e4m3_info tmp;
        tmp.storage = gem5::AMDGPU::fp8_e4m3_info::nan;
        return tmp;
    }
    static gem5::AMDGPU::fp8_e4m3_info quiet_NaN() {…}
 
    static constexpr bool has_infinity = false;
    static gem5::AMDGPU::fp8_e4m3_info infinity()
    {
        assert(has_infinity);
        gem5::AMDGPU::fp8_e4m3_info tmp;
        tmp.storage = gem5::AMDGPU::fp8_e4m3_info::inf;
        return tmp;
    }
    static gem5::AMDGPU::fp8_e4m3_info infinity() {…}
 
    static gem5::AMDGPU::fp8_e4m3_info max()
    {
        gem5::AMDGPU::fp8_e4m3_info tmp;
        tmp.storage = gem5::AMDGPU::fp8_e4m3_info::max;
        return tmp;
    }
    static gem5::AMDGPU::fp8_e4m3_info max() {…}
};
class numeric_limits<gem5::AMDGPU::fp8_e4m3_info> {…};
 
} // namespace std
 
#endif // __ARCH_AMDGPU_COMMON_DTYPE_FP8_E4M3_HH__