pif.cc

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#include "mem/cache/prefetch/pif.hh"
 
#include <utility>
 
#include "debug/HWPrefetch.hh"
#include "params/PIFPrefetcher.hh"
 
namespace gem5
{
 
namespace prefetch
{
 
PIF::PIF(const PIFPrefetcherParams &p)
    : Queued(p),
      precSize(p.prec_spatial_region_bits),
      succSize(p.succ_spatial_region_bits),
      maxCompactorEntries(p.compactor_entries),
      historyBuffer(p.history_buffer_size),
      index((name() + ".PIFIndex").c_str(), p.index_entries, p.index_assoc,
            p.index_replacement_policy,
            p.index_indexing_policy,
            IndexEntry(genTagExtractor(p.index_indexing_policy))),
      streamAddressBuffer(p.stream_address_buffer_entries),
      listenersPC()
{
}
PIF::PIF(const PIFPrefetcherParams &p) {…}
 
PIF::CompactorEntry::CompactorEntry(Addr addr,
    unsigned int prec_size, unsigned int succ_size)
{
    trigger = addr;
    prec.resize(prec_size, false);
    succ.resize(succ_size, false);
}
PIF::CompactorEntry::CompactorEntry(Addr addr, {…}
 
Addr
PIF::CompactorEntry::distanceFromTrigger(Addr target,
        unsigned int log_blk_size) const
{
    const Addr target_blk = target >> log_blk_size;
    const Addr trigger_blk = trigger >> log_blk_size;
 
    return target_blk > trigger_blk ?
              target_blk - trigger_blk : trigger_blk - target_blk;
}
PIF::CompactorEntry::distanceFromTrigger(Addr target, {…}
 
bool
PIF::CompactorEntry::inSameSpatialRegion(Addr pc,
        unsigned int log_blk_size, bool update)
{
    Addr blk_distance = distanceFromTrigger(pc, log_blk_size);
 
    bool hit = (pc > trigger) ?
        (succ.size() > blk_distance) : (prec.size() > blk_distance);
    if (hit && update) {
        if (pc > trigger) {
            succ[blk_distance] = true;
        } else if (pc < trigger) {
            prec[blk_distance] = true;
        }
    }
    return hit;
}
PIF::CompactorEntry::inSameSpatialRegion(Addr pc, {…}
 
bool
PIF::CompactorEntry::hasAddress(Addr target,
                                          unsigned int log_blk_size) const
{
    Addr blk_distance = distanceFromTrigger(target, log_blk_size);
    bool hit = false;
    if (target > trigger) {
        hit = blk_distance < succ.size() && succ[blk_distance];
    } else if (target < trigger) {
        hit = blk_distance < prec.size() && prec[blk_distance];
    } else {
        hit = true;
    }
    return hit;
}
PIF::CompactorEntry::hasAddress(Addr target, {…}
 
void
PIF::CompactorEntry::getPredictedAddresses(unsigned int log_blk_size,
    std::vector<AddrPriority> &addresses) const
{
    // Calculate the addresses of the instruction blocks that are encoded
    // by the bit vector and issue prefetch requests for these addresses.
    // Predictions are made by traversing the bit vector from left to right
    // as this typically predicts the accesses in the order they will be
    // issued in the core.
    const Addr trigger_blk = trigger >> log_blk_size;
    for (int i = prec.size()-1; i >= 0; i--) {
        // Address from the preceding blocks to issue a prefetch
        if (prec[i]) {
            const Addr prec_addr = (trigger_blk - (i+1)) << log_blk_size;
            addresses.push_back(AddrPriority(prec_addr, 0));
        }
    }
    for (int i = 0; i < succ.size(); i++) {
        // Address from the succeding blocks to issue a prefetch
        if (succ[i]) {
            const Addr succ_addr = (trigger_blk + (i+1)) << log_blk_size;
            addresses.push_back(AddrPriority(succ_addr, 0));
        }
    }
}
PIF::CompactorEntry::getPredictedAddresses(unsigned int log_blk_size, {…}
 
void
PIF::notifyRetiredInst(const Addr pc)
{
    // First access to the prefetcher
    if (temporalCompactor.size() == 0) {
        spatialCompactor = CompactorEntry(pc, precSize, succSize);
        temporalCompactor.push_back(spatialCompactor);
    } else {
        // If the PC of the instruction retired is in the same spatial region
        // than the last trigger address, update the bit vectors based on the
        // distance between them
        if (spatialCompactor.inSameSpatialRegion(pc, lBlkSize, true)) {
        // If the PC of the instruction retired is outside the latest spatial
        // region, check if it matches in any of the regions in the temporal
        // compactor and update it to the MRU position
        } else {
            bool is_in_temporal_compactor = false;
 
            // Check if the PC is in the temporal compactor
            for (auto it = temporalCompactor.begin();
                    it != temporalCompactor.end(); it++)
            {
                if (it->inSameSpatialRegion(pc, lBlkSize, false)) {
                    spatialCompactor = (*it);
                    temporalCompactor.erase(it);
                    is_in_temporal_compactor = true;
                    break;
                }
            }
 
            if (temporalCompactor.size() == maxCompactorEntries) {
                temporalCompactor.pop_front(); // Discard the LRU entry
            }
 
            temporalCompactor.push_back(spatialCompactor);
 
            // If the compactor entry is neither the spatial or can't be
            // found in the temporal compactor, reset the spatial compactor
            // updating the trigger address and resetting the vector bits
            if (!is_in_temporal_compactor) {
                // Insert the spatial entry into the history buffer and update
                // the 'iterator' table to point to the new entry
                historyBuffer.push_back(spatialCompactor);
 
                const IndexEntry::KeyType key{spatialCompactor.trigger, false};
                auto idx_entry = index.findEntry(key);
                if (idx_entry != nullptr) {
                    index.accessEntry(idx_entry);
                } else {
                    idx_entry = index.findVictim(key);
                    assert(idx_entry != nullptr);
                    index.insertEntry(key, idx_entry);
                }
                idx_entry->historyIt =
                    historyBuffer.getIterator(historyBuffer.tail());
 
                // Reset the spatial compactor fields with the new address
                spatialCompactor = CompactorEntry(pc, precSize, succSize);
            }
        }
    }
}
PIF::notifyRetiredInst(const Addr pc) {…}
 
void
PIF::calculatePrefetch(const PrefetchInfo &pfi,
    std::vector<AddrPriority> &addresses,
    const CacheAccessor &cache)
{
    if (!pfi.hasPC()) {
        return;
    }
 
    const Addr pc = pfi.getPC();
    bool is_secure = pfi.isSecure();
 
    // First check if the access has been prefetched, this is done by
    // comparing the access against the active Stream Address Buffers
    for (auto &sabEntry : streamAddressBuffer) {
        if (sabEntry->hasAddress(pc, lBlkSize)) {
            sabEntry++;
            sabEntry->getPredictedAddresses(lBlkSize, addresses);
            // We are done
            return;
        }
    }
 
    // Check if a valid entry in the 'index' table is found and allocate a new
    // active prediction stream
    IndexEntry *idx_entry = index.findEntry({pc, is_secure});
 
    if (idx_entry != nullptr) {
        index.accessEntry(idx_entry);
        // Trigger address from the 'index' table and index to the history
        // buffer
        auto entry = idx_entry->historyIt;
 
        // Track the block in the Stream Address Buffer
        streamAddressBuffer.push_back(entry);
 
        entry->getPredictedAddresses(lBlkSize, addresses);
    }
}
PIF::calculatePrefetch(const PrefetchInfo &pfi, {…}
 
void
PIF::PrefetchListenerPC::notify(const Addr& pc)
{
    parent.notifyRetiredInst(pc);
}
PIF::PrefetchListenerPC::notify(const Addr& pc) {…}
 
void
PIF::addEventProbeRetiredInsts(SimObject *obj, const char *name)
{
    ProbeManager *pm(obj->getProbeManager());
    listenersPC.push_back(new PrefetchListenerPC(*this, pm, name));
}
PIF::addEventProbeRetiredInsts(SimObject *obj, const char *name) {…}
 
} // namespace prefetch
} // namespace gem5