decoder.cc

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/*
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#include "arch/riscv/decoder.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/types.hh"
#include "base/bitfield.hh"
#include "debug/Decode.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
{
    ISA *isa = dynamic_cast<ISA*>(p.isa);
    vlen = isa->getVecLenInBits();
    elen = isa->getVecElemLenInBits();
    _enableZcd = isa->enableZcd();
    reset();
}
Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst) {…}
 
void Decoder::reset()
{
    aligned = true;
    mid = false;
    machInst = 0;
    emi = 0;
}
void Decoder::reset() {…}
 
void
Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
{
    // The MSB of the upper and lower halves of a machine instruction.
    constexpr size_t max_bit = sizeof(machInst) * 8 - 1;
    constexpr size_t mid_bit = sizeof(machInst) * 4 - 1;
 
    auto inst = letoh(machInst);
    DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
            fetchPC);
 
    bool aligned = pc.instAddr() % sizeof(machInst) == 0;
    if (aligned) {
        emi.instBits = inst;
        if (compressed(inst))
            emi.instBits = bits(inst, mid_bit, 0);
        outOfBytes = !compressed(emi);
        instDone = true;
    } else {
        if (mid) {
            assert(bits(emi.instBits, max_bit, mid_bit + 1) == 0);
            replaceBits(emi.instBits, max_bit, mid_bit + 1, inst);
            mid = false;
            outOfBytes = false;
            instDone = true;
        } else {
            emi.instBits = bits(inst, max_bit, mid_bit + 1);
            mid = !compressed(emi);
            outOfBytes = true;
            instDone = compressed(emi);
        }
    }
}
Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC) {…}
 
StaticInstPtr
Decoder::decode(ExtMachInst mach_inst, Addr addr)
{
    DPRINTF(Decode, "Decoding instruction 0x%08x at address %#x\n",
            mach_inst.instBits, addr);
 
    StaticInstPtr &si = instMap[mach_inst];
    if (!si)
        si = decodeInst(mach_inst);
 
    si->size(compressed(mach_inst) ? 2 : 4);
 
    DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
            si->getName(), mach_inst);
    return si;
}
Decoder::decode(ExtMachInst mach_inst, Addr addr) {…}
 
StaticInstPtr
Decoder::decode(PCStateBase &_next_pc)
{
    if (!instDone)
        return nullptr;
    instDone = false;
 
    auto &next_pc = _next_pc.as<PCState>();
 
    if (compressed(emi)) {
        next_pc.npc(next_pc.instAddr() + sizeof(machInst) / 2);
        next_pc.compressed(true);
    } else {
        next_pc.npc(next_pc.instAddr() + sizeof(machInst));
        next_pc.compressed(false);
    }
 
    emi.vl      = next_pc.vl();
    emi.vtype8  = next_pc.vtype() & 0xff;
    emi.vill    = next_pc.vtype().vill;
    emi.rv_type = static_cast<int>(next_pc.rvType());
    emi.enable_zcd = _enableZcd;
 
    return decode(emi, next_pc.instAddr());
}
Decoder::decode(PCStateBase &_next_pc) {…}
 
} // namespace RiscvISA
} // namespace gem5