simple_mem.hh

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/*
 * Copyright (c) 2012-2013 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
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 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * All rights reserved.
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 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
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 * documentation and/or other materials provided with the distribution;
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#ifndef __MEM_SIMPLE_MEMORY_HH__
#define __MEM_SIMPLE_MEMORY_HH__
 
#include <list>
 
#include "base/random.hh"
#include "mem/abstract_mem.hh"
#include "mem/port.hh"
#include "params/SimpleMemory.hh"
 
namespace gem5
{
 
namespace memory
{
 
class SimpleMemory : public AbstractMemory
{
 
  private:
 
    class DeferredPacket
    {
 
      public:
 
        const Tick tick;
        const PacketPtr pkt;
 
        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
        { }
        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) {…}
    };
    class DeferredPacket {…};
 
    class MemoryPort : public ResponsePort
    {
      private:
        SimpleMemory& mem;
 
      public:
        MemoryPort(const std::string& _name, SimpleMemory& _memory);
 
      protected:
        Tick recvAtomic(PacketPtr pkt) override;
        Tick recvAtomicBackdoor(
                PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
        void recvFunctional(PacketPtr pkt) override;
        void recvMemBackdoorReq(const MemBackdoorReq &req,
                MemBackdoorPtr &backdoor) override;
        bool recvTimingReq(PacketPtr pkt) override;
        void recvRespRetry() override;
        AddrRangeList getAddrRanges() const override;
    };
    class MemoryPort : public ResponsePort {…};
 
    MemoryPort port;
 
    const Tick latency;
 
    const Tick latency_var;
 
    std::list<DeferredPacket> packetQueue;
 
    const double bandwidth;
 
    bool isBusy;
 
    bool retryReq;
 
    bool retryResp;
 
    mutable Random::RandomPtr rng = Random::genRandom();
 
    void release();
 
    EventFunctionWrapper releaseEvent;
 
    void dequeue();
 
    EventFunctionWrapper dequeueEvent;
 
    Tick getLatency() const;
 
    std::unique_ptr<Packet> pendingDelete;
 
  public:
 
    SimpleMemory(const SimpleMemoryParams &p);
 
    DrainState drain() override;
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;
    void init() override;
 
  protected:
    Tick recvAtomic(PacketPtr pkt);
    Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor);
    void recvFunctional(PacketPtr pkt);
    void recvMemBackdoorReq(const MemBackdoorReq &req,
            MemBackdoorPtr &backdoor);
    bool recvTimingReq(PacketPtr pkt);
    void recvRespRetry();
};
class SimpleMemory : public AbstractMemory {…};
 
} // namespace memory
} // namespace gem5
 
#endif //__MEM_SIMPLE_MEMORY_HH__