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vopc.cc
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1/*
2 * Copyright (c) 2024 Advanced Micro Devices, Inc.
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4 *
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9 * this list of conditions and the following disclaimer.
10 *
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30 */
31
32#include "arch/amdgpu/vega/insts/instructions.hh"
33
34namespace gem5
35{
36
37namespace VegaISA
38{
39 // --- Inst_VOPC__V_CMP_CLASS_F32 class methods ---
40
41 Inst_VOPC__V_CMP_CLASS_F32::Inst_VOPC__V_CMP_CLASS_F32(InFmt_VOPC *iFmt)
42 : Inst_VOPC(iFmt, "v_cmp_class_f32")
43 {
44 setFlag(ALU);
45 setFlag(F32);
46 } // Inst_VOPC__V_CMP_CLASS_F32
47
48 Inst_VOPC__V_CMP_CLASS_F32::~Inst_VOPC__V_CMP_CLASS_F32()
49 {
50 } // ~Inst_VOPC__V_CMP_CLASS_F32
51
52 // --- description from .arch file ---
53 // VCC = IEEE numeric class function specified in S1.u, performed on S0.f
54 // The function reports true if the floating point value is *any* of the
55 // --- numeric types selected in S1.u according to the following list:
56 // S1.u[0] -- value is a signaling NaN.
57 // S1.u[1] -- value is a quiet NaN.
58 // S1.u[2] -- value is negative infinity.
59 // S1.u[3] -- value is a negative normal value.
60 // S1.u[4] -- value is a negative denormal value.
61 // S1.u[5] -- value is negative zero.
62 // S1.u[6] -- value is positive zero.
63 // S1.u[7] -- value is a positive denormal value.
64 // S1.u[8] -- value is a positive normal value.
65 // S1.u[9] -- value is positive infinity.
66 void
67 Inst_VOPC__V_CMP_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
68 {
69 Wavefront *wf = gpuDynInst->wavefront();
70 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
71 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
72 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
73
74 src0.readSrc();
75 src1.read();
76
77 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
78 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
79
80 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
81 if (wf->execMask(lane)) {
82 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
83 // is NaN
84 if (std::isnan(src0[lane])) {
85 vcc.setBit(lane, 1);
86 continue;
87 }
88 }
89 if (bits(src1[lane], 2)) {
90 // is -infinity
91 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
92 vcc.setBit(lane, 1);
93 continue;
94 }
95 }
96 if (bits(src1[lane], 3)) {
97 // is -normal
98 if (std::isnormal(src0[lane])
99 && std::signbit(src0[lane])) {
100 vcc.setBit(lane, 1);
101 continue;
102 }
103 }
104 if (bits(src1[lane], 4)) {
105 // is -denormal
106 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
107 && std::signbit(src0[lane])) {
108 vcc.setBit(lane, 1);
109 continue;
110 }
111 }
112 if (bits(src1[lane], 5)) {
113 // is -zero
114 if (std::fpclassify(src0[lane]) == FP_ZERO
115 && std::signbit(src0[lane])) {
116 vcc.setBit(lane, 1);
117 continue;
118 }
119 }
120 if (bits(src1[lane], 6)) {
121 // is +zero
122 if (std::fpclassify(src0[lane]) == FP_ZERO
123 && !std::signbit(src0[lane])) {
124 vcc.setBit(lane, 1);
125 continue;
126 }
127 }
128 if (bits(src1[lane], 7)) {
129 // is +denormal
130 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
131 && !std::signbit(src0[lane])) {
132 vcc.setBit(lane, 1);
133 continue;
134 }
135 }
136 if (bits(src1[lane], 8)) {
137 // is +normal
138 if (std::isnormal(src0[lane])
139 && !std::signbit(src0[lane])) {
140 vcc.setBit(lane, 1);
141 continue;
142 }
143 }
144 if (bits(src1[lane], 9)) {
145 // is +infinity
146 if (std::isinf(src0[lane]) && !std::signbit(src0[lane])) {
147 vcc.setBit(lane, 1);
148 continue;
149 }
150 }
151 }
152 }
153
154 vcc.write();
155 } // execute
156 // --- Inst_VOPC__V_CMPX_CLASS_F32 class methods ---
157
158 Inst_VOPC__V_CMPX_CLASS_F32::Inst_VOPC__V_CMPX_CLASS_F32(InFmt_VOPC *iFmt)
159 : Inst_VOPC(iFmt, "v_cmpx_class_f32")
160 {
161 setFlag(ALU);
162 setFlag(F32);
163 setFlag(WritesEXEC);
164 } // Inst_VOPC__V_CMPX_CLASS_F32
165
166 Inst_VOPC__V_CMPX_CLASS_F32::~Inst_VOPC__V_CMPX_CLASS_F32()
167 {
168 } // ~Inst_VOPC__V_CMPX_CLASS_F32
169
170 // --- description from .arch file ---
171 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
172 // S0.f The function reports true if the floating point value is *any* of
173 // the numeric types selected in S1.u according to the following list:
174 // S1.u[0] -- value is a signaling NaN.
175 // S1.u[1] -- value is a quiet NaN.
176 // S1.u[2] -- value is negative infinity.
177 // S1.u[3] -- value is a negative normal value.
178 // S1.u[4] -- value is a negative denormal value.
179 // S1.u[5] -- value is negative zero.
180 // S1.u[6] -- value is positive zero.
181 // S1.u[7] -- value is a positive denormal value.
182 // S1.u[8] -- value is a positive normal value.
183 // S1.u[9] -- value is positive infinity.
184 void
185 Inst_VOPC__V_CMPX_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
186 {
187 Wavefront *wf = gpuDynInst->wavefront();
188 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
189 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
190 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
191
192 src0.readSrc();
193 src1.read();
194
195 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
196 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
197
198 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
199 if (wf->execMask(lane)) {
200 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
201 // is NaN
202 if (std::isnan(src0[lane])) {
203 vcc.setBit(lane, 1);
204 continue;
205 }
206 }
207 if (bits(src1[lane], 2)) {
208 // is -infinity
209 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
210 vcc.setBit(lane, 1);
211 continue;
212 }
213 }
214 if (bits(src1[lane], 3)) {
215 // is -normal
216 if (std::isnormal(src0[lane])
217 && std::signbit(src0[lane])) {
218 vcc.setBit(lane, 1);
219 continue;
220 }
221 }
222 if (bits(src1[lane], 4)) {
223 // is -denormal
224 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
225 && std::signbit(src0[lane])) {
226 vcc.setBit(lane, 1);
227 continue;
228 }
229 }
230 if (bits(src1[lane], 5)) {
231 // is -zero
232 if (std::fpclassify(src0[lane]) == FP_ZERO
233 && std::signbit(src0[lane])) {
234 vcc.setBit(lane, 1);
235 continue;
236 }
237 }
238 if (bits(src1[lane], 6)) {
239 // is +zero
240 if (std::fpclassify(src0[lane]) == FP_ZERO
241 && !std::signbit(src0[lane])) {
242 vcc.setBit(lane, 1);
243 continue;
244 }
245 }
246 if (bits(src1[lane], 7)) {
247 // is +denormal
248 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
249 && !std::signbit(src0[lane])) {
250 vcc.setBit(lane, 1);
251 continue;
252 }
253 }
254 if (bits(src1[lane], 8)) {
255 // is +normal
256 if (std::isnormal(src0[lane])
257 && !std::signbit(src0[lane])) {
258 vcc.setBit(lane, 1);
259 continue;
260 }
261 }
262 if (bits(src1[lane], 9)) {
263 // is +infinity
264 if (std::isinf(src0[lane]) && !std::signbit(src0[lane])) {
265 vcc.setBit(lane, 1);
266 continue;
267 }
268 }
269 }
270 }
271
272 vcc.write();
273 wf->execMask() = vcc.rawData();
274 } // execute
275 // --- Inst_VOPC__V_CMP_CLASS_F64 class methods ---
276
277 Inst_VOPC__V_CMP_CLASS_F64::Inst_VOPC__V_CMP_CLASS_F64(InFmt_VOPC *iFmt)
278 : Inst_VOPC(iFmt, "v_cmp_class_f64")
279 {
280 setFlag(ALU);
281 setFlag(F64);
282 } // Inst_VOPC__V_CMP_CLASS_F64
283
284 Inst_VOPC__V_CMP_CLASS_F64::~Inst_VOPC__V_CMP_CLASS_F64()
285 {
286 } // ~Inst_VOPC__V_CMP_CLASS_F64
287
288 // --- description from .arch file ---
289 // VCC = IEEE numeric class function specified in S1.u, performed on S0.d
290 // The function reports true if the floating point value is *any* of the
291 // --- numeric types selected in S1.u according to the following list:
292 // S1.u[0] -- value is a signaling NaN.
293 // S1.u[1] -- value is a quiet NaN.
294 // S1.u[2] -- value is negative infinity.
295 // S1.u[3] -- value is a negative normal value.
296 // S1.u[4] -- value is a negative denormal value.
297 // S1.u[5] -- value is negative zero.
298 // S1.u[6] -- value is positive zero.
299 // S1.u[7] -- value is a positive denormal value.
300 // S1.u[8] -- value is a positive normal value.
301 // S1.u[9] -- value is positive infinity.
302 void
303 Inst_VOPC__V_CMP_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
304 {
305 Wavefront *wf = gpuDynInst->wavefront();
306 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
307 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
308 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
309
310 src0.readSrc();
311 src1.read();
312
313 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
314 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
315
316 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
317 if (wf->execMask(lane)) {
318 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
319 // is NaN
320 if (std::isnan(src0[lane])) {
321 vcc.setBit(lane, 1);
322 continue;
323 }
324 }
325 if (bits(src1[lane], 2)) {
326 // is -infinity
327 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
328 vcc.setBit(lane, 1);
329 continue;
330 }
331 }
332 if (bits(src1[lane], 3)) {
333 // is -normal
334 if (std::isnormal(src0[lane])
335 && std::signbit(src0[lane])) {
336 vcc.setBit(lane, 1);
337 continue;
338 }
339 }
340 if (bits(src1[lane], 4)) {
341 // is -denormal
342 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
343 && std::signbit(src0[lane])) {
344 vcc.setBit(lane, 1);
345 continue;
346 }
347 }
348 if (bits(src1[lane], 5)) {
349 // is -zero
350 if (std::fpclassify(src0[lane]) == FP_ZERO
351 && std::signbit(src0[lane])) {
352 vcc.setBit(lane, 1);
353 continue;
354 }
355 }
356 if (bits(src1[lane], 6)) {
357 // is +zero
358 if (std::fpclassify(src0[lane]) == FP_ZERO
359 && !std::signbit(src0[lane])) {
360 vcc.setBit(lane, 1);
361 continue;
362 }
363 }
364 if (bits(src1[lane], 7)) {
365 // is +denormal
366 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
367 && !std::signbit(src0[lane])) {
368 vcc.setBit(lane, 1);
369 continue;
370 }
371 }
372 if (bits(src1[lane], 8)) {
373 // is +normal
374 if (std::isnormal(src0[lane])
375 && !std::signbit(src0[lane])) {
376 vcc.setBit(lane, 1);
377 continue;
378 }
379 }
380 if (bits(src1[lane], 9)) {
381 // is +infinity
382 if (std::isinf(src0[lane])
383 && !std::signbit(src0[lane])) {
384 vcc.setBit(lane, 1);
385 continue;
386 }
387 }
388 }
389 }
390
391 vcc.write();
392 } // execute
393 // --- Inst_VOPC__V_CMPX_CLASS_F64 class methods ---
394
395 Inst_VOPC__V_CMPX_CLASS_F64::Inst_VOPC__V_CMPX_CLASS_F64(InFmt_VOPC *iFmt)
396 : Inst_VOPC(iFmt, "v_cmpx_class_f64")
397 {
398 setFlag(ALU);
399 setFlag(F64);
400 setFlag(WritesEXEC);
401 } // Inst_VOPC__V_CMPX_CLASS_F64
402
403 Inst_VOPC__V_CMPX_CLASS_F64::~Inst_VOPC__V_CMPX_CLASS_F64()
404 {
405 } // ~Inst_VOPC__V_CMPX_CLASS_F64
406
407 // --- description from .arch file ---
408 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
409 // S0.d The function reports true if the floating point value is *any* of
410 // the numeric types selected in S1.u according to the following list:
411 // S1.u[0] -- value is a signaling NaN.
412 // S1.u[1] -- value is a quiet NaN.
413 // S1.u[2] -- value is negative infinity.
414 // S1.u[3] -- value is a negative normal value.
415 // S1.u[4] -- value is a negative denormal value.
416 // S1.u[5] -- value is negative zero.
417 // S1.u[6] -- value is positive zero.
418 // S1.u[7] -- value is a positive denormal value.
419 // S1.u[8] -- value is a positive normal value.
420 // S1.u[9] -- value is positive infinity.
421 void
422 Inst_VOPC__V_CMPX_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
423 {
424 Wavefront *wf = gpuDynInst->wavefront();
425 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
426 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
427 ConstScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
428
429 src0.readSrc();
430 src1.read();
431
432 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
433 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
434
435 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
436 if (wf->execMask(lane)) {
437 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
438 // is NaN
439 if (std::isnan(src0[lane])) {
440 vcc.setBit(lane, 1);
441 continue;
442 }
443 }
444 if (bits(src1[lane], 2)) {
445 // is -infinity
446 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
447 vcc.setBit(lane, 1);
448 continue;
449 }
450 }
451 if (bits(src1[lane], 3)) {
452 // is -normal
453 if (std::isnormal(src0[lane])
454 && std::signbit(src0[lane])) {
455 vcc.setBit(lane, 1);
456 continue;
457 }
458 }
459 if (bits(src1[lane], 4)) {
460 // is -denormal
461 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
462 && std::signbit(src0[lane])) {
463 vcc.setBit(lane, 1);
464 continue;
465 }
466 }
467 if (bits(src1[lane], 5)) {
468 // is -zero
469 if (std::fpclassify(src0[lane]) == FP_ZERO
470 && std::signbit(src0[lane])) {
471 vcc.setBit(lane, 1);
472 continue;
473 }
474 }
475 if (bits(src1[lane], 6)) {
476 // is +zero
477 if (std::fpclassify(src0[lane]) == FP_ZERO
478 && !std::signbit(src0[lane])) {
479 vcc.setBit(lane, 1);
480 continue;
481 }
482 }
483 if (bits(src1[lane], 7)) {
484 // is +denormal
485 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
486 && !std::signbit(src0[lane])) {
487 vcc.setBit(lane, 1);
488 continue;
489 }
490 }
491 if (bits(src1[lane], 8)) {
492 // is +normal
493 if (std::isnormal(src0[lane])
494 && !std::signbit(src0[lane])) {
495 vcc.setBit(lane, 1);
496 continue;
497 }
498 }
499 if (bits(src1[lane], 9)) {
500 // is +infinity
501 if (std::isinf(src0[lane])
502 && !std::signbit(src0[lane])) {
503 vcc.setBit(lane, 1);
504 continue;
505 }
506 }
507 }
508 }
509
510 vcc.write();
511 wf->execMask() = vcc.rawData();
512 } // execute
513 // --- Inst_VOPC__V_CMP_CLASS_F16 class methods ---
514
515 Inst_VOPC__V_CMP_CLASS_F16::Inst_VOPC__V_CMP_CLASS_F16(InFmt_VOPC *iFmt)
516 : Inst_VOPC(iFmt, "v_cmp_class_f16")
517 {
518 setFlag(ALU);
519 setFlag(F16);
520 } // Inst_VOPC__V_CMP_CLASS_F16
521
522 Inst_VOPC__V_CMP_CLASS_F16::~Inst_VOPC__V_CMP_CLASS_F16()
523 {
524 } // ~Inst_VOPC__V_CMP_CLASS_F16
525
526 // --- description from .arch file ---
527 // VCC = IEEE numeric class function specified in S1.u, performed on S0.f16
528 // The function reports true if the floating point value is *any* of the
529 // --- numeric types selected in S1.u according to the following list:
530 // S1.u[0] -- value is a signaling NaN.
531 // S1.u[1] -- value is a quiet NaN.
532 // S1.u[2] -- value is negative infinity.
533 // S1.u[3] -- value is a negative normal value.
534 // S1.u[4] -- value is a negative denormal value.
535 // S1.u[5] -- value is negative zero.
536 // S1.u[6] -- value is positive zero.
537 // S1.u[7] -- value is a positive denormal value.
538 // S1.u[8] -- value is a positive normal value.
539 // S1.u[9] -- value is positive infinity.
540 void
545 // --- Inst_VOPC__V_CMPX_CLASS_F16 class methods ---
546
547 Inst_VOPC__V_CMPX_CLASS_F16::Inst_VOPC__V_CMPX_CLASS_F16(InFmt_VOPC *iFmt)
548 : Inst_VOPC(iFmt, "v_cmpx_class_f16")
549 {
550 setFlag(ALU);
551 setFlag(F16);
552 setFlag(WritesEXEC);
553 } // Inst_VOPC__V_CMPX_CLASS_F16
554
555 Inst_VOPC__V_CMPX_CLASS_F16::~Inst_VOPC__V_CMPX_CLASS_F16()
556 {
557 } // ~Inst_VOPC__V_CMPX_CLASS_F16
558
559 // --- description from .arch file ---
560 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
561 // --- S0.f16
562 // The function reports true if the floating point value is *any* of the
563 // --- numeric types selected in S1.u according to the following list:
564 // S1.u[0] -- value is a signaling NaN.
565 // S1.u[1] -- value is a quiet NaN.
566 // S1.u[2] -- value is negative infinity.
567 // S1.u[3] -- value is a negative normal value.
568 // S1.u[4] -- value is a negative denormal value.
569 // S1.u[5] -- value is negative zero.
570 // S1.u[6] -- value is positive zero.
571 // S1.u[7] -- value is a positive denormal value.
572 // S1.u[8] -- value is a positive normal value.
573 // S1.u[9] -- value is positive infinity.
574 void
579 // --- Inst_VOPC__V_CMP_F_F16 class methods ---
580
581 Inst_VOPC__V_CMP_F_F16::Inst_VOPC__V_CMP_F_F16(InFmt_VOPC *iFmt)
582 : Inst_VOPC(iFmt, "v_cmp_f_f16")
583 {
584 setFlag(ALU);
585 setFlag(F16);
586 } // Inst_VOPC__V_CMP_F_F16
587
588 Inst_VOPC__V_CMP_F_F16::~Inst_VOPC__V_CMP_F_F16()
589 {
590 } // ~Inst_VOPC__V_CMP_F_F16
591
592 // --- description from .arch file ---
593 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
594 void
595 Inst_VOPC__V_CMP_F_F16::execute(GPUDynInstPtr gpuDynInst)
596 {
597 panicUnimplemented();
598 } // execute
599 // --- Inst_VOPC__V_CMP_LT_F16 class methods ---
600
601 Inst_VOPC__V_CMP_LT_F16::Inst_VOPC__V_CMP_LT_F16(InFmt_VOPC *iFmt)
602 : Inst_VOPC(iFmt, "v_cmp_lt_f16")
603 {
604 setFlag(ALU);
605 setFlag(F16);
606 } // Inst_VOPC__V_CMP_LT_F16
607
608 Inst_VOPC__V_CMP_LT_F16::~Inst_VOPC__V_CMP_LT_F16()
609 {
610 } // ~Inst_VOPC__V_CMP_LT_F16
611
612 // --- description from .arch file ---
613 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
614 void
615 Inst_VOPC__V_CMP_LT_F16::execute(GPUDynInstPtr gpuDynInst)
616 {
617 panicUnimplemented();
618 } // execute
619 // --- Inst_VOPC__V_CMP_EQ_F16 class methods ---
620
621 Inst_VOPC__V_CMP_EQ_F16::Inst_VOPC__V_CMP_EQ_F16(InFmt_VOPC *iFmt)
622 : Inst_VOPC(iFmt, "v_cmp_eq_f16")
623 {
624 setFlag(ALU);
625 setFlag(F16);
626 } // Inst_VOPC__V_CMP_EQ_F16
627
628 Inst_VOPC__V_CMP_EQ_F16::~Inst_VOPC__V_CMP_EQ_F16()
629 {
630 } // ~Inst_VOPC__V_CMP_EQ_F16
631
632 // --- description from .arch file ---
633 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
634 void
635 Inst_VOPC__V_CMP_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
636 {
637 panicUnimplemented();
638 } // execute
639 // --- Inst_VOPC__V_CMP_LE_F16 class methods ---
640
641 Inst_VOPC__V_CMP_LE_F16::Inst_VOPC__V_CMP_LE_F16(InFmt_VOPC *iFmt)
642 : Inst_VOPC(iFmt, "v_cmp_le_f16")
643 {
644 setFlag(ALU);
645 setFlag(F16);
646 } // Inst_VOPC__V_CMP_LE_F16
647
648 Inst_VOPC__V_CMP_LE_F16::~Inst_VOPC__V_CMP_LE_F16()
649 {
650 } // ~Inst_VOPC__V_CMP_LE_F16
651
652 // --- description from .arch file ---
653 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
654 void
655 Inst_VOPC__V_CMP_LE_F16::execute(GPUDynInstPtr gpuDynInst)
656 {
657 panicUnimplemented();
658 } // execute
659 // --- Inst_VOPC__V_CMP_GT_F16 class methods ---
660
661 Inst_VOPC__V_CMP_GT_F16::Inst_VOPC__V_CMP_GT_F16(InFmt_VOPC *iFmt)
662 : Inst_VOPC(iFmt, "v_cmp_gt_f16")
663 {
664 setFlag(ALU);
665 setFlag(F16);
666 } // Inst_VOPC__V_CMP_GT_F16
667
668 Inst_VOPC__V_CMP_GT_F16::~Inst_VOPC__V_CMP_GT_F16()
669 {
670 } // ~Inst_VOPC__V_CMP_GT_F16
671
672 // --- description from .arch file ---
673 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
674 void
675 Inst_VOPC__V_CMP_GT_F16::execute(GPUDynInstPtr gpuDynInst)
676 {
677 panicUnimplemented();
678 } // execute
679 // --- Inst_VOPC__V_CMP_LG_F16 class methods ---
680
681 Inst_VOPC__V_CMP_LG_F16::Inst_VOPC__V_CMP_LG_F16(InFmt_VOPC *iFmt)
682 : Inst_VOPC(iFmt, "v_cmp_lg_f16")
683 {
684 setFlag(ALU);
685 setFlag(F16);
686 } // Inst_VOPC__V_CMP_LG_F16
687
688 Inst_VOPC__V_CMP_LG_F16::~Inst_VOPC__V_CMP_LG_F16()
689 {
690 } // ~Inst_VOPC__V_CMP_LG_F16
691
692 // --- description from .arch file ---
693 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
694 void
695 Inst_VOPC__V_CMP_LG_F16::execute(GPUDynInstPtr gpuDynInst)
696 {
697 panicUnimplemented();
698 } // execute
699 // --- Inst_VOPC__V_CMP_GE_F16 class methods ---
700
701 Inst_VOPC__V_CMP_GE_F16::Inst_VOPC__V_CMP_GE_F16(InFmt_VOPC *iFmt)
702 : Inst_VOPC(iFmt, "v_cmp_ge_f16")
703 {
704 setFlag(ALU);
705 setFlag(F16);
706 } // Inst_VOPC__V_CMP_GE_F16
707
708 Inst_VOPC__V_CMP_GE_F16::~Inst_VOPC__V_CMP_GE_F16()
709 {
710 } // ~Inst_VOPC__V_CMP_GE_F16
711
712 // --- description from .arch file ---
713 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
714 void
715 Inst_VOPC__V_CMP_GE_F16::execute(GPUDynInstPtr gpuDynInst)
716 {
717 panicUnimplemented();
718 } // execute
719 // --- Inst_VOPC__V_CMP_O_F16 class methods ---
720
721 Inst_VOPC__V_CMP_O_F16::Inst_VOPC__V_CMP_O_F16(InFmt_VOPC *iFmt)
722 : Inst_VOPC(iFmt, "v_cmp_o_f16")
723 {
724 setFlag(ALU);
725 setFlag(F16);
726 } // Inst_VOPC__V_CMP_O_F16
727
728 Inst_VOPC__V_CMP_O_F16::~Inst_VOPC__V_CMP_O_F16()
729 {
730 } // ~Inst_VOPC__V_CMP_O_F16
731
732 // --- description from .arch file ---
733 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
734 void
735 Inst_VOPC__V_CMP_O_F16::execute(GPUDynInstPtr gpuDynInst)
736 {
737 panicUnimplemented();
738 } // execute
739 // --- Inst_VOPC__V_CMP_U_F16 class methods ---
740
741 Inst_VOPC__V_CMP_U_F16::Inst_VOPC__V_CMP_U_F16(InFmt_VOPC *iFmt)
742 : Inst_VOPC(iFmt, "v_cmp_u_f16")
743 {
744 setFlag(ALU);
745 setFlag(F16);
746 } // Inst_VOPC__V_CMP_U_F16
747
748 Inst_VOPC__V_CMP_U_F16::~Inst_VOPC__V_CMP_U_F16()
749 {
750 } // ~Inst_VOPC__V_CMP_U_F16
751
752 // --- description from .arch file ---
753 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
754 void
755 Inst_VOPC__V_CMP_U_F16::execute(GPUDynInstPtr gpuDynInst)
756 {
757 panicUnimplemented();
758 } // execute
759 // --- Inst_VOPC__V_CMP_NGE_F16 class methods ---
760
761 Inst_VOPC__V_CMP_NGE_F16::Inst_VOPC__V_CMP_NGE_F16(InFmt_VOPC *iFmt)
762 : Inst_VOPC(iFmt, "v_cmp_nge_f16")
763 {
764 setFlag(ALU);
765 setFlag(F16);
766 } // Inst_VOPC__V_CMP_NGE_F16
767
768 Inst_VOPC__V_CMP_NGE_F16::~Inst_VOPC__V_CMP_NGE_F16()
769 {
770 } // ~Inst_VOPC__V_CMP_NGE_F16
771
772 // --- description from .arch file ---
773 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
774 void
775 Inst_VOPC__V_CMP_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
776 {
777 panicUnimplemented();
778 } // execute
779 // --- Inst_VOPC__V_CMP_NLG_F16 class methods ---
780
781 Inst_VOPC__V_CMP_NLG_F16::Inst_VOPC__V_CMP_NLG_F16(InFmt_VOPC *iFmt)
782 : Inst_VOPC(iFmt, "v_cmp_nlg_f16")
783 {
784 setFlag(ALU);
785 setFlag(F16);
786 } // Inst_VOPC__V_CMP_NLG_F16
787
788 Inst_VOPC__V_CMP_NLG_F16::~Inst_VOPC__V_CMP_NLG_F16()
789 {
790 } // ~Inst_VOPC__V_CMP_NLG_F16
791
792 // --- description from .arch file ---
793 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
794 void
795 Inst_VOPC__V_CMP_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
796 {
797 panicUnimplemented();
798 } // execute
799 // --- Inst_VOPC__V_CMP_NGT_F16 class methods ---
800
801 Inst_VOPC__V_CMP_NGT_F16::Inst_VOPC__V_CMP_NGT_F16(InFmt_VOPC *iFmt)
802 : Inst_VOPC(iFmt, "v_cmp_ngt_f16")
803 {
804 setFlag(ALU);
805 setFlag(F16);
806 } // Inst_VOPC__V_CMP_NGT_F16
807
808 Inst_VOPC__V_CMP_NGT_F16::~Inst_VOPC__V_CMP_NGT_F16()
809 {
810 } // ~Inst_VOPC__V_CMP_NGT_F16
811
812 // --- description from .arch file ---
813 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
814 void
815 Inst_VOPC__V_CMP_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
816 {
817 panicUnimplemented();
818 } // execute
819 // --- Inst_VOPC__V_CMP_NLE_F16 class methods ---
820
821 Inst_VOPC__V_CMP_NLE_F16::Inst_VOPC__V_CMP_NLE_F16(InFmt_VOPC *iFmt)
822 : Inst_VOPC(iFmt, "v_cmp_nle_f16")
823 {
824 setFlag(ALU);
825 setFlag(F16);
826 } // Inst_VOPC__V_CMP_NLE_F16
827
828 Inst_VOPC__V_CMP_NLE_F16::~Inst_VOPC__V_CMP_NLE_F16()
829 {
830 } // ~Inst_VOPC__V_CMP_NLE_F16
831
832 // --- description from .arch file ---
833 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
834 void
835 Inst_VOPC__V_CMP_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
836 {
837 panicUnimplemented();
838 } // execute
839 // --- Inst_VOPC__V_CMP_NEQ_F16 class methods ---
840
841 Inst_VOPC__V_CMP_NEQ_F16::Inst_VOPC__V_CMP_NEQ_F16(InFmt_VOPC *iFmt)
842 : Inst_VOPC(iFmt, "v_cmp_neq_f16")
843 {
844 setFlag(ALU);
845 setFlag(F16);
846 } // Inst_VOPC__V_CMP_NEQ_F16
847
848 Inst_VOPC__V_CMP_NEQ_F16::~Inst_VOPC__V_CMP_NEQ_F16()
849 {
850 } // ~Inst_VOPC__V_CMP_NEQ_F16
851
852 // --- description from .arch file ---
853 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
854 void
855 Inst_VOPC__V_CMP_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
856 {
857 panicUnimplemented();
858 } // execute
859 // --- Inst_VOPC__V_CMP_NLT_F16 class methods ---
860
861 Inst_VOPC__V_CMP_NLT_F16::Inst_VOPC__V_CMP_NLT_F16(InFmt_VOPC *iFmt)
862 : Inst_VOPC(iFmt, "v_cmp_nlt_f16")
863 {
864 setFlag(ALU);
865 setFlag(F16);
866 } // Inst_VOPC__V_CMP_NLT_F16
867
868 Inst_VOPC__V_CMP_NLT_F16::~Inst_VOPC__V_CMP_NLT_F16()
869 {
870 } // ~Inst_VOPC__V_CMP_NLT_F16
871
872 // --- description from .arch file ---
873 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
874 void
875 Inst_VOPC__V_CMP_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
876 {
877 panicUnimplemented();
878 } // execute
879 // --- Inst_VOPC__V_CMP_TRU_F16 class methods ---
880
881 Inst_VOPC__V_CMP_TRU_F16::Inst_VOPC__V_CMP_TRU_F16(InFmt_VOPC *iFmt)
882 : Inst_VOPC(iFmt, "v_cmp_tru_f16")
883 {
884 setFlag(ALU);
885 setFlag(F16);
886 } // Inst_VOPC__V_CMP_TRU_F16
887
888 Inst_VOPC__V_CMP_TRU_F16::~Inst_VOPC__V_CMP_TRU_F16()
889 {
890 } // ~Inst_VOPC__V_CMP_TRU_F16
891
892 // --- description from .arch file ---
893 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
894 void
895 Inst_VOPC__V_CMP_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
896 {
897 panicUnimplemented();
898 } // execute
899 // --- Inst_VOPC__V_CMPX_F_F16 class methods ---
900
901 Inst_VOPC__V_CMPX_F_F16::Inst_VOPC__V_CMPX_F_F16(InFmt_VOPC *iFmt)
902 : Inst_VOPC(iFmt, "v_cmpx_f_f16")
903 {
904 setFlag(ALU);
905 setFlag(F16);
906 setFlag(WritesEXEC);
907 } // Inst_VOPC__V_CMPX_F_F16
908
909 Inst_VOPC__V_CMPX_F_F16::~Inst_VOPC__V_CMPX_F_F16()
910 {
911 } // ~Inst_VOPC__V_CMPX_F_F16
912
913 // --- description from .arch file ---
914 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
915 void
916 Inst_VOPC__V_CMPX_F_F16::execute(GPUDynInstPtr gpuDynInst)
917 {
918 panicUnimplemented();
919 } // execute
920 // --- Inst_VOPC__V_CMPX_LT_F16 class methods ---
921
922 Inst_VOPC__V_CMPX_LT_F16::Inst_VOPC__V_CMPX_LT_F16(InFmt_VOPC *iFmt)
923 : Inst_VOPC(iFmt, "v_cmpx_lt_f16")
924 {
925 setFlag(ALU);
926 setFlag(F16);
927 setFlag(WritesEXEC);
928 } // Inst_VOPC__V_CMPX_LT_F16
929
930 Inst_VOPC__V_CMPX_LT_F16::~Inst_VOPC__V_CMPX_LT_F16()
931 {
932 } // ~Inst_VOPC__V_CMPX_LT_F16
933
934 // --- description from .arch file ---
935 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
936 void
937 Inst_VOPC__V_CMPX_LT_F16::execute(GPUDynInstPtr gpuDynInst)
938 {
939 panicUnimplemented();
940 } // execute
941 // --- Inst_VOPC__V_CMPX_EQ_F16 class methods ---
942
943 Inst_VOPC__V_CMPX_EQ_F16::Inst_VOPC__V_CMPX_EQ_F16(InFmt_VOPC *iFmt)
944 : Inst_VOPC(iFmt, "v_cmpx_eq_f16")
945 {
946 setFlag(ALU);
947 setFlag(F16);
948 setFlag(WritesEXEC);
949 } // Inst_VOPC__V_CMPX_EQ_F16
950
951 Inst_VOPC__V_CMPX_EQ_F16::~Inst_VOPC__V_CMPX_EQ_F16()
952 {
953 } // ~Inst_VOPC__V_CMPX_EQ_F16
954
955 // --- description from .arch file ---
956 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
957 void
958 Inst_VOPC__V_CMPX_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
959 {
960 panicUnimplemented();
961 } // execute
962 // --- Inst_VOPC__V_CMPX_LE_F16 class methods ---
963
964 Inst_VOPC__V_CMPX_LE_F16::Inst_VOPC__V_CMPX_LE_F16(InFmt_VOPC *iFmt)
965 : Inst_VOPC(iFmt, "v_cmpx_le_f16")
966 {
967 setFlag(ALU);
968 setFlag(F16);
969 setFlag(WritesEXEC);
970 } // Inst_VOPC__V_CMPX_LE_F16
971
972 Inst_VOPC__V_CMPX_LE_F16::~Inst_VOPC__V_CMPX_LE_F16()
973 {
974 } // ~Inst_VOPC__V_CMPX_LE_F16
975
976 // --- description from .arch file ---
977 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
978 void
979 Inst_VOPC__V_CMPX_LE_F16::execute(GPUDynInstPtr gpuDynInst)
980 {
981 panicUnimplemented();
982 } // execute
983 // --- Inst_VOPC__V_CMPX_GT_F16 class methods ---
984
985 Inst_VOPC__V_CMPX_GT_F16::Inst_VOPC__V_CMPX_GT_F16(InFmt_VOPC *iFmt)
986 : Inst_VOPC(iFmt, "v_cmpx_gt_f16")
987 {
988 setFlag(ALU);
989 setFlag(F16);
990 setFlag(WritesEXEC);
991 } // Inst_VOPC__V_CMPX_GT_F16
992
993 Inst_VOPC__V_CMPX_GT_F16::~Inst_VOPC__V_CMPX_GT_F16()
994 {
995 } // ~Inst_VOPC__V_CMPX_GT_F16
996
997 // --- description from .arch file ---
998 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
999 void
1000 Inst_VOPC__V_CMPX_GT_F16::execute(GPUDynInstPtr gpuDynInst)
1001 {
1002 panicUnimplemented();
1003 } // execute
1004 // --- Inst_VOPC__V_CMPX_LG_F16 class methods ---
1005
1006 Inst_VOPC__V_CMPX_LG_F16::Inst_VOPC__V_CMPX_LG_F16(InFmt_VOPC *iFmt)
1007 : Inst_VOPC(iFmt, "v_cmpx_lg_f16")
1008 {
1009 setFlag(ALU);
1010 setFlag(F16);
1011 setFlag(WritesEXEC);
1012 } // Inst_VOPC__V_CMPX_LG_F16
1013
1014 Inst_VOPC__V_CMPX_LG_F16::~Inst_VOPC__V_CMPX_LG_F16()
1015 {
1016 } // ~Inst_VOPC__V_CMPX_LG_F16
1017
1018 // --- description from .arch file ---
1019 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1020 void
1021 Inst_VOPC__V_CMPX_LG_F16::execute(GPUDynInstPtr gpuDynInst)
1022 {
1023 panicUnimplemented();
1024 } // execute
1025 // --- Inst_VOPC__V_CMPX_GE_F16 class methods ---
1026
1027 Inst_VOPC__V_CMPX_GE_F16::Inst_VOPC__V_CMPX_GE_F16(InFmt_VOPC *iFmt)
1028 : Inst_VOPC(iFmt, "v_cmpx_ge_f16")
1029 {
1030 setFlag(ALU);
1031 setFlag(F16);
1032 setFlag(WritesEXEC);
1033 } // Inst_VOPC__V_CMPX_GE_F16
1034
1035 Inst_VOPC__V_CMPX_GE_F16::~Inst_VOPC__V_CMPX_GE_F16()
1036 {
1037 } // ~Inst_VOPC__V_CMPX_GE_F16
1038
1039 // --- description from .arch file ---
1040 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1041 void
1042 Inst_VOPC__V_CMPX_GE_F16::execute(GPUDynInstPtr gpuDynInst)
1043 {
1044 panicUnimplemented();
1045 } // execute
1046 // --- Inst_VOPC__V_CMPX_O_F16 class methods ---
1047
1048 Inst_VOPC__V_CMPX_O_F16::Inst_VOPC__V_CMPX_O_F16(InFmt_VOPC *iFmt)
1049 : Inst_VOPC(iFmt, "v_cmpx_o_f16")
1050 {
1051 setFlag(ALU);
1052 setFlag(F16);
1053 setFlag(WritesEXEC);
1054 } // Inst_VOPC__V_CMPX_O_F16
1055
1056 Inst_VOPC__V_CMPX_O_F16::~Inst_VOPC__V_CMPX_O_F16()
1057 {
1058 } // ~Inst_VOPC__V_CMPX_O_F16
1059
1060 // --- description from .arch file ---
1061 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
1062 // encoding.
1063 void
1064 Inst_VOPC__V_CMPX_O_F16::execute(GPUDynInstPtr gpuDynInst)
1065 {
1066 panicUnimplemented();
1067 } // execute
1068 // --- Inst_VOPC__V_CMPX_U_F16 class methods ---
1069
1070 Inst_VOPC__V_CMPX_U_F16::Inst_VOPC__V_CMPX_U_F16(InFmt_VOPC *iFmt)
1071 : Inst_VOPC(iFmt, "v_cmpx_u_f16")
1072 {
1073 setFlag(ALU);
1074 setFlag(F16);
1075 setFlag(WritesEXEC);
1076 } // Inst_VOPC__V_CMPX_U_F16
1077
1078 Inst_VOPC__V_CMPX_U_F16::~Inst_VOPC__V_CMPX_U_F16()
1079 {
1080 } // ~Inst_VOPC__V_CMPX_U_F16
1081
1082 // --- description from .arch file ---
1083 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
1084 // encoding.
1085 void
1086 Inst_VOPC__V_CMPX_U_F16::execute(GPUDynInstPtr gpuDynInst)
1087 {
1088 panicUnimplemented();
1089 } // execute
1090 // --- Inst_VOPC__V_CMPX_NGE_F16 class methods ---
1091
1092 Inst_VOPC__V_CMPX_NGE_F16::Inst_VOPC__V_CMPX_NGE_F16(InFmt_VOPC *iFmt)
1093 : Inst_VOPC(iFmt, "v_cmpx_nge_f16")
1094 {
1095 setFlag(ALU);
1096 setFlag(F16);
1097 setFlag(WritesEXEC);
1098 } // Inst_VOPC__V_CMPX_NGE_F16
1099
1100 Inst_VOPC__V_CMPX_NGE_F16::~Inst_VOPC__V_CMPX_NGE_F16()
1101 {
1102 } // ~Inst_VOPC__V_CMPX_NGE_F16
1103
1104 // --- description from .arch file ---
1105 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
1106 void
1107 Inst_VOPC__V_CMPX_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
1108 {
1109 panicUnimplemented();
1110 } // execute
1111 // --- Inst_VOPC__V_CMPX_NLG_F16 class methods ---
1112
1113 Inst_VOPC__V_CMPX_NLG_F16::Inst_VOPC__V_CMPX_NLG_F16(InFmt_VOPC *iFmt)
1114 : Inst_VOPC(iFmt, "v_cmpx_nlg_f16")
1115 {
1116 setFlag(ALU);
1117 setFlag(F16);
1118 setFlag(WritesEXEC);
1119 } // Inst_VOPC__V_CMPX_NLG_F16
1120
1121 Inst_VOPC__V_CMPX_NLG_F16::~Inst_VOPC__V_CMPX_NLG_F16()
1122 {
1123 } // ~Inst_VOPC__V_CMPX_NLG_F16
1124
1125 // --- description from .arch file ---
1126 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
1127 void
1128 Inst_VOPC__V_CMPX_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
1129 {
1130 panicUnimplemented();
1131 } // execute
1132 // --- Inst_VOPC__V_CMPX_NGT_F16 class methods ---
1133
1134 Inst_VOPC__V_CMPX_NGT_F16::Inst_VOPC__V_CMPX_NGT_F16(InFmt_VOPC *iFmt)
1135 : Inst_VOPC(iFmt, "v_cmpx_ngt_f16")
1136 {
1137 setFlag(ALU);
1138 setFlag(F16);
1139 setFlag(WritesEXEC);
1140 } // Inst_VOPC__V_CMPX_NGT_F16
1141
1142 Inst_VOPC__V_CMPX_NGT_F16::~Inst_VOPC__V_CMPX_NGT_F16()
1143 {
1144 } // ~Inst_VOPC__V_CMPX_NGT_F16
1145
1146 // --- description from .arch file ---
1147 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
1148 void
1149 Inst_VOPC__V_CMPX_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
1150 {
1151 panicUnimplemented();
1152 } // execute
1153 // --- Inst_VOPC__V_CMPX_NLE_F16 class methods ---
1154
1155 Inst_VOPC__V_CMPX_NLE_F16::Inst_VOPC__V_CMPX_NLE_F16(InFmt_VOPC *iFmt)
1156 : Inst_VOPC(iFmt, "v_cmpx_nle_f16")
1157 {
1158 setFlag(ALU);
1159 setFlag(F16);
1160 setFlag(WritesEXEC);
1161 } // Inst_VOPC__V_CMPX_NLE_F16
1162
1163 Inst_VOPC__V_CMPX_NLE_F16::~Inst_VOPC__V_CMPX_NLE_F16()
1164 {
1165 } // ~Inst_VOPC__V_CMPX_NLE_F16
1166
1167 // --- description from .arch file ---
1168 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
1169 void
1170 Inst_VOPC__V_CMPX_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
1171 {
1172 panicUnimplemented();
1173 } // execute
1174 // --- Inst_VOPC__V_CMPX_NEQ_F16 class methods ---
1175
1176 Inst_VOPC__V_CMPX_NEQ_F16::Inst_VOPC__V_CMPX_NEQ_F16(InFmt_VOPC *iFmt)
1177 : Inst_VOPC(iFmt, "v_cmpx_neq_f16")
1178 {
1179 setFlag(ALU);
1180 setFlag(F16);
1181 setFlag(WritesEXEC);
1182 } // Inst_VOPC__V_CMPX_NEQ_F16
1183
1184 Inst_VOPC__V_CMPX_NEQ_F16::~Inst_VOPC__V_CMPX_NEQ_F16()
1185 {
1186 } // ~Inst_VOPC__V_CMPX_NEQ_F16
1187
1188 // --- description from .arch file ---
1189 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
1190 void
1191 Inst_VOPC__V_CMPX_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
1192 {
1193 panicUnimplemented();
1194 } // execute
1195 // --- Inst_VOPC__V_CMPX_NLT_F16 class methods ---
1196
1197 Inst_VOPC__V_CMPX_NLT_F16::Inst_VOPC__V_CMPX_NLT_F16(InFmt_VOPC *iFmt)
1198 : Inst_VOPC(iFmt, "v_cmpx_nlt_f16")
1199 {
1200 setFlag(ALU);
1201 setFlag(F16);
1202 setFlag(WritesEXEC);
1203 } // Inst_VOPC__V_CMPX_NLT_F16
1204
1205 Inst_VOPC__V_CMPX_NLT_F16::~Inst_VOPC__V_CMPX_NLT_F16()
1206 {
1207 } // ~Inst_VOPC__V_CMPX_NLT_F16
1208
1209 // --- description from .arch file ---
1210 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
1211 void
1212 Inst_VOPC__V_CMPX_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
1213 {
1214 panicUnimplemented();
1215 } // execute
1216 // --- Inst_VOPC__V_CMPX_TRU_F16 class methods ---
1217
1218 Inst_VOPC__V_CMPX_TRU_F16::Inst_VOPC__V_CMPX_TRU_F16(InFmt_VOPC *iFmt)
1219 : Inst_VOPC(iFmt, "v_cmpx_tru_f16")
1220 {
1221 setFlag(ALU);
1222 setFlag(F16);
1223 setFlag(WritesEXEC);
1224 } // Inst_VOPC__V_CMPX_TRU_F16
1225
1226 Inst_VOPC__V_CMPX_TRU_F16::~Inst_VOPC__V_CMPX_TRU_F16()
1227 {
1228 } // ~Inst_VOPC__V_CMPX_TRU_F16
1229
1230 // --- description from .arch file ---
1231 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
1232 void
1233 Inst_VOPC__V_CMPX_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
1234 {
1235 panicUnimplemented();
1236 } // execute
1237 // --- Inst_VOPC__V_CMP_F_F32 class methods ---
1238
1239 Inst_VOPC__V_CMP_F_F32::Inst_VOPC__V_CMP_F_F32(InFmt_VOPC *iFmt)
1240 : Inst_VOPC(iFmt, "v_cmp_f_f32")
1241 {
1242 setFlag(ALU);
1243 setFlag(F32);
1244 } // Inst_VOPC__V_CMP_F_F32
1245
1246 Inst_VOPC__V_CMP_F_F32::~Inst_VOPC__V_CMP_F_F32()
1247 {
1248 } // ~Inst_VOPC__V_CMP_F_F32
1249
1250 // --- description from .arch file ---
1251 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
1252 void
1253 Inst_VOPC__V_CMP_F_F32::execute(GPUDynInstPtr gpuDynInst)
1254 {
1255 Wavefront *wf = gpuDynInst->wavefront();
1256 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1257
1258 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1259 if (wf->execMask(lane)) {
1260 vcc.setBit(lane, 0);
1261 }
1262 }
1263
1264 vcc.write();
1265 } // execute
1266 // --- Inst_VOPC__V_CMP_LT_F32 class methods ---
1267
1268 Inst_VOPC__V_CMP_LT_F32::Inst_VOPC__V_CMP_LT_F32(InFmt_VOPC *iFmt)
1269 : Inst_VOPC(iFmt, "v_cmp_lt_f32")
1270 {
1271 setFlag(ALU);
1272 setFlag(F32);
1273 } // Inst_VOPC__V_CMP_LT_F32
1274
1275 Inst_VOPC__V_CMP_LT_F32::~Inst_VOPC__V_CMP_LT_F32()
1276 {
1277 } // ~Inst_VOPC__V_CMP_LT_F32
1278
1279 // --- description from .arch file ---
1280 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
1281 void
1282 Inst_VOPC__V_CMP_LT_F32::execute(GPUDynInstPtr gpuDynInst)
1283 {
1284 Wavefront *wf = gpuDynInst->wavefront();
1285 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1286 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1287 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1288
1289 src0.readSrc();
1290 src1.read();
1291
1292 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1293 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1294
1295 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1296 if (wf->execMask(lane)) {
1297 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
1298 }
1299 }
1300
1301 vcc.write();
1302 } // execute
1303 // --- Inst_VOPC__V_CMP_EQ_F32 class methods ---
1304
1305 Inst_VOPC__V_CMP_EQ_F32::Inst_VOPC__V_CMP_EQ_F32(InFmt_VOPC *iFmt)
1306 : Inst_VOPC(iFmt, "v_cmp_eq_f32")
1307 {
1308 setFlag(ALU);
1309 setFlag(F32);
1310 } // Inst_VOPC__V_CMP_EQ_F32
1311
1312 Inst_VOPC__V_CMP_EQ_F32::~Inst_VOPC__V_CMP_EQ_F32()
1313 {
1314 } // ~Inst_VOPC__V_CMP_EQ_F32
1315
1316 // --- description from .arch file ---
1317 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
1318 void
1319 Inst_VOPC__V_CMP_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
1320 {
1321 Wavefront *wf = gpuDynInst->wavefront();
1322 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1323 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1324 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1325
1326 src0.readSrc();
1327 src1.read();
1328
1329 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1330 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1331
1332 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1333 if (wf->execMask(lane)) {
1334 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
1335 }
1336 }
1337
1338 vcc.write();
1339 } // execute
1340 // --- Inst_VOPC__V_CMP_LE_F32 class methods ---
1341
1342 Inst_VOPC__V_CMP_LE_F32::Inst_VOPC__V_CMP_LE_F32(InFmt_VOPC *iFmt)
1343 : Inst_VOPC(iFmt, "v_cmp_le_f32")
1344 {
1345 setFlag(ALU);
1346 setFlag(F32);
1347 } // Inst_VOPC__V_CMP_LE_F32
1348
1349 Inst_VOPC__V_CMP_LE_F32::~Inst_VOPC__V_CMP_LE_F32()
1350 {
1351 } // ~Inst_VOPC__V_CMP_LE_F32
1352
1353 // --- description from .arch file ---
1354 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
1355 void
1356 Inst_VOPC__V_CMP_LE_F32::execute(GPUDynInstPtr gpuDynInst)
1357 {
1358 Wavefront *wf = gpuDynInst->wavefront();
1359 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1360 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1361 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1362
1363 src0.readSrc();
1364 src1.read();
1365
1366 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1367 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1368
1369 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1370 if (wf->execMask(lane)) {
1371 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
1372 }
1373 }
1374
1375 vcc.write();
1376 } // execute
1377 // --- Inst_VOPC__V_CMP_GT_F32 class methods ---
1378
1379 Inst_VOPC__V_CMP_GT_F32::Inst_VOPC__V_CMP_GT_F32(InFmt_VOPC *iFmt)
1380 : Inst_VOPC(iFmt, "v_cmp_gt_f32")
1381 {
1382 setFlag(ALU);
1383 setFlag(F32);
1384 } // Inst_VOPC__V_CMP_GT_F32
1385
1386 Inst_VOPC__V_CMP_GT_F32::~Inst_VOPC__V_CMP_GT_F32()
1387 {
1388 } // ~Inst_VOPC__V_CMP_GT_F32
1389
1390 // --- description from .arch file ---
1391 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
1392 void
1393 Inst_VOPC__V_CMP_GT_F32::execute(GPUDynInstPtr gpuDynInst)
1394 {
1395 Wavefront *wf = gpuDynInst->wavefront();
1396 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1397 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1398 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1399
1400 src0.readSrc();
1401 src1.read();
1402
1403 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1404 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1405
1406 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1407 if (wf->execMask(lane)) {
1408 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
1409 }
1410 }
1411
1412 vcc.write();
1413 } // execute
1414 // --- Inst_VOPC__V_CMP_LG_F32 class methods ---
1415
1416 Inst_VOPC__V_CMP_LG_F32::Inst_VOPC__V_CMP_LG_F32(InFmt_VOPC *iFmt)
1417 : Inst_VOPC(iFmt, "v_cmp_lg_f32")
1418 {
1419 setFlag(ALU);
1420 setFlag(F32);
1421 } // Inst_VOPC__V_CMP_LG_F32
1422
1423 Inst_VOPC__V_CMP_LG_F32::~Inst_VOPC__V_CMP_LG_F32()
1424 {
1425 } // ~Inst_VOPC__V_CMP_LG_F32
1426
1427 // --- description from .arch file ---
1428 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1429 void
1430 Inst_VOPC__V_CMP_LG_F32::execute(GPUDynInstPtr gpuDynInst)
1431 {
1432 Wavefront *wf = gpuDynInst->wavefront();
1433 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1434 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1435 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1436
1437 src0.readSrc();
1438 src1.read();
1439
1440 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1441 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1442
1443 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1444 if (wf->execMask(lane)) {
1445 vcc.setBit(lane, (src0[lane] < src1[lane]
1446 || src0[lane] > src1[lane]) ? 1 : 0);
1447 }
1448 }
1449
1450 vcc.write();
1451 } // execute
1452 // --- Inst_VOPC__V_CMP_GE_F32 class methods ---
1453
1454 Inst_VOPC__V_CMP_GE_F32::Inst_VOPC__V_CMP_GE_F32(InFmt_VOPC *iFmt)
1455 : Inst_VOPC(iFmt, "v_cmp_ge_f32")
1456 {
1457 setFlag(ALU);
1458 setFlag(F32);
1459 } // Inst_VOPC__V_CMP_GE_F32
1460
1461 Inst_VOPC__V_CMP_GE_F32::~Inst_VOPC__V_CMP_GE_F32()
1462 {
1463 } // ~Inst_VOPC__V_CMP_GE_F32
1464
1465 // --- description from .arch file ---
1466 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1467 void
1468 Inst_VOPC__V_CMP_GE_F32::execute(GPUDynInstPtr gpuDynInst)
1469 {
1470 Wavefront *wf = gpuDynInst->wavefront();
1471 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1472 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1473 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1474
1475 src0.readSrc();
1476 src1.read();
1477
1478 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1479 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1480
1481 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1482 if (wf->execMask(lane)) {
1483 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
1484 }
1485 }
1486
1487 vcc.write();
1488 } // execute
1489 // --- Inst_VOPC__V_CMP_O_F32 class methods ---
1490
1491 Inst_VOPC__V_CMP_O_F32::Inst_VOPC__V_CMP_O_F32(InFmt_VOPC *iFmt)
1492 : Inst_VOPC(iFmt, "v_cmp_o_f32")
1493 {
1494 setFlag(ALU);
1495 setFlag(F32);
1496 } // Inst_VOPC__V_CMP_O_F32
1497
1498 Inst_VOPC__V_CMP_O_F32::~Inst_VOPC__V_CMP_O_F32()
1499 {
1500 } // ~Inst_VOPC__V_CMP_O_F32
1501
1502 // --- description from .arch file ---
1503 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
1504 void
1505 Inst_VOPC__V_CMP_O_F32::execute(GPUDynInstPtr gpuDynInst)
1506 {
1507 Wavefront *wf = gpuDynInst->wavefront();
1508 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1509 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1510 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1511
1512 src0.readSrc();
1513 src1.read();
1514
1515 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1516 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1517
1518 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1519 if (wf->execMask(lane)) {
1520 vcc.setBit(lane, (!std::isnan(src0[lane])
1521 && !std::isnan(src1[lane])) ? 1 : 0);
1522 }
1523 }
1524
1525 vcc.write();
1526 } // execute
1527 // --- Inst_VOPC__V_CMP_U_F32 class methods ---
1528
1529 Inst_VOPC__V_CMP_U_F32::Inst_VOPC__V_CMP_U_F32(InFmt_VOPC *iFmt)
1530 : Inst_VOPC(iFmt, "v_cmp_u_f32")
1531 {
1532 setFlag(ALU);
1533 setFlag(F32);
1534 } // Inst_VOPC__V_CMP_U_F32
1535
1536 Inst_VOPC__V_CMP_U_F32::~Inst_VOPC__V_CMP_U_F32()
1537 {
1538 } // ~Inst_VOPC__V_CMP_U_F32
1539
1540 // --- description from .arch file ---
1541 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
1542 void
1543 Inst_VOPC__V_CMP_U_F32::execute(GPUDynInstPtr gpuDynInst)
1544 {
1545 Wavefront *wf = gpuDynInst->wavefront();
1546 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1547 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1548 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1549
1550 src0.readSrc();
1551 src1.read();
1552
1553 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1554 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1555
1556 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1557 if (wf->execMask(lane)) {
1558 vcc.setBit(lane, (std::isnan(src0[lane])
1559 || std::isnan(src1[lane])) ? 1 : 0);
1560 }
1561 }
1562
1563 vcc.write();
1564 } // execute
1565 // --- Inst_VOPC__V_CMP_NGE_F32 class methods ---
1566
1567 Inst_VOPC__V_CMP_NGE_F32::Inst_VOPC__V_CMP_NGE_F32(InFmt_VOPC *iFmt)
1568 : Inst_VOPC(iFmt, "v_cmp_nge_f32")
1569 {
1570 setFlag(ALU);
1571 setFlag(F32);
1572 } // Inst_VOPC__V_CMP_NGE_F32
1573
1574 Inst_VOPC__V_CMP_NGE_F32::~Inst_VOPC__V_CMP_NGE_F32()
1575 {
1576 } // ~Inst_VOPC__V_CMP_NGE_F32
1577
1578 // --- description from .arch file ---
1579 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
1580 void
1581 Inst_VOPC__V_CMP_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
1582 {
1583 Wavefront *wf = gpuDynInst->wavefront();
1584 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1585 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1586 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1587
1588 src0.readSrc();
1589 src1.read();
1590
1591 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1592 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1593
1594 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1595 if (wf->execMask(lane)) {
1596 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
1597 }
1598 }
1599
1600 vcc.write();
1601 } // execute
1602 // --- Inst_VOPC__V_CMP_NLG_F32 class methods ---
1603
1604 Inst_VOPC__V_CMP_NLG_F32::Inst_VOPC__V_CMP_NLG_F32(InFmt_VOPC *iFmt)
1605 : Inst_VOPC(iFmt, "v_cmp_nlg_f32")
1606 {
1607 setFlag(ALU);
1608 setFlag(F32);
1609 } // Inst_VOPC__V_CMP_NLG_F32
1610
1611 Inst_VOPC__V_CMP_NLG_F32::~Inst_VOPC__V_CMP_NLG_F32()
1612 {
1613 } // ~Inst_VOPC__V_CMP_NLG_F32
1614
1615 // --- description from .arch file ---
1616 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
1617 void
1618 Inst_VOPC__V_CMP_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
1619 {
1620 Wavefront *wf = gpuDynInst->wavefront();
1621 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1622 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1623 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1624
1625 src0.readSrc();
1626 src1.read();
1627
1628 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1629 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1630
1631 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1632 if (wf->execMask(lane)) {
1633 vcc.setBit(lane, !(src0[lane] < src1[lane]
1634 || src0[lane] > src1[lane]) ? 1 : 0);
1635 }
1636 }
1637
1638 vcc.write();
1639 } // execute
1640 // --- Inst_VOPC__V_CMP_NGT_F32 class methods ---
1641
1642 Inst_VOPC__V_CMP_NGT_F32::Inst_VOPC__V_CMP_NGT_F32(InFmt_VOPC *iFmt)
1643 : Inst_VOPC(iFmt, "v_cmp_ngt_f32")
1644 {
1645 setFlag(ALU);
1646 setFlag(F32);
1647 } // Inst_VOPC__V_CMP_NGT_F32
1648
1649 Inst_VOPC__V_CMP_NGT_F32::~Inst_VOPC__V_CMP_NGT_F32()
1650 {
1651 } // ~Inst_VOPC__V_CMP_NGT_F32
1652
1653 // --- description from .arch file ---
1654 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
1655 void
1656 Inst_VOPC__V_CMP_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
1657 {
1658 Wavefront *wf = gpuDynInst->wavefront();
1659 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1660 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1661 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1662
1663 src0.readSrc();
1664 src1.read();
1665
1666 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1667 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1668
1669 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1670 if (wf->execMask(lane)) {
1671 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
1672 }
1673 }
1674
1675 vcc.write();
1676 } // execute
1677 // --- Inst_VOPC__V_CMP_NLE_F32 class methods ---
1678
1679 Inst_VOPC__V_CMP_NLE_F32::Inst_VOPC__V_CMP_NLE_F32(InFmt_VOPC *iFmt)
1680 : Inst_VOPC(iFmt, "v_cmp_nle_f32")
1681 {
1682 setFlag(ALU);
1683 setFlag(F32);
1684 } // Inst_VOPC__V_CMP_NLE_F32
1685
1686 Inst_VOPC__V_CMP_NLE_F32::~Inst_VOPC__V_CMP_NLE_F32()
1687 {
1688 } // ~Inst_VOPC__V_CMP_NLE_F32
1689
1690 // --- description from .arch file ---
1691 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
1692 void
1693 Inst_VOPC__V_CMP_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
1694 {
1695 Wavefront *wf = gpuDynInst->wavefront();
1696 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1697 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1698 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1699
1700 src0.readSrc();
1701 src1.read();
1702
1703 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1704 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1705
1706 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1707 if (wf->execMask(lane)) {
1708 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
1709 }
1710 }
1711
1712 vcc.write();
1713 } // execute
1714 // --- Inst_VOPC__V_CMP_NEQ_F32 class methods ---
1715
1716 Inst_VOPC__V_CMP_NEQ_F32::Inst_VOPC__V_CMP_NEQ_F32(InFmt_VOPC *iFmt)
1717 : Inst_VOPC(iFmt, "v_cmp_neq_f32")
1718 {
1719 setFlag(ALU);
1720 setFlag(F32);
1721 } // Inst_VOPC__V_CMP_NEQ_F32
1722
1723 Inst_VOPC__V_CMP_NEQ_F32::~Inst_VOPC__V_CMP_NEQ_F32()
1724 {
1725 } // ~Inst_VOPC__V_CMP_NEQ_F32
1726
1727 // --- description from .arch file ---
1728 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
1729 void
1730 Inst_VOPC__V_CMP_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
1731 {
1732 Wavefront *wf = gpuDynInst->wavefront();
1733 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1734 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1735 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1736
1737 src0.readSrc();
1738 src1.read();
1739
1740 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1741 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1742
1743 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1744 if (wf->execMask(lane)) {
1745 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
1746 }
1747 }
1748
1749 vcc.write();
1750 } // execute
1751 // --- Inst_VOPC__V_CMP_NLT_F32 class methods ---
1752
1753 Inst_VOPC__V_CMP_NLT_F32::Inst_VOPC__V_CMP_NLT_F32(InFmt_VOPC *iFmt)
1754 : Inst_VOPC(iFmt, "v_cmp_nlt_f32")
1755 {
1756 setFlag(ALU);
1757 setFlag(F32);
1758 } // Inst_VOPC__V_CMP_NLT_F32
1759
1760 Inst_VOPC__V_CMP_NLT_F32::~Inst_VOPC__V_CMP_NLT_F32()
1761 {
1762 } // ~Inst_VOPC__V_CMP_NLT_F32
1763
1764 // --- description from .arch file ---
1765 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
1766 void
1767 Inst_VOPC__V_CMP_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
1768 {
1769 Wavefront *wf = gpuDynInst->wavefront();
1770 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1771 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1772 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1773
1774 src0.readSrc();
1775 src1.read();
1776
1777 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1778 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1779
1780 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1781 if (wf->execMask(lane)) {
1782 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
1783 }
1784 }
1785
1786 vcc.write();
1787 } // execute
1788 // --- Inst_VOPC__V_CMP_TRU_F32 class methods ---
1789
1790 Inst_VOPC__V_CMP_TRU_F32::Inst_VOPC__V_CMP_TRU_F32(InFmt_VOPC *iFmt)
1791 : Inst_VOPC(iFmt, "v_cmp_tru_f32")
1792 {
1793 setFlag(ALU);
1794 setFlag(F32);
1795 } // Inst_VOPC__V_CMP_TRU_F32
1796
1797 Inst_VOPC__V_CMP_TRU_F32::~Inst_VOPC__V_CMP_TRU_F32()
1798 {
1799 } // ~Inst_VOPC__V_CMP_TRU_F32
1800
1801 // --- description from .arch file ---
1802 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
1803 void
1804 Inst_VOPC__V_CMP_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
1805 {
1806 Wavefront *wf = gpuDynInst->wavefront();
1807 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1808
1809 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1810 if (wf->execMask(lane)) {
1811 vcc.setBit(lane, 1);
1812 }
1813 }
1814
1815 vcc.write();
1816 } // execute
1817 // --- Inst_VOPC__V_CMPX_F_F32 class methods ---
1818
1819 Inst_VOPC__V_CMPX_F_F32::Inst_VOPC__V_CMPX_F_F32(InFmt_VOPC *iFmt)
1820 : Inst_VOPC(iFmt, "v_cmpx_f_f32")
1821 {
1822 setFlag(ALU);
1823 setFlag(F32);
1824 setFlag(WritesEXEC);
1825 } // Inst_VOPC__V_CMPX_F_F32
1826
1827 Inst_VOPC__V_CMPX_F_F32::~Inst_VOPC__V_CMPX_F_F32()
1828 {
1829 } // ~Inst_VOPC__V_CMPX_F_F32
1830
1831 // --- description from .arch file ---
1832 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
1833 void
1834 Inst_VOPC__V_CMPX_F_F32::execute(GPUDynInstPtr gpuDynInst)
1835 {
1836 Wavefront *wf = gpuDynInst->wavefront();
1837 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1838
1839 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1840 if (wf->execMask(lane)) {
1841 vcc.setBit(lane, 0);
1842 }
1843 }
1844
1845 vcc.write();
1846 wf->execMask() = vcc.rawData();
1847 } // execute
1848 // --- Inst_VOPC__V_CMPX_LT_F32 class methods ---
1849
1850 Inst_VOPC__V_CMPX_LT_F32::Inst_VOPC__V_CMPX_LT_F32(InFmt_VOPC *iFmt)
1851 : Inst_VOPC(iFmt, "v_cmpx_lt_f32")
1852 {
1853 setFlag(ALU);
1854 setFlag(F32);
1855 setFlag(WritesEXEC);
1856 } // Inst_VOPC__V_CMPX_LT_F32
1857
1858 Inst_VOPC__V_CMPX_LT_F32::~Inst_VOPC__V_CMPX_LT_F32()
1859 {
1860 } // ~Inst_VOPC__V_CMPX_LT_F32
1861
1862 // --- description from .arch file ---
1863 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
1864 void
1865 Inst_VOPC__V_CMPX_LT_F32::execute(GPUDynInstPtr gpuDynInst)
1866 {
1867 Wavefront *wf = gpuDynInst->wavefront();
1868 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1869 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1870 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1871
1872 src0.readSrc();
1873 src1.read();
1874
1875 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1876 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1877
1878 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1879 if (wf->execMask(lane)) {
1880 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
1881 }
1882 }
1883
1884 vcc.write();
1885 wf->execMask() = vcc.rawData();
1886 } // execute
1887 // --- Inst_VOPC__V_CMPX_EQ_F32 class methods ---
1888
1889 Inst_VOPC__V_CMPX_EQ_F32::Inst_VOPC__V_CMPX_EQ_F32(InFmt_VOPC *iFmt)
1890 : Inst_VOPC(iFmt, "v_cmpx_eq_f32")
1891 {
1892 setFlag(ALU);
1893 setFlag(F32);
1894 setFlag(WritesEXEC);
1895 } // Inst_VOPC__V_CMPX_EQ_F32
1896
1897 Inst_VOPC__V_CMPX_EQ_F32::~Inst_VOPC__V_CMPX_EQ_F32()
1898 {
1899 } // ~Inst_VOPC__V_CMPX_EQ_F32
1900
1901 // --- description from .arch file ---
1902 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
1903 void
1904 Inst_VOPC__V_CMPX_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
1905 {
1906 Wavefront *wf = gpuDynInst->wavefront();
1907 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1908 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1909 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1910
1911 src0.readSrc();
1912 src1.read();
1913
1914 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1915 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1916
1917 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1918 if (wf->execMask(lane)) {
1919 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
1920 }
1921 }
1922
1923 vcc.write();
1924 wf->execMask() = vcc.rawData();
1925 } // execute
1926 // --- Inst_VOPC__V_CMPX_LE_F32 class methods ---
1927
1928 Inst_VOPC__V_CMPX_LE_F32::Inst_VOPC__V_CMPX_LE_F32(InFmt_VOPC *iFmt)
1929 : Inst_VOPC(iFmt, "v_cmpx_le_f32")
1930 {
1931 setFlag(ALU);
1932 setFlag(F32);
1933 setFlag(WritesEXEC);
1934 } // Inst_VOPC__V_CMPX_LE_F32
1935
1936 Inst_VOPC__V_CMPX_LE_F32::~Inst_VOPC__V_CMPX_LE_F32()
1937 {
1938 } // ~Inst_VOPC__V_CMPX_LE_F32
1939
1940 // --- description from .arch file ---
1941 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
1942 void
1943 Inst_VOPC__V_CMPX_LE_F32::execute(GPUDynInstPtr gpuDynInst)
1944 {
1945 Wavefront *wf = gpuDynInst->wavefront();
1946 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1947 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1948 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1949
1950 src0.readSrc();
1951 src1.read();
1952
1953 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1954 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1955
1956 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1957 if (wf->execMask(lane)) {
1958 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
1959 }
1960 }
1961
1962 vcc.write();
1963 wf->execMask() = vcc.rawData();
1964 } // execute
1965 // --- Inst_VOPC__V_CMPX_GT_F32 class methods ---
1966
1967 Inst_VOPC__V_CMPX_GT_F32::Inst_VOPC__V_CMPX_GT_F32(InFmt_VOPC *iFmt)
1968 : Inst_VOPC(iFmt, "v_cmpx_gt_f32")
1969 {
1970 setFlag(ALU);
1971 setFlag(F32);
1972 setFlag(WritesEXEC);
1973 } // Inst_VOPC__V_CMPX_GT_F32
1974
1975 Inst_VOPC__V_CMPX_GT_F32::~Inst_VOPC__V_CMPX_GT_F32()
1976 {
1977 } // ~Inst_VOPC__V_CMPX_GT_F32
1978
1979 // --- description from .arch file ---
1980 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
1981 void
1982 Inst_VOPC__V_CMPX_GT_F32::execute(GPUDynInstPtr gpuDynInst)
1983 {
1984 Wavefront *wf = gpuDynInst->wavefront();
1985 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
1986 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
1987 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
1988
1989 src0.readSrc();
1990 src1.read();
1991
1992 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
1993 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
1994
1995 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1996 if (wf->execMask(lane)) {
1997 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
1998 }
1999 }
2000
2001 vcc.write();
2002 wf->execMask() = vcc.rawData();
2003 } // execute
2004 // --- Inst_VOPC__V_CMPX_LG_F32 class methods ---
2005
2006 Inst_VOPC__V_CMPX_LG_F32::Inst_VOPC__V_CMPX_LG_F32(InFmt_VOPC *iFmt)
2007 : Inst_VOPC(iFmt, "v_cmpx_lg_f32")
2008 {
2009 setFlag(ALU);
2010 setFlag(F32);
2011 setFlag(WritesEXEC);
2012 } // Inst_VOPC__V_CMPX_LG_F32
2013
2014 Inst_VOPC__V_CMPX_LG_F32::~Inst_VOPC__V_CMPX_LG_F32()
2015 {
2016 } // ~Inst_VOPC__V_CMPX_LG_F32
2017
2018 // --- description from .arch file ---
2019 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
2020 void
2021 Inst_VOPC__V_CMPX_LG_F32::execute(GPUDynInstPtr gpuDynInst)
2022 {
2023 Wavefront *wf = gpuDynInst->wavefront();
2024 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2025 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2026 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2027
2028 src0.readSrc();
2029 src1.read();
2030
2031 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2032 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2033
2034 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2035 if (wf->execMask(lane)) {
2036 vcc.setBit(lane, (src0[lane] < src1[lane]
2037 || src0[lane] > src1[lane]) ? 1 : 0);
2038 }
2039 }
2040
2041 vcc.write();
2042 wf->execMask() = vcc.rawData();
2043 } // execute
2044 // --- Inst_VOPC__V_CMPX_GE_F32 class methods ---
2045
2046 Inst_VOPC__V_CMPX_GE_F32::Inst_VOPC__V_CMPX_GE_F32(InFmt_VOPC *iFmt)
2047 : Inst_VOPC(iFmt, "v_cmpx_ge_f32")
2048 {
2049 setFlag(ALU);
2050 setFlag(F32);
2051 setFlag(WritesEXEC);
2052 } // Inst_VOPC__V_CMPX_GE_F32
2053
2054 Inst_VOPC__V_CMPX_GE_F32::~Inst_VOPC__V_CMPX_GE_F32()
2055 {
2056 } // ~Inst_VOPC__V_CMPX_GE_F32
2057
2058 // --- description from .arch file ---
2059 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
2060 void
2061 Inst_VOPC__V_CMPX_GE_F32::execute(GPUDynInstPtr gpuDynInst)
2062 {
2063 Wavefront *wf = gpuDynInst->wavefront();
2064 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2065 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2066 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2067
2068 src0.readSrc();
2069 src1.read();
2070
2071 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2072 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2073
2074 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2075 if (wf->execMask(lane)) {
2076 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
2077 }
2078 }
2079
2080 vcc.write();
2081 wf->execMask() = vcc.rawData();
2082 } // execute
2083 // --- Inst_VOPC__V_CMPX_O_F32 class methods ---
2084
2085 Inst_VOPC__V_CMPX_O_F32::Inst_VOPC__V_CMPX_O_F32(InFmt_VOPC *iFmt)
2086 : Inst_VOPC(iFmt, "v_cmpx_o_f32")
2087 {
2088 setFlag(ALU);
2089 setFlag(F32);
2090 setFlag(WritesEXEC);
2091 } // Inst_VOPC__V_CMPX_O_F32
2092
2093 Inst_VOPC__V_CMPX_O_F32::~Inst_VOPC__V_CMPX_O_F32()
2094 {
2095 } // ~Inst_VOPC__V_CMPX_O_F32
2096
2097 // --- description from .arch file ---
2098 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
2099 // encoding.
2100 void
2101 Inst_VOPC__V_CMPX_O_F32::execute(GPUDynInstPtr gpuDynInst)
2102 {
2103 Wavefront *wf = gpuDynInst->wavefront();
2104 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2105 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2106 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2107
2108 src0.readSrc();
2109 src1.read();
2110
2111 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2112 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2113
2114 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2115 if (wf->execMask(lane)) {
2116 vcc.setBit(lane, (!std::isnan(src0[lane])
2117 && !std::isnan(src1[lane])) ? 1 : 0);
2118 }
2119 }
2120
2121 vcc.write();
2122 wf->execMask() = vcc.rawData();
2123 } // execute
2124 // --- Inst_VOPC__V_CMPX_U_F32 class methods ---
2125
2126 Inst_VOPC__V_CMPX_U_F32::Inst_VOPC__V_CMPX_U_F32(InFmt_VOPC *iFmt)
2127 : Inst_VOPC(iFmt, "v_cmpx_u_f32")
2128 {
2129 setFlag(ALU);
2130 setFlag(F32);
2131 setFlag(WritesEXEC);
2132 } // Inst_VOPC__V_CMPX_U_F32
2133
2134 Inst_VOPC__V_CMPX_U_F32::~Inst_VOPC__V_CMPX_U_F32()
2135 {
2136 } // ~Inst_VOPC__V_CMPX_U_F32
2137
2138 // --- description from .arch file ---
2139 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
2140 // encoding.
2141 void
2142 Inst_VOPC__V_CMPX_U_F32::execute(GPUDynInstPtr gpuDynInst)
2143 {
2144 Wavefront *wf = gpuDynInst->wavefront();
2145 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2146 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2147 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2148
2149 src0.readSrc();
2150 src1.read();
2151
2152 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2153 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2154
2155 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2156 if (wf->execMask(lane)) {
2157 vcc.setBit(lane, (std::isnan(src0[lane])
2158 || std::isnan(src1[lane])) ? 1 : 0);
2159 }
2160 }
2161
2162 vcc.write();
2163 wf->execMask() = vcc.rawData();
2164 } // execute
2165 // --- Inst_VOPC__V_CMPX_NGE_F32 class methods ---
2166
2167 Inst_VOPC__V_CMPX_NGE_F32::Inst_VOPC__V_CMPX_NGE_F32(InFmt_VOPC *iFmt)
2168 : Inst_VOPC(iFmt, "v_cmpx_nge_f32")
2169 {
2170 setFlag(ALU);
2171 setFlag(F32);
2172 setFlag(WritesEXEC);
2173 } // Inst_VOPC__V_CMPX_NGE_F32
2174
2175 Inst_VOPC__V_CMPX_NGE_F32::~Inst_VOPC__V_CMPX_NGE_F32()
2176 {
2177 } // ~Inst_VOPC__V_CMPX_NGE_F32
2178
2179 // --- description from .arch file ---
2180 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
2181 void
2182 Inst_VOPC__V_CMPX_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
2183 {
2184 Wavefront *wf = gpuDynInst->wavefront();
2185 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2186 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2187 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2188
2189 src0.readSrc();
2190 src1.read();
2191
2192 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2193 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2194
2195 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2196 if (wf->execMask(lane)) {
2197 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
2198 }
2199 }
2200
2201 vcc.write();
2202 wf->execMask() = vcc.rawData();
2203 } // execute
2204 // --- Inst_VOPC__V_CMPX_NLG_F32 class methods ---
2205
2206 Inst_VOPC__V_CMPX_NLG_F32::Inst_VOPC__V_CMPX_NLG_F32(InFmt_VOPC *iFmt)
2207 : Inst_VOPC(iFmt, "v_cmpx_nlg_f32")
2208 {
2209 setFlag(ALU);
2210 setFlag(F32);
2211 setFlag(WritesEXEC);
2212 } // Inst_VOPC__V_CMPX_NLG_F32
2213
2214 Inst_VOPC__V_CMPX_NLG_F32::~Inst_VOPC__V_CMPX_NLG_F32()
2215 {
2216 } // ~Inst_VOPC__V_CMPX_NLG_F32
2217
2218 // --- description from .arch file ---
2219 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
2220 void
2221 Inst_VOPC__V_CMPX_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
2222 {
2223 Wavefront *wf = gpuDynInst->wavefront();
2224 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2225 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2226 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2227
2228 src0.readSrc();
2229 src1.read();
2230
2231 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2232 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2233
2234 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2235 if (wf->execMask(lane)) {
2236 vcc.setBit(lane, !(src0[lane] < src1[lane]
2237 || src0[lane] > src1[lane]) ? 1 : 0);
2238 }
2239 }
2240
2241 vcc.write();
2242 wf->execMask() = vcc.rawData();
2243 } // execute
2244 // --- Inst_VOPC__V_CMPX_NGT_F32 class methods ---
2245
2246 Inst_VOPC__V_CMPX_NGT_F32::Inst_VOPC__V_CMPX_NGT_F32(InFmt_VOPC *iFmt)
2247 : Inst_VOPC(iFmt, "v_cmpx_ngt_f32")
2248 {
2249 setFlag(ALU);
2250 setFlag(F32);
2251 setFlag(WritesEXEC);
2252 } // Inst_VOPC__V_CMPX_NGT_F32
2253
2254 Inst_VOPC__V_CMPX_NGT_F32::~Inst_VOPC__V_CMPX_NGT_F32()
2255 {
2256 } // ~Inst_VOPC__V_CMPX_NGT_F32
2257
2258 // --- description from .arch file ---
2259 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
2260 void
2261 Inst_VOPC__V_CMPX_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
2262 {
2263 Wavefront *wf = gpuDynInst->wavefront();
2264 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2265 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2266 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2267
2268 src0.readSrc();
2269 src1.read();
2270
2271 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2272 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2273
2274 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2275 if (wf->execMask(lane)) {
2276 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
2277 }
2278 }
2279
2280 vcc.write();
2281 wf->execMask() = vcc.rawData();
2282 } // execute
2283 // --- Inst_VOPC__V_CMPX_NLE_F32 class methods ---
2284
2285 Inst_VOPC__V_CMPX_NLE_F32::Inst_VOPC__V_CMPX_NLE_F32(InFmt_VOPC *iFmt)
2286 : Inst_VOPC(iFmt, "v_cmpx_nle_f32")
2287 {
2288 setFlag(ALU);
2289 setFlag(F32);
2290 setFlag(WritesEXEC);
2291 } // Inst_VOPC__V_CMPX_NLE_F32
2292
2293 Inst_VOPC__V_CMPX_NLE_F32::~Inst_VOPC__V_CMPX_NLE_F32()
2294 {
2295 } // ~Inst_VOPC__V_CMPX_NLE_F32
2296
2297 // --- description from .arch file ---
2298 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
2299 void
2300 Inst_VOPC__V_CMPX_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
2301 {
2302 Wavefront *wf = gpuDynInst->wavefront();
2303 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2304 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2305 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2306
2307 src0.readSrc();
2308 src1.read();
2309
2310 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2311 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2312
2313 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2314 if (wf->execMask(lane)) {
2315 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
2316 }
2317 }
2318
2319 vcc.write();
2320 wf->execMask() = vcc.rawData();
2321 } // execute
2322 // --- Inst_VOPC__V_CMPX_NEQ_F32 class methods ---
2323
2324 Inst_VOPC__V_CMPX_NEQ_F32::Inst_VOPC__V_CMPX_NEQ_F32(InFmt_VOPC *iFmt)
2325 : Inst_VOPC(iFmt, "v_cmpx_neq_f32")
2326 {
2327 setFlag(ALU);
2328 setFlag(F32);
2329 setFlag(WritesEXEC);
2330 } // Inst_VOPC__V_CMPX_NEQ_F32
2331
2332 Inst_VOPC__V_CMPX_NEQ_F32::~Inst_VOPC__V_CMPX_NEQ_F32()
2333 {
2334 } // ~Inst_VOPC__V_CMPX_NEQ_F32
2335
2336 // --- description from .arch file ---
2337 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
2338 void
2339 Inst_VOPC__V_CMPX_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
2340 {
2341 Wavefront *wf = gpuDynInst->wavefront();
2342 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2343 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2344 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2345
2346 src0.readSrc();
2347 src1.read();
2348
2349 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2350 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2351
2352 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2353 if (wf->execMask(lane)) {
2354 vcc.setBit(lane, !(src0[lane] == src1[lane]) ? 1 : 0);
2355 }
2356 }
2357
2358 vcc.write();
2359 wf->execMask() = vcc.rawData();
2360 } // execute
2361 // --- Inst_VOPC__V_CMPX_NLT_F32 class methods ---
2362
2363 Inst_VOPC__V_CMPX_NLT_F32::Inst_VOPC__V_CMPX_NLT_F32(InFmt_VOPC *iFmt)
2364 : Inst_VOPC(iFmt, "v_cmpx_nlt_f32")
2365 {
2366 setFlag(ALU);
2367 setFlag(F32);
2368 setFlag(WritesEXEC);
2369 } // Inst_VOPC__V_CMPX_NLT_F32
2370
2371 Inst_VOPC__V_CMPX_NLT_F32::~Inst_VOPC__V_CMPX_NLT_F32()
2372 {
2373 } // ~Inst_VOPC__V_CMPX_NLT_F32
2374
2375 // --- description from .arch file ---
2376 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
2377 void
2378 Inst_VOPC__V_CMPX_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
2379 {
2380 Wavefront *wf = gpuDynInst->wavefront();
2381 ConstVecOperandF32 src0(gpuDynInst, instData.SRC0);
2382 ConstVecOperandF32 src1(gpuDynInst, instData.VSRC1);
2383 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2384
2385 src0.readSrc();
2386 src1.read();
2387
2388 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2389 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2390
2391 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2392 if (wf->execMask(lane)) {
2393 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
2394 }
2395 }
2396
2397 vcc.write();
2398 wf->execMask() = vcc.rawData();
2399 } // execute
2400 // --- Inst_VOPC__V_CMPX_TRU_F32 class methods ---
2401
2402 Inst_VOPC__V_CMPX_TRU_F32::Inst_VOPC__V_CMPX_TRU_F32(InFmt_VOPC *iFmt)
2403 : Inst_VOPC(iFmt, "v_cmpx_tru_f32")
2404 {
2405 setFlag(ALU);
2406 setFlag(F32);
2407 setFlag(WritesEXEC);
2408 } // Inst_VOPC__V_CMPX_TRU_F32
2409
2410 Inst_VOPC__V_CMPX_TRU_F32::~Inst_VOPC__V_CMPX_TRU_F32()
2411 {
2412 } // ~Inst_VOPC__V_CMPX_TRU_F32
2413
2414 // --- description from .arch file ---
2415 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
2416 void
2417 Inst_VOPC__V_CMPX_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
2418 {
2419 Wavefront *wf = gpuDynInst->wavefront();
2420 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2421
2422 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2423 if (wf->execMask(lane)) {
2424 vcc.setBit(lane, 1);
2425 }
2426 }
2427
2428 vcc.write();
2429 wf->execMask() = vcc.rawData();
2430 } // execute
2431 // --- Inst_VOPC__V_CMP_F_F64 class methods ---
2432
2433 Inst_VOPC__V_CMP_F_F64::Inst_VOPC__V_CMP_F_F64(InFmt_VOPC *iFmt)
2434 : Inst_VOPC(iFmt, "v_cmp_f_f64")
2435 {
2436 setFlag(ALU);
2437 setFlag(F64);
2438 } // Inst_VOPC__V_CMP_F_F64
2439
2440 Inst_VOPC__V_CMP_F_F64::~Inst_VOPC__V_CMP_F_F64()
2441 {
2442 } // ~Inst_VOPC__V_CMP_F_F64
2443
2444 // --- description from .arch file ---
2445 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
2446 void
2447 Inst_VOPC__V_CMP_F_F64::execute(GPUDynInstPtr gpuDynInst)
2448 {
2449 Wavefront *wf = gpuDynInst->wavefront();
2450 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2451
2452 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2453 if (wf->execMask(lane)) {
2454 vcc.setBit(lane, 0);
2455 }
2456 }
2457
2458 vcc.write();
2459 } // execute
2460 // --- Inst_VOPC__V_CMP_LT_F64 class methods ---
2461
2462 Inst_VOPC__V_CMP_LT_F64::Inst_VOPC__V_CMP_LT_F64(InFmt_VOPC *iFmt)
2463 : Inst_VOPC(iFmt, "v_cmp_lt_f64")
2464 {
2465 setFlag(ALU);
2466 setFlag(F64);
2467 } // Inst_VOPC__V_CMP_LT_F64
2468
2469 Inst_VOPC__V_CMP_LT_F64::~Inst_VOPC__V_CMP_LT_F64()
2470 {
2471 } // ~Inst_VOPC__V_CMP_LT_F64
2472
2473 // --- description from .arch file ---
2474 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
2475 void
2476 Inst_VOPC__V_CMP_LT_F64::execute(GPUDynInstPtr gpuDynInst)
2477 {
2478 Wavefront *wf = gpuDynInst->wavefront();
2479 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2480 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2481 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2482
2483 src0.readSrc();
2484 src1.read();
2485
2486 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2487 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2488
2489 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2490 if (wf->execMask(lane)) {
2491 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
2492 }
2493 }
2494
2495 vcc.write();
2496 } // execute
2497 // --- Inst_VOPC__V_CMP_EQ_F64 class methods ---
2498
2499 Inst_VOPC__V_CMP_EQ_F64::Inst_VOPC__V_CMP_EQ_F64(InFmt_VOPC *iFmt)
2500 : Inst_VOPC(iFmt, "v_cmp_eq_f64")
2501 {
2502 setFlag(ALU);
2503 setFlag(F64);
2504 } // Inst_VOPC__V_CMP_EQ_F64
2505
2506 Inst_VOPC__V_CMP_EQ_F64::~Inst_VOPC__V_CMP_EQ_F64()
2507 {
2508 } // ~Inst_VOPC__V_CMP_EQ_F64
2509
2510 // --- description from .arch file ---
2511 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
2512 void
2513 Inst_VOPC__V_CMP_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
2514 {
2515 Wavefront *wf = gpuDynInst->wavefront();
2516 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2517 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2518 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2519
2520 src0.readSrc();
2521 src1.read();
2522
2523 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2524 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2525
2526 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2527 if (wf->execMask(lane)) {
2528 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
2529 }
2530 }
2531
2532 vcc.write();
2533 } // execute
2534 // --- Inst_VOPC__V_CMP_LE_F64 class methods ---
2535
2536 Inst_VOPC__V_CMP_LE_F64::Inst_VOPC__V_CMP_LE_F64(InFmt_VOPC *iFmt)
2537 : Inst_VOPC(iFmt, "v_cmp_le_f64")
2538 {
2539 setFlag(ALU);
2540 setFlag(F64);
2541 } // Inst_VOPC__V_CMP_LE_F64
2542
2543 Inst_VOPC__V_CMP_LE_F64::~Inst_VOPC__V_CMP_LE_F64()
2544 {
2545 } // ~Inst_VOPC__V_CMP_LE_F64
2546
2547 // --- description from .arch file ---
2548 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
2549 void
2550 Inst_VOPC__V_CMP_LE_F64::execute(GPUDynInstPtr gpuDynInst)
2551 {
2552 Wavefront *wf = gpuDynInst->wavefront();
2553 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2554 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2555 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2556
2557 src0.readSrc();
2558 src1.read();
2559
2560 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2561 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2562
2563 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2564 if (wf->execMask(lane)) {
2565 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
2566 }
2567 }
2568
2569 vcc.write();
2570 } // execute
2571 // --- Inst_VOPC__V_CMP_GT_F64 class methods ---
2572
2573 Inst_VOPC__V_CMP_GT_F64::Inst_VOPC__V_CMP_GT_F64(InFmt_VOPC *iFmt)
2574 : Inst_VOPC(iFmt, "v_cmp_gt_f64")
2575 {
2576 setFlag(ALU);
2577 setFlag(F64);
2578 } // Inst_VOPC__V_CMP_GT_F64
2579
2580 Inst_VOPC__V_CMP_GT_F64::~Inst_VOPC__V_CMP_GT_F64()
2581 {
2582 } // ~Inst_VOPC__V_CMP_GT_F64
2583
2584 // --- description from .arch file ---
2585 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
2586 void
2587 Inst_VOPC__V_CMP_GT_F64::execute(GPUDynInstPtr gpuDynInst)
2588 {
2589 Wavefront *wf = gpuDynInst->wavefront();
2590 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2591 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2592 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2593
2594 src0.readSrc();
2595 src1.read();
2596
2597 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2598 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2599
2600 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2601 if (wf->execMask(lane)) {
2602 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
2603 }
2604 }
2605
2606 vcc.write();
2607 } // execute
2608 // --- Inst_VOPC__V_CMP_LG_F64 class methods ---
2609
2610 Inst_VOPC__V_CMP_LG_F64::Inst_VOPC__V_CMP_LG_F64(InFmt_VOPC *iFmt)
2611 : Inst_VOPC(iFmt, "v_cmp_lg_f64")
2612 {
2613 setFlag(ALU);
2614 setFlag(F64);
2615 } // Inst_VOPC__V_CMP_LG_F64
2616
2617 Inst_VOPC__V_CMP_LG_F64::~Inst_VOPC__V_CMP_LG_F64()
2618 {
2619 } // ~Inst_VOPC__V_CMP_LG_F64
2620
2621 // --- description from .arch file ---
2622 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
2623 void
2624 Inst_VOPC__V_CMP_LG_F64::execute(GPUDynInstPtr gpuDynInst)
2625 {
2626 Wavefront *wf = gpuDynInst->wavefront();
2627 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2628 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2629 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2630
2631 src0.readSrc();
2632 src1.read();
2633
2634 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2635 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2636
2637 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2638 if (wf->execMask(lane)) {
2639 vcc.setBit(lane, (src0[lane] < src1[lane]
2640 || src0[lane] > src1[lane]) ? 1 : 0);
2641 }
2642 }
2643
2644 vcc.write();
2645 } // execute
2646 // --- Inst_VOPC__V_CMP_GE_F64 class methods ---
2647
2648 Inst_VOPC__V_CMP_GE_F64::Inst_VOPC__V_CMP_GE_F64(InFmt_VOPC *iFmt)
2649 : Inst_VOPC(iFmt, "v_cmp_ge_f64")
2650 {
2651 setFlag(ALU);
2652 setFlag(F64);
2653 } // Inst_VOPC__V_CMP_GE_F64
2654
2655 Inst_VOPC__V_CMP_GE_F64::~Inst_VOPC__V_CMP_GE_F64()
2656 {
2657 } // ~Inst_VOPC__V_CMP_GE_F64
2658
2659 // --- description from .arch file ---
2660 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
2661 void
2662 Inst_VOPC__V_CMP_GE_F64::execute(GPUDynInstPtr gpuDynInst)
2663 {
2664 Wavefront *wf = gpuDynInst->wavefront();
2665 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2666 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2667 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2668
2669 src0.readSrc();
2670 src1.read();
2671
2672 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2673 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2674
2675 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2676 if (wf->execMask(lane)) {
2677 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
2678 }
2679 }
2680
2681 vcc.write();
2682 } // execute
2683 // --- Inst_VOPC__V_CMP_O_F64 class methods ---
2684
2685 Inst_VOPC__V_CMP_O_F64::Inst_VOPC__V_CMP_O_F64(InFmt_VOPC *iFmt)
2686 : Inst_VOPC(iFmt, "v_cmp_o_f64")
2687 {
2688 setFlag(ALU);
2689 setFlag(F64);
2690 } // Inst_VOPC__V_CMP_O_F64
2691
2692 Inst_VOPC__V_CMP_O_F64::~Inst_VOPC__V_CMP_O_F64()
2693 {
2694 } // ~Inst_VOPC__V_CMP_O_F64
2695
2696 // --- description from .arch file ---
2697 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
2698 void
2699 Inst_VOPC__V_CMP_O_F64::execute(GPUDynInstPtr gpuDynInst)
2700 {
2701 Wavefront *wf = gpuDynInst->wavefront();
2702 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2703 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2704 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2705
2706 src0.readSrc();
2707 src1.read();
2708
2709 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2710 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2711
2712 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2713 if (wf->execMask(lane)) {
2714 vcc.setBit(lane, (!std::isnan(src0[lane])
2715 && !std::isnan(src1[lane])) ? 1 : 0);
2716 }
2717 }
2718
2719 vcc.write();
2720 } // execute
2721 // --- Inst_VOPC__V_CMP_U_F64 class methods ---
2722
2723 Inst_VOPC__V_CMP_U_F64::Inst_VOPC__V_CMP_U_F64(InFmt_VOPC *iFmt)
2724 : Inst_VOPC(iFmt, "v_cmp_u_f64")
2725 {
2726 setFlag(ALU);
2727 setFlag(F64);
2728 } // Inst_VOPC__V_CMP_U_F64
2729
2730 Inst_VOPC__V_CMP_U_F64::~Inst_VOPC__V_CMP_U_F64()
2731 {
2732 } // ~Inst_VOPC__V_CMP_U_F64
2733
2734 // --- description from .arch file ---
2735 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
2736 void
2737 Inst_VOPC__V_CMP_U_F64::execute(GPUDynInstPtr gpuDynInst)
2738 {
2739 Wavefront *wf = gpuDynInst->wavefront();
2740 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2741 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2742 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2743
2744 src0.readSrc();
2745 src1.read();
2746
2747 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2748 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2749
2750 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2751 if (wf->execMask(lane)) {
2752 vcc.setBit(lane, (std::isnan(src0[lane])
2753 || std::isnan(src1[lane])) ? 1 : 0);
2754 }
2755 }
2756
2757 vcc.write();
2758 } // execute
2759 // --- Inst_VOPC__V_CMP_NGE_F64 class methods ---
2760
2761 Inst_VOPC__V_CMP_NGE_F64::Inst_VOPC__V_CMP_NGE_F64(InFmt_VOPC *iFmt)
2762 : Inst_VOPC(iFmt, "v_cmp_nge_f64")
2763 {
2764 setFlag(ALU);
2765 setFlag(F64);
2766 } // Inst_VOPC__V_CMP_NGE_F64
2767
2768 Inst_VOPC__V_CMP_NGE_F64::~Inst_VOPC__V_CMP_NGE_F64()
2769 {
2770 } // ~Inst_VOPC__V_CMP_NGE_F64
2771
2772 // --- description from .arch file ---
2773 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
2774 void
2775 Inst_VOPC__V_CMP_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
2776 {
2777 Wavefront *wf = gpuDynInst->wavefront();
2778 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2779 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2780 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2781
2782 src0.readSrc();
2783 src1.read();
2784
2785 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2786 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2787
2788 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2789 if (wf->execMask(lane)) {
2790 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
2791 }
2792 }
2793
2794 vcc.write();
2795 } // execute
2796 // --- Inst_VOPC__V_CMP_NLG_F64 class methods ---
2797
2798 Inst_VOPC__V_CMP_NLG_F64::Inst_VOPC__V_CMP_NLG_F64(InFmt_VOPC *iFmt)
2799 : Inst_VOPC(iFmt, "v_cmp_nlg_f64")
2800 {
2801 setFlag(ALU);
2802 setFlag(F64);
2803 } // Inst_VOPC__V_CMP_NLG_F64
2804
2805 Inst_VOPC__V_CMP_NLG_F64::~Inst_VOPC__V_CMP_NLG_F64()
2806 {
2807 } // ~Inst_VOPC__V_CMP_NLG_F64
2808
2809 // --- description from .arch file ---
2810 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
2811 void
2812 Inst_VOPC__V_CMP_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
2813 {
2814 Wavefront *wf = gpuDynInst->wavefront();
2815 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2816 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2817 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2818
2819 src0.readSrc();
2820 src1.read();
2821
2822 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2823 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2824
2825 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2826 if (wf->execMask(lane)) {
2827 vcc.setBit(lane, !(src0[lane] < src1[lane]
2828 || src0[lane] > src1[lane]) ? 1 : 0);
2829 }
2830 }
2831
2832 vcc.write();
2833 } // execute
2834 // --- Inst_VOPC__V_CMP_NGT_F64 class methods ---
2835
2836 Inst_VOPC__V_CMP_NGT_F64::Inst_VOPC__V_CMP_NGT_F64(InFmt_VOPC *iFmt)
2837 : Inst_VOPC(iFmt, "v_cmp_ngt_f64")
2838 {
2839 setFlag(ALU);
2840 setFlag(F64);
2841 } // Inst_VOPC__V_CMP_NGT_F64
2842
2843 Inst_VOPC__V_CMP_NGT_F64::~Inst_VOPC__V_CMP_NGT_F64()
2844 {
2845 } // ~Inst_VOPC__V_CMP_NGT_F64
2846
2847 // --- description from .arch file ---
2848 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
2849 void
2850 Inst_VOPC__V_CMP_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
2851 {
2852 Wavefront *wf = gpuDynInst->wavefront();
2853 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2854 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2855 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2856
2857 src0.readSrc();
2858 src1.read();
2859
2860 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2861 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2862
2863 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2864 if (wf->execMask(lane)) {
2865 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
2866 }
2867 }
2868
2869 vcc.write();
2870 } // execute
2871 // --- Inst_VOPC__V_CMP_NLE_F64 class methods ---
2872
2873 Inst_VOPC__V_CMP_NLE_F64::Inst_VOPC__V_CMP_NLE_F64(InFmt_VOPC *iFmt)
2874 : Inst_VOPC(iFmt, "v_cmp_nle_f64")
2875 {
2876 setFlag(ALU);
2877 setFlag(F64);
2878 } // Inst_VOPC__V_CMP_NLE_F64
2879
2880 Inst_VOPC__V_CMP_NLE_F64::~Inst_VOPC__V_CMP_NLE_F64()
2881 {
2882 } // ~Inst_VOPC__V_CMP_NLE_F64
2883
2884 // --- description from .arch file ---
2885 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
2886 void
2887 Inst_VOPC__V_CMP_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
2888 {
2889 Wavefront *wf = gpuDynInst->wavefront();
2890 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2891 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2892 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2893
2894 src0.readSrc();
2895 src1.read();
2896
2897 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2898 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2899
2900 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2901 if (wf->execMask(lane)) {
2902 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
2903 }
2904 }
2905
2906 vcc.write();
2907 } // execute
2908 // --- Inst_VOPC__V_CMP_NEQ_F64 class methods ---
2909
2910 Inst_VOPC__V_CMP_NEQ_F64::Inst_VOPC__V_CMP_NEQ_F64(InFmt_VOPC *iFmt)
2911 : Inst_VOPC(iFmt, "v_cmp_neq_f64")
2912 {
2913 setFlag(ALU);
2914 setFlag(F64);
2915 } // Inst_VOPC__V_CMP_NEQ_F64
2916
2917 Inst_VOPC__V_CMP_NEQ_F64::~Inst_VOPC__V_CMP_NEQ_F64()
2918 {
2919 } // ~Inst_VOPC__V_CMP_NEQ_F64
2920
2921 // --- description from .arch file ---
2922 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
2923 void
2924 Inst_VOPC__V_CMP_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
2925 {
2926 Wavefront *wf = gpuDynInst->wavefront();
2927 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2928 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2929 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2930
2931 src0.readSrc();
2932 src1.read();
2933
2934 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2935 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2936
2937 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2938 if (wf->execMask(lane)) {
2939 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
2940 }
2941 }
2942
2943 vcc.write();
2944 } // execute
2945 // --- Inst_VOPC__V_CMP_NLT_F64 class methods ---
2946
2947 Inst_VOPC__V_CMP_NLT_F64::Inst_VOPC__V_CMP_NLT_F64(InFmt_VOPC *iFmt)
2948 : Inst_VOPC(iFmt, "v_cmp_nlt_f64")
2949 {
2950 setFlag(ALU);
2951 setFlag(F64);
2952 } // Inst_VOPC__V_CMP_NLT_F64
2953
2954 Inst_VOPC__V_CMP_NLT_F64::~Inst_VOPC__V_CMP_NLT_F64()
2955 {
2956 } // ~Inst_VOPC__V_CMP_NLT_F64
2957
2958 // --- description from .arch file ---
2959 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
2960 void
2961 Inst_VOPC__V_CMP_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
2962 {
2963 Wavefront *wf = gpuDynInst->wavefront();
2964 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
2965 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
2966 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
2967
2968 src0.readSrc();
2969 src1.read();
2970
2971 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
2972 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
2973
2974 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2975 if (wf->execMask(lane)) {
2976 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
2977 }
2978 }
2979
2980 vcc.write();
2981 } // execute
2982 // --- Inst_VOPC__V_CMP_TRU_F64 class methods ---
2983
2984 Inst_VOPC__V_CMP_TRU_F64::Inst_VOPC__V_CMP_TRU_F64(InFmt_VOPC *iFmt)
2985 : Inst_VOPC(iFmt, "v_cmp_tru_f64")
2986 {
2987 setFlag(ALU);
2988 setFlag(F64);
2989 } // Inst_VOPC__V_CMP_TRU_F64
2990
2991 Inst_VOPC__V_CMP_TRU_F64::~Inst_VOPC__V_CMP_TRU_F64()
2992 {
2993 } // ~Inst_VOPC__V_CMP_TRU_F64
2994
2995 // --- description from .arch file ---
2996 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
2997 void
2998 Inst_VOPC__V_CMP_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
2999 {
3000 Wavefront *wf = gpuDynInst->wavefront();
3001 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3002
3003 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3004 if (wf->execMask(lane)) {
3005 vcc.setBit(lane, 1);
3006 }
3007 }
3008
3009 vcc.write();
3010 } // execute
3011 // --- Inst_VOPC__V_CMPX_F_F64 class methods ---
3012
3013 Inst_VOPC__V_CMPX_F_F64::Inst_VOPC__V_CMPX_F_F64(InFmt_VOPC *iFmt)
3014 : Inst_VOPC(iFmt, "v_cmpx_f_f64")
3015 {
3016 setFlag(ALU);
3017 setFlag(F64);
3018 setFlag(WritesEXEC);
3019 } // Inst_VOPC__V_CMPX_F_F64
3020
3021 Inst_VOPC__V_CMPX_F_F64::~Inst_VOPC__V_CMPX_F_F64()
3022 {
3023 } // ~Inst_VOPC__V_CMPX_F_F64
3024
3025 // --- description from .arch file ---
3026 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
3027 void
3028 Inst_VOPC__V_CMPX_F_F64::execute(GPUDynInstPtr gpuDynInst)
3029 {
3030 Wavefront *wf = gpuDynInst->wavefront();
3031 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3032
3033 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3034 if (wf->execMask(lane)) {
3035 vcc.setBit(lane, 0);
3036 }
3037 }
3038
3039 vcc.write();
3040 wf->execMask() = vcc.rawData();
3041 } // execute
3042 // --- Inst_VOPC__V_CMPX_LT_F64 class methods ---
3043
3044 Inst_VOPC__V_CMPX_LT_F64::Inst_VOPC__V_CMPX_LT_F64(InFmt_VOPC *iFmt)
3045 : Inst_VOPC(iFmt, "v_cmpx_lt_f64")
3046 {
3047 setFlag(ALU);
3048 setFlag(F64);
3049 setFlag(WritesEXEC);
3050 } // Inst_VOPC__V_CMPX_LT_F64
3051
3052 Inst_VOPC__V_CMPX_LT_F64::~Inst_VOPC__V_CMPX_LT_F64()
3053 {
3054 } // ~Inst_VOPC__V_CMPX_LT_F64
3055
3056 // --- description from .arch file ---
3057 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3058 void
3059 Inst_VOPC__V_CMPX_LT_F64::execute(GPUDynInstPtr gpuDynInst)
3060 {
3061 Wavefront *wf = gpuDynInst->wavefront();
3062 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3063 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3064 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3065
3066 src0.readSrc();
3067 src1.read();
3068
3069 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3070 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3071
3072 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3073 if (wf->execMask(lane)) {
3074 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
3075 }
3076 }
3077
3078 vcc.write();
3079 wf->execMask() = vcc.rawData();
3080 } // execute
3081 // --- Inst_VOPC__V_CMPX_EQ_F64 class methods ---
3082
3083 Inst_VOPC__V_CMPX_EQ_F64::Inst_VOPC__V_CMPX_EQ_F64(InFmt_VOPC *iFmt)
3084 : Inst_VOPC(iFmt, "v_cmpx_eq_f64")
3085 {
3086 setFlag(ALU);
3087 setFlag(F64);
3088 setFlag(WritesEXEC);
3089 } // Inst_VOPC__V_CMPX_EQ_F64
3090
3091 Inst_VOPC__V_CMPX_EQ_F64::~Inst_VOPC__V_CMPX_EQ_F64()
3092 {
3093 } // ~Inst_VOPC__V_CMPX_EQ_F64
3094
3095 // --- description from .arch file ---
3096 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
3097 void
3098 Inst_VOPC__V_CMPX_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
3099 {
3100 Wavefront *wf = gpuDynInst->wavefront();
3101 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3102 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3103 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3104
3105 src0.readSrc();
3106 src1.read();
3107
3108 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3109 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3110
3111 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3112 if (wf->execMask(lane)) {
3113 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
3114 }
3115 }
3116
3117 vcc.write();
3118 wf->execMask() = vcc.rawData();
3119 } // execute
3120 // --- Inst_VOPC__V_CMPX_LE_F64 class methods ---
3121
3122 Inst_VOPC__V_CMPX_LE_F64::Inst_VOPC__V_CMPX_LE_F64(InFmt_VOPC *iFmt)
3123 : Inst_VOPC(iFmt, "v_cmpx_le_f64")
3124 {
3125 setFlag(ALU);
3126 setFlag(F64);
3127 setFlag(WritesEXEC);
3128 } // Inst_VOPC__V_CMPX_LE_F64
3129
3130 Inst_VOPC__V_CMPX_LE_F64::~Inst_VOPC__V_CMPX_LE_F64()
3131 {
3132 } // ~Inst_VOPC__V_CMPX_LE_F64
3133
3134 // --- description from .arch file ---
3135 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
3136 void
3137 Inst_VOPC__V_CMPX_LE_F64::execute(GPUDynInstPtr gpuDynInst)
3138 {
3139 Wavefront *wf = gpuDynInst->wavefront();
3140 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3141 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3142 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3143
3144 src0.readSrc();
3145 src1.read();
3146
3147 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3148 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3149
3150 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3151 if (wf->execMask(lane)) {
3152 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
3153 }
3154 }
3155
3156 wf->execMask() = vcc.rawData();
3157 vcc.write();
3158 } // execute
3159 // --- Inst_VOPC__V_CMPX_GT_F64 class methods ---
3160
3161 Inst_VOPC__V_CMPX_GT_F64::Inst_VOPC__V_CMPX_GT_F64(InFmt_VOPC *iFmt)
3162 : Inst_VOPC(iFmt, "v_cmpx_gt_f64")
3163 {
3164 setFlag(ALU);
3165 setFlag(F64);
3166 setFlag(WritesEXEC);
3167 } // Inst_VOPC__V_CMPX_GT_F64
3168
3169 Inst_VOPC__V_CMPX_GT_F64::~Inst_VOPC__V_CMPX_GT_F64()
3170 {
3171 } // ~Inst_VOPC__V_CMPX_GT_F64
3172
3173 // --- description from .arch file ---
3174 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
3175 void
3176 Inst_VOPC__V_CMPX_GT_F64::execute(GPUDynInstPtr gpuDynInst)
3177 {
3178 Wavefront *wf = gpuDynInst->wavefront();
3179 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3180 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3181 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3182
3183 src0.readSrc();
3184 src1.read();
3185
3186 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3187 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3188
3189 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3190 if (wf->execMask(lane)) {
3191 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
3192 }
3193 }
3194
3195 wf->execMask() = vcc.rawData();
3196 vcc.write();
3197 } // execute
3198 // --- Inst_VOPC__V_CMPX_LG_F64 class methods ---
3199
3200 Inst_VOPC__V_CMPX_LG_F64::Inst_VOPC__V_CMPX_LG_F64(InFmt_VOPC *iFmt)
3201 : Inst_VOPC(iFmt, "v_cmpx_lg_f64")
3202 {
3203 setFlag(ALU);
3204 setFlag(F64);
3205 setFlag(WritesEXEC);
3206 } // Inst_VOPC__V_CMPX_LG_F64
3207
3208 Inst_VOPC__V_CMPX_LG_F64::~Inst_VOPC__V_CMPX_LG_F64()
3209 {
3210 } // ~Inst_VOPC__V_CMPX_LG_F64
3211
3212 // --- description from .arch file ---
3213 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3214 void
3215 Inst_VOPC__V_CMPX_LG_F64::execute(GPUDynInstPtr gpuDynInst)
3216 {
3217 Wavefront *wf = gpuDynInst->wavefront();
3218 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3219 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3220 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3221
3222 src0.readSrc();
3223 src1.read();
3224
3225 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3226 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3227
3228 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3229 if (wf->execMask(lane)) {
3230 vcc.setBit(lane, (src0[lane] < src1[lane]
3231 || src0[lane] > src1[lane]) ? 1 : 0);
3232 }
3233 }
3234
3235 wf->execMask() = vcc.rawData();
3236 vcc.write();
3237 } // execute
3238 // --- Inst_VOPC__V_CMPX_GE_F64 class methods ---
3239
3240 Inst_VOPC__V_CMPX_GE_F64::Inst_VOPC__V_CMPX_GE_F64(InFmt_VOPC *iFmt)
3241 : Inst_VOPC(iFmt, "v_cmpx_ge_f64")
3242 {
3243 setFlag(ALU);
3244 setFlag(F64);
3245 setFlag(WritesEXEC);
3246 } // Inst_VOPC__V_CMPX_GE_F64
3247
3248 Inst_VOPC__V_CMPX_GE_F64::~Inst_VOPC__V_CMPX_GE_F64()
3249 {
3250 } // ~Inst_VOPC__V_CMPX_GE_F64
3251
3252 // --- description from .arch file ---
3253 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3254 void
3255 Inst_VOPC__V_CMPX_GE_F64::execute(GPUDynInstPtr gpuDynInst)
3256 {
3257 Wavefront *wf = gpuDynInst->wavefront();
3258 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3259 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3260 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3261
3262 src0.readSrc();
3263 src1.read();
3264
3265 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3266 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3267
3268 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3269 if (wf->execMask(lane)) {
3270 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3271 }
3272 }
3273
3274 wf->execMask() = vcc.rawData();
3275 vcc.write();
3276 } // execute
3277 // --- Inst_VOPC__V_CMPX_O_F64 class methods ---
3278
3279 Inst_VOPC__V_CMPX_O_F64::Inst_VOPC__V_CMPX_O_F64(InFmt_VOPC *iFmt)
3280 : Inst_VOPC(iFmt, "v_cmpx_o_f64")
3281 {
3282 setFlag(ALU);
3283 setFlag(F64);
3284 setFlag(WritesEXEC);
3285 } // Inst_VOPC__V_CMPX_O_F64
3286
3287 Inst_VOPC__V_CMPX_O_F64::~Inst_VOPC__V_CMPX_O_F64()
3288 {
3289 } // ~Inst_VOPC__V_CMPX_O_F64
3290
3291 // --- description from .arch file ---
3292 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
3293 // encoding.
3294 void
3295 Inst_VOPC__V_CMPX_O_F64::execute(GPUDynInstPtr gpuDynInst)
3296 {
3297 Wavefront *wf = gpuDynInst->wavefront();
3298 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3299 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3300 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3301
3302 src0.readSrc();
3303 src1.read();
3304
3305 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3306 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3307
3308 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3309 if (wf->execMask(lane)) {
3310 vcc.setBit(lane, (!std::isnan(src0[lane])
3311 && !std::isnan(src1[lane])) ? 1 : 0);
3312 }
3313 }
3314
3315 wf->execMask() = vcc.rawData();
3316 vcc.write();
3317 } // execute
3318 // --- Inst_VOPC__V_CMPX_U_F64 class methods ---
3319
3320 Inst_VOPC__V_CMPX_U_F64::Inst_VOPC__V_CMPX_U_F64(InFmt_VOPC *iFmt)
3321 : Inst_VOPC(iFmt, "v_cmpx_u_f64")
3322 {
3323 setFlag(ALU);
3324 setFlag(F64);
3325 setFlag(WritesEXEC);
3326 } // Inst_VOPC__V_CMPX_U_F64
3327
3328 Inst_VOPC__V_CMPX_U_F64::~Inst_VOPC__V_CMPX_U_F64()
3329 {
3330 } // ~Inst_VOPC__V_CMPX_U_F64
3331
3332 // --- description from .arch file ---
3333 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
3334 // encoding.
3335 void
3336 Inst_VOPC__V_CMPX_U_F64::execute(GPUDynInstPtr gpuDynInst)
3337 {
3338 Wavefront *wf = gpuDynInst->wavefront();
3339 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3340 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3341 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3342
3343 src0.readSrc();
3344 src1.read();
3345
3346 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3347 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3348
3349 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3350 if (wf->execMask(lane)) {
3351 vcc.setBit(lane, (std::isnan(src0[lane])
3352 || std::isnan(src1[lane])) ? 1 : 0);
3353 }
3354 }
3355
3356 wf->execMask() = vcc.rawData();
3357 vcc.write();
3358 } // execute
3359 // --- Inst_VOPC__V_CMPX_NGE_F64 class methods ---
3360
3361 Inst_VOPC__V_CMPX_NGE_F64::Inst_VOPC__V_CMPX_NGE_F64(InFmt_VOPC *iFmt)
3362 : Inst_VOPC(iFmt, "v_cmpx_nge_f64")
3363 {
3364 setFlag(ALU);
3365 setFlag(F64);
3366 setFlag(WritesEXEC);
3367 } // Inst_VOPC__V_CMPX_NGE_F64
3368
3369 Inst_VOPC__V_CMPX_NGE_F64::~Inst_VOPC__V_CMPX_NGE_F64()
3370 {
3371 } // ~Inst_VOPC__V_CMPX_NGE_F64
3372
3373 // --- description from .arch file ---
3374 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
3375 void
3376 Inst_VOPC__V_CMPX_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
3377 {
3378 Wavefront *wf = gpuDynInst->wavefront();
3379 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3380 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3381 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3382
3383 src0.readSrc();
3384 src1.read();
3385
3386 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3387 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3388
3389 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3390 if (wf->execMask(lane)) {
3391 vcc.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
3392 }
3393 }
3394
3395 wf->execMask() = vcc.rawData();
3396 vcc.write();
3397 } // execute
3398 // --- Inst_VOPC__V_CMPX_NLG_F64 class methods ---
3399
3400 Inst_VOPC__V_CMPX_NLG_F64::Inst_VOPC__V_CMPX_NLG_F64(InFmt_VOPC *iFmt)
3401 : Inst_VOPC(iFmt, "v_cmpx_nlg_f64")
3402 {
3403 setFlag(ALU);
3404 setFlag(F64);
3405 setFlag(WritesEXEC);
3406 } // Inst_VOPC__V_CMPX_NLG_F64
3407
3408 Inst_VOPC__V_CMPX_NLG_F64::~Inst_VOPC__V_CMPX_NLG_F64()
3409 {
3410 } // ~Inst_VOPC__V_CMPX_NLG_F64
3411
3412 // --- description from .arch file ---
3413 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
3414 void
3415 Inst_VOPC__V_CMPX_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
3416 {
3417 Wavefront *wf = gpuDynInst->wavefront();
3418 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3419 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3420 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3421
3422 src0.readSrc();
3423 src1.read();
3424
3425 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3426 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3427
3428 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3429 if (wf->execMask(lane)) {
3430 vcc.setBit(lane, !(src0[lane] < src1[lane]
3431 || src0[lane] > src1[lane]) ? 1 : 0);
3432 }
3433 }
3434
3435 wf->execMask() = vcc.rawData();
3436 vcc.write();
3437 } // execute
3438 // --- Inst_VOPC__V_CMPX_NGT_F64 class methods ---
3439
3440 Inst_VOPC__V_CMPX_NGT_F64::Inst_VOPC__V_CMPX_NGT_F64(InFmt_VOPC *iFmt)
3441 : Inst_VOPC(iFmt, "v_cmpx_ngt_f64")
3442 {
3443 setFlag(ALU);
3444 setFlag(F64);
3445 setFlag(WritesEXEC);
3446 } // Inst_VOPC__V_CMPX_NGT_F64
3447
3448 Inst_VOPC__V_CMPX_NGT_F64::~Inst_VOPC__V_CMPX_NGT_F64()
3449 {
3450 } // ~Inst_VOPC__V_CMPX_NGT_F64
3451
3452 // --- description from .arch file ---
3453 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
3454 void
3455 Inst_VOPC__V_CMPX_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
3456 {
3457 Wavefront *wf = gpuDynInst->wavefront();
3458 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3459 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3460 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3461
3462 src0.readSrc();
3463 src1.read();
3464
3465 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3466 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3467
3468 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3469 if (wf->execMask(lane)) {
3470 vcc.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
3471 }
3472 }
3473
3474 wf->execMask() = vcc.rawData();
3475 vcc.write();
3476 } // execute
3477 // --- Inst_VOPC__V_CMPX_NLE_F64 class methods ---
3478
3479 Inst_VOPC__V_CMPX_NLE_F64::Inst_VOPC__V_CMPX_NLE_F64(InFmt_VOPC *iFmt)
3480 : Inst_VOPC(iFmt, "v_cmpx_nle_f64")
3481 {
3482 setFlag(ALU);
3483 setFlag(F64);
3484 setFlag(WritesEXEC);
3485 } // Inst_VOPC__V_CMPX_NLE_F64
3486
3487 Inst_VOPC__V_CMPX_NLE_F64::~Inst_VOPC__V_CMPX_NLE_F64()
3488 {
3489 } // ~Inst_VOPC__V_CMPX_NLE_F64
3490
3491 // --- description from .arch file ---
3492 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
3493 void
3494 Inst_VOPC__V_CMPX_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
3495 {
3496 Wavefront *wf = gpuDynInst->wavefront();
3497 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3498 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3499 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3500
3501 src0.readSrc();
3502 src1.read();
3503
3504 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3505 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3506
3507 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3508 if (wf->execMask(lane)) {
3509 vcc.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
3510 }
3511 }
3512
3513 wf->execMask() = vcc.rawData();
3514 vcc.write();
3515 } // execute
3516 // --- Inst_VOPC__V_CMPX_NEQ_F64 class methods ---
3517
3518 Inst_VOPC__V_CMPX_NEQ_F64::Inst_VOPC__V_CMPX_NEQ_F64(InFmt_VOPC *iFmt)
3519 : Inst_VOPC(iFmt, "v_cmpx_neq_f64")
3520 {
3521 setFlag(ALU);
3522 setFlag(F64);
3523 setFlag(WritesEXEC);
3524 } // Inst_VOPC__V_CMPX_NEQ_F64
3525
3526 Inst_VOPC__V_CMPX_NEQ_F64::~Inst_VOPC__V_CMPX_NEQ_F64()
3527 {
3528 } // ~Inst_VOPC__V_CMPX_NEQ_F64
3529
3530 // --- description from .arch file ---
3531 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
3532 void
3533 Inst_VOPC__V_CMPX_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
3534 {
3535 Wavefront *wf = gpuDynInst->wavefront();
3536 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3537 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3538 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3539
3540 src0.readSrc();
3541 src1.read();
3542
3543 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3544 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3545
3546 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3547 if (wf->execMask(lane)) {
3548 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
3549 }
3550 }
3551
3552 wf->execMask() = vcc.rawData();
3553 vcc.write();
3554 } // execute
3555 // --- Inst_VOPC__V_CMPX_NLT_F64 class methods ---
3556
3557 Inst_VOPC__V_CMPX_NLT_F64::Inst_VOPC__V_CMPX_NLT_F64(InFmt_VOPC *iFmt)
3558 : Inst_VOPC(iFmt, "v_cmpx_nlt_f64")
3559 {
3560 setFlag(ALU);
3561 setFlag(F64);
3562 setFlag(WritesEXEC);
3563 } // Inst_VOPC__V_CMPX_NLT_F64
3564
3565 Inst_VOPC__V_CMPX_NLT_F64::~Inst_VOPC__V_CMPX_NLT_F64()
3566 {
3567 } // ~Inst_VOPC__V_CMPX_NLT_F64
3568
3569 // --- description from .arch file ---
3570 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
3571 void
3572 Inst_VOPC__V_CMPX_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
3573 {
3574 Wavefront *wf = gpuDynInst->wavefront();
3575 ConstVecOperandF64 src0(gpuDynInst, instData.SRC0);
3576 ConstVecOperandF64 src1(gpuDynInst, instData.VSRC1);
3577 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3578
3579 src0.readSrc();
3580 src1.read();
3581
3582 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3583 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3584
3585 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3586 if (wf->execMask(lane)) {
3587 vcc.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
3588 }
3589 }
3590
3591 wf->execMask() = vcc.rawData();
3592 vcc.write();
3593 } // execute
3594 // --- Inst_VOPC__V_CMPX_TRU_F64 class methods ---
3595
3596 Inst_VOPC__V_CMPX_TRU_F64::Inst_VOPC__V_CMPX_TRU_F64(InFmt_VOPC *iFmt)
3597 : Inst_VOPC(iFmt, "v_cmpx_tru_f64")
3598 {
3599 setFlag(ALU);
3600 setFlag(F64);
3601 setFlag(WritesEXEC);
3602 } // Inst_VOPC__V_CMPX_TRU_F64
3603
3604 Inst_VOPC__V_CMPX_TRU_F64::~Inst_VOPC__V_CMPX_TRU_F64()
3605 {
3606 } // ~Inst_VOPC__V_CMPX_TRU_F64
3607
3608 // --- description from .arch file ---
3609 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
3610 void
3611 Inst_VOPC__V_CMPX_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
3612 {
3613 Wavefront *wf = gpuDynInst->wavefront();
3614 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3615
3616 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3617 if (wf->execMask(lane)) {
3618 vcc.setBit(lane, 1);
3619 }
3620 }
3621
3622 wf->execMask() = vcc.rawData();
3623 vcc.write();
3624 } // execute
3625 // --- Inst_VOPC__V_CMP_F_I16 class methods ---
3626
3627 Inst_VOPC__V_CMP_F_I16::Inst_VOPC__V_CMP_F_I16(InFmt_VOPC *iFmt)
3628 : Inst_VOPC(iFmt, "v_cmp_f_i16")
3629 {
3630 setFlag(ALU);
3631 } // Inst_VOPC__V_CMP_F_I16
3632
3633 Inst_VOPC__V_CMP_F_I16::~Inst_VOPC__V_CMP_F_I16()
3634 {
3635 } // ~Inst_VOPC__V_CMP_F_I16
3636
3637 // --- description from .arch file ---
3638 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
3639 void
3640 Inst_VOPC__V_CMP_F_I16::execute(GPUDynInstPtr gpuDynInst)
3641 {
3642 Wavefront *wf = gpuDynInst->wavefront();
3643 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3644
3645 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3646 if (wf->execMask(lane)) {
3647 vcc.setBit(lane, 0);
3648 }
3649 }
3650
3651 vcc.write();
3652 } // execute
3653 // --- Inst_VOPC__V_CMP_LT_I16 class methods ---
3654
3655 Inst_VOPC__V_CMP_LT_I16::Inst_VOPC__V_CMP_LT_I16(InFmt_VOPC *iFmt)
3656 : Inst_VOPC(iFmt, "v_cmp_lt_i16")
3657 {
3658 setFlag(ALU);
3659 } // Inst_VOPC__V_CMP_LT_I16
3660
3661 Inst_VOPC__V_CMP_LT_I16::~Inst_VOPC__V_CMP_LT_I16()
3662 {
3663 } // ~Inst_VOPC__V_CMP_LT_I16
3664
3665 // --- description from .arch file ---
3666 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3667 void
3668 Inst_VOPC__V_CMP_LT_I16::execute(GPUDynInstPtr gpuDynInst)
3669 {
3670 Wavefront *wf = gpuDynInst->wavefront();
3671 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3672 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3673 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3674
3675 src0.readSrc();
3676 src1.read();
3677
3678 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3679 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3680
3681 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3682 if (wf->execMask(lane)) {
3683 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
3684 }
3685 }
3686
3687 vcc.write();
3688 } // execute
3689 // --- Inst_VOPC__V_CMP_EQ_I16 class methods ---
3690
3691 Inst_VOPC__V_CMP_EQ_I16::Inst_VOPC__V_CMP_EQ_I16(InFmt_VOPC *iFmt)
3692 : Inst_VOPC(iFmt, "v_cmp_eq_i16")
3693 {
3694 setFlag(ALU);
3695 } // Inst_VOPC__V_CMP_EQ_I16
3696
3697 Inst_VOPC__V_CMP_EQ_I16::~Inst_VOPC__V_CMP_EQ_I16()
3698 {
3699 } // ~Inst_VOPC__V_CMP_EQ_I16
3700
3701 // --- description from .arch file ---
3702 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
3703 void
3704 Inst_VOPC__V_CMP_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
3705 {
3706 Wavefront *wf = gpuDynInst->wavefront();
3707 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3708 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3709 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3710
3711 src0.readSrc();
3712 src1.read();
3713
3714 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3715 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3716
3717 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3718 if (wf->execMask(lane)) {
3719 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
3720 }
3721 }
3722
3723 vcc.write();
3724 } // execute
3725 // --- Inst_VOPC__V_CMP_LE_I16 class methods ---
3726
3727 Inst_VOPC__V_CMP_LE_I16::Inst_VOPC__V_CMP_LE_I16(InFmt_VOPC *iFmt)
3728 : Inst_VOPC(iFmt, "v_cmp_le_i16")
3729 {
3730 setFlag(ALU);
3731 } // Inst_VOPC__V_CMP_LE_I16
3732
3733 Inst_VOPC__V_CMP_LE_I16::~Inst_VOPC__V_CMP_LE_I16()
3734 {
3735 } // ~Inst_VOPC__V_CMP_LE_I16
3736
3737 // --- description from .arch file ---
3738 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
3739 void
3740 Inst_VOPC__V_CMP_LE_I16::execute(GPUDynInstPtr gpuDynInst)
3741 {
3742 Wavefront *wf = gpuDynInst->wavefront();
3743 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3744 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3745 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3746
3747 src0.readSrc();
3748 src1.read();
3749
3750 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3751 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3752
3753 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3754 if (wf->execMask(lane)) {
3755 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
3756 }
3757 }
3758
3759 vcc.write();
3760 } // execute
3761 // --- Inst_VOPC__V_CMP_GT_I16 class methods ---
3762
3763 Inst_VOPC__V_CMP_GT_I16::Inst_VOPC__V_CMP_GT_I16(InFmt_VOPC *iFmt)
3764 : Inst_VOPC(iFmt, "v_cmp_gt_i16")
3765 {
3766 setFlag(ALU);
3767 } // Inst_VOPC__V_CMP_GT_I16
3768
3769 Inst_VOPC__V_CMP_GT_I16::~Inst_VOPC__V_CMP_GT_I16()
3770 {
3771 } // ~Inst_VOPC__V_CMP_GT_I16
3772
3773 // --- description from .arch file ---
3774 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
3775 void
3776 Inst_VOPC__V_CMP_GT_I16::execute(GPUDynInstPtr gpuDynInst)
3777 {
3778 Wavefront *wf = gpuDynInst->wavefront();
3779 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3780 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3781 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3782
3783 src0.readSrc();
3784 src1.read();
3785
3786 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3787 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3788
3789 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3790 if (wf->execMask(lane)) {
3791 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
3792 }
3793 }
3794
3795 vcc.write();
3796 } // execute
3797 // --- Inst_VOPC__V_CMP_NE_I16 class methods ---
3798
3799 Inst_VOPC__V_CMP_NE_I16::Inst_VOPC__V_CMP_NE_I16(InFmt_VOPC *iFmt)
3800 : Inst_VOPC(iFmt, "v_cmp_ne_i16")
3801 {
3802 setFlag(ALU);
3803 } // Inst_VOPC__V_CMP_NE_I16
3804
3805 Inst_VOPC__V_CMP_NE_I16::~Inst_VOPC__V_CMP_NE_I16()
3806 {
3807 } // ~Inst_VOPC__V_CMP_NE_I16
3808
3809 // --- description from .arch file ---
3810 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3811 void
3812 Inst_VOPC__V_CMP_NE_I16::execute(GPUDynInstPtr gpuDynInst)
3813 {
3814 Wavefront *wf = gpuDynInst->wavefront();
3815 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3816 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3817 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3818
3819 src0.readSrc();
3820 src1.read();
3821
3822 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3823 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3824
3825 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3826 if (wf->execMask(lane)) {
3827 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
3828 }
3829 }
3830
3831 vcc.write();
3832 } // execute
3833 // --- Inst_VOPC__V_CMP_GE_I16 class methods ---
3834
3835 Inst_VOPC__V_CMP_GE_I16::Inst_VOPC__V_CMP_GE_I16(InFmt_VOPC *iFmt)
3836 : Inst_VOPC(iFmt, "v_cmp_ge_i16")
3837 {
3838 setFlag(ALU);
3839 } // Inst_VOPC__V_CMP_GE_I16
3840
3841 Inst_VOPC__V_CMP_GE_I16::~Inst_VOPC__V_CMP_GE_I16()
3842 {
3843 } // ~Inst_VOPC__V_CMP_GE_I16
3844
3845 // --- description from .arch file ---
3846 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3847 void
3848 Inst_VOPC__V_CMP_GE_I16::execute(GPUDynInstPtr gpuDynInst)
3849 {
3850 Wavefront *wf = gpuDynInst->wavefront();
3851 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
3852 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
3853 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3854
3855 src0.readSrc();
3856 src1.read();
3857
3858 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3859 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3860
3861 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3862 if (wf->execMask(lane)) {
3863 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3864 }
3865 }
3866
3867 vcc.write();
3868 } // execute
3869 // --- Inst_VOPC__V_CMP_T_I16 class methods ---
3870
3871 Inst_VOPC__V_CMP_T_I16::Inst_VOPC__V_CMP_T_I16(InFmt_VOPC *iFmt)
3872 : Inst_VOPC(iFmt, "v_cmp_t_i16")
3873 {
3874 setFlag(ALU);
3875 } // Inst_VOPC__V_CMP_T_I16
3876
3877 Inst_VOPC__V_CMP_T_I16::~Inst_VOPC__V_CMP_T_I16()
3878 {
3879 } // ~Inst_VOPC__V_CMP_T_I16
3880
3881 // --- description from .arch file ---
3882 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
3883 void
3884 Inst_VOPC__V_CMP_T_I16::execute(GPUDynInstPtr gpuDynInst)
3885 {
3886 Wavefront *wf = gpuDynInst->wavefront();
3887 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3888
3889 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3890 if (wf->execMask(lane)) {
3891 vcc.setBit(lane, 1);
3892 }
3893 }
3894
3895 vcc.write();
3896 } // execute
3897 // --- Inst_VOPC__V_CMP_F_U16 class methods ---
3898
3899 Inst_VOPC__V_CMP_F_U16::Inst_VOPC__V_CMP_F_U16(InFmt_VOPC *iFmt)
3900 : Inst_VOPC(iFmt, "v_cmp_f_u16")
3901 {
3902 setFlag(ALU);
3903 } // Inst_VOPC__V_CMP_F_U16
3904
3905 Inst_VOPC__V_CMP_F_U16::~Inst_VOPC__V_CMP_F_U16()
3906 {
3907 } // ~Inst_VOPC__V_CMP_F_U16
3908
3909 // --- description from .arch file ---
3910 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
3911 void
3912 Inst_VOPC__V_CMP_F_U16::execute(GPUDynInstPtr gpuDynInst)
3913 {
3914 Wavefront *wf = gpuDynInst->wavefront();
3915 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3916
3917 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3918 if (wf->execMask(lane)) {
3919 vcc.setBit(lane, 0);
3920 }
3921 }
3922
3923 vcc.write();
3924 } // execute
3925 // --- Inst_VOPC__V_CMP_LT_U16 class methods ---
3926
3927 Inst_VOPC__V_CMP_LT_U16::Inst_VOPC__V_CMP_LT_U16(InFmt_VOPC *iFmt)
3928 : Inst_VOPC(iFmt, "v_cmp_lt_u16")
3929 {
3930 setFlag(ALU);
3931 } // Inst_VOPC__V_CMP_LT_U16
3932
3933 Inst_VOPC__V_CMP_LT_U16::~Inst_VOPC__V_CMP_LT_U16()
3934 {
3935 } // ~Inst_VOPC__V_CMP_LT_U16
3936
3937 // --- description from .arch file ---
3938 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3939 void
3940 Inst_VOPC__V_CMP_LT_U16::execute(GPUDynInstPtr gpuDynInst)
3941 {
3942 Wavefront *wf = gpuDynInst->wavefront();
3943 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3944 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3945 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3946
3947 src0.readSrc();
3948 src1.read();
3949
3950 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
3951 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3952
3953 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3954 if (wf->execMask(lane)) {
3955 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
3956 }
3957 }
3958
3959 vcc.write();
3960 } // execute
3961 // --- Inst_VOPC__V_CMP_EQ_U16 class methods ---
3962
3963 Inst_VOPC__V_CMP_EQ_U16::Inst_VOPC__V_CMP_EQ_U16(InFmt_VOPC *iFmt)
3964 : Inst_VOPC(iFmt, "v_cmp_eq_u16")
3965 {
3966 setFlag(ALU);
3967 } // Inst_VOPC__V_CMP_EQ_U16
3968
3969 Inst_VOPC__V_CMP_EQ_U16::~Inst_VOPC__V_CMP_EQ_U16()
3970 {
3971 } // ~Inst_VOPC__V_CMP_EQ_U16
3972
3973 // --- description from .arch file ---
3974 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
3975 void
3976 Inst_VOPC__V_CMP_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
3977 {
3978 Wavefront *wf = gpuDynInst->wavefront();
3979 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
3980 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
3981 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
3982
3983 src0.readSrc();
3984 src1.read();
3985
3986 auto cmpImpl = [](uint16_t a, uint16_t b) { return a == b ? 1 : 0; };
3987
3988 if (isSDWAInst()) {
3989 sdwabHelper<uint16_t>(gpuDynInst, cmpImpl);
3990 } else if (isDPPInst()) {
3991 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
3992 } else {
3993 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3994 if (wf->execMask(lane)) {
3995 vcc.setBit(lane, cmpImpl(src0[lane], src1[lane]));
3996 }
3997 }
3998
3999 vcc.write();
4000 }
4001 } // execute
4002 // --- Inst_VOPC__V_CMP_LE_U16 class methods ---
4003
4004 Inst_VOPC__V_CMP_LE_U16::Inst_VOPC__V_CMP_LE_U16(InFmt_VOPC *iFmt)
4005 : Inst_VOPC(iFmt, "v_cmp_le_u16")
4006 {
4007 setFlag(ALU);
4008 } // Inst_VOPC__V_CMP_LE_U16
4009
4010 Inst_VOPC__V_CMP_LE_U16::~Inst_VOPC__V_CMP_LE_U16()
4011 {
4012 } // ~Inst_VOPC__V_CMP_LE_U16
4013
4014 // --- description from .arch file ---
4015 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4016 void
4017 Inst_VOPC__V_CMP_LE_U16::execute(GPUDynInstPtr gpuDynInst)
4018 {
4019 Wavefront *wf = gpuDynInst->wavefront();
4020 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4021 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4022 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4023
4024 src0.readSrc();
4025 src1.read();
4026
4027 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4028 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4029
4030 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4031 if (wf->execMask(lane)) {
4032 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4033 }
4034 }
4035
4036 vcc.write();
4037 } // execute
4038 // --- Inst_VOPC__V_CMP_GT_U16 class methods ---
4039
4040 Inst_VOPC__V_CMP_GT_U16::Inst_VOPC__V_CMP_GT_U16(InFmt_VOPC *iFmt)
4041 : Inst_VOPC(iFmt, "v_cmp_gt_u16")
4042 {
4043 setFlag(ALU);
4044 } // Inst_VOPC__V_CMP_GT_U16
4045
4046 Inst_VOPC__V_CMP_GT_U16::~Inst_VOPC__V_CMP_GT_U16()
4047 {
4048 } // ~Inst_VOPC__V_CMP_GT_U16
4049
4050 // --- description from .arch file ---
4051 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4052 void
4053 Inst_VOPC__V_CMP_GT_U16::execute(GPUDynInstPtr gpuDynInst)
4054 {
4055 Wavefront *wf = gpuDynInst->wavefront();
4056 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4057 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4058 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4059
4060 src0.readSrc();
4061 src1.read();
4062
4063 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4064 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4065
4066 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4067 if (wf->execMask(lane)) {
4068 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4069 }
4070 }
4071
4072 vcc.write();
4073 } // execute
4074 // --- Inst_VOPC__V_CMP_NE_U16 class methods ---
4075
4076 Inst_VOPC__V_CMP_NE_U16::Inst_VOPC__V_CMP_NE_U16(InFmt_VOPC *iFmt)
4077 : Inst_VOPC(iFmt, "v_cmp_ne_u16")
4078 {
4079 setFlag(ALU);
4080 } // Inst_VOPC__V_CMP_NE_U16
4081
4082 Inst_VOPC__V_CMP_NE_U16::~Inst_VOPC__V_CMP_NE_U16()
4083 {
4084 } // ~Inst_VOPC__V_CMP_NE_U16
4085
4086 // --- description from .arch file ---
4087 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4088 void
4089 Inst_VOPC__V_CMP_NE_U16::execute(GPUDynInstPtr gpuDynInst)
4090 {
4091 Wavefront *wf = gpuDynInst->wavefront();
4092 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4093 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4094 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4095
4096 src0.readSrc();
4097 src1.read();
4098
4099 auto cmpImpl = [](uint16_t a, uint16_t b) { return a != b ? 1 : 0; };
4100
4101 if (isSDWAInst()) {
4102 sdwabHelper<uint16_t>(gpuDynInst, cmpImpl);
4103 } else if (isDPPInst()) {
4104 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4105 } else {
4106 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4107 if (wf->execMask(lane)) {
4108 vcc.setBit(lane, cmpImpl(src0[lane], src1[lane]));
4109 }
4110 }
4111
4112 vcc.write();
4113 }
4114
4115 vcc.write();
4116 } // execute
4117 // --- Inst_VOPC__V_CMP_GE_U16 class methods ---
4118
4119 Inst_VOPC__V_CMP_GE_U16::Inst_VOPC__V_CMP_GE_U16(InFmt_VOPC *iFmt)
4120 : Inst_VOPC(iFmt, "v_cmp_ge_u16")
4121 {
4122 setFlag(ALU);
4123 } // Inst_VOPC__V_CMP_GE_U16
4124
4125 Inst_VOPC__V_CMP_GE_U16::~Inst_VOPC__V_CMP_GE_U16()
4126 {
4127 } // ~Inst_VOPC__V_CMP_GE_U16
4128
4129 // --- description from .arch file ---
4130 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4131 void
4132 Inst_VOPC__V_CMP_GE_U16::execute(GPUDynInstPtr gpuDynInst)
4133 {
4134 Wavefront *wf = gpuDynInst->wavefront();
4135 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4136 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4137 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4138
4139 src0.readSrc();
4140 src1.read();
4141
4142 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4143 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4144
4145 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4146 if (wf->execMask(lane)) {
4147 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4148 }
4149 }
4150
4151 vcc.write();
4152 } // execute
4153 // --- Inst_VOPC__V_CMP_T_U16 class methods ---
4154
4155 Inst_VOPC__V_CMP_T_U16::Inst_VOPC__V_CMP_T_U16(InFmt_VOPC *iFmt)
4156 : Inst_VOPC(iFmt, "v_cmp_t_u16")
4157 {
4158 setFlag(ALU);
4159 } // Inst_VOPC__V_CMP_T_U16
4160
4161 Inst_VOPC__V_CMP_T_U16::~Inst_VOPC__V_CMP_T_U16()
4162 {
4163 } // ~Inst_VOPC__V_CMP_T_U16
4164
4165 // --- description from .arch file ---
4166 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
4167 void
4168 Inst_VOPC__V_CMP_T_U16::execute(GPUDynInstPtr gpuDynInst)
4169 {
4170 Wavefront *wf = gpuDynInst->wavefront();
4171 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4172
4173 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4174 if (wf->execMask(lane)) {
4175 vcc.setBit(lane, 1);
4176 }
4177 }
4178
4179 vcc.write();
4180 } // execute
4181 // --- Inst_VOPC__V_CMPX_F_I16 class methods ---
4182
4183 Inst_VOPC__V_CMPX_F_I16::Inst_VOPC__V_CMPX_F_I16(InFmt_VOPC *iFmt)
4184 : Inst_VOPC(iFmt, "v_cmpx_f_i16")
4185 {
4186 setFlag(ALU);
4187 setFlag(WritesEXEC);
4188 } // Inst_VOPC__V_CMPX_F_I16
4189
4190 Inst_VOPC__V_CMPX_F_I16::~Inst_VOPC__V_CMPX_F_I16()
4191 {
4192 } // ~Inst_VOPC__V_CMPX_F_I16
4193
4194 // --- description from .arch file ---
4195 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
4196 void
4197 Inst_VOPC__V_CMPX_F_I16::execute(GPUDynInstPtr gpuDynInst)
4198 {
4199 Wavefront *wf = gpuDynInst->wavefront();
4200 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4201
4202 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4203 if (wf->execMask(lane)) {
4204 vcc.setBit(lane, 0);
4205 }
4206 }
4207
4208 wf->execMask() = vcc.rawData();
4209 vcc.write();
4210 } // execute
4211 // --- Inst_VOPC__V_CMPX_LT_I16 class methods ---
4212
4213 Inst_VOPC__V_CMPX_LT_I16::Inst_VOPC__V_CMPX_LT_I16(InFmt_VOPC *iFmt)
4214 : Inst_VOPC(iFmt, "v_cmpx_lt_i16")
4215 {
4216 setFlag(ALU);
4217 setFlag(WritesEXEC);
4218 } // Inst_VOPC__V_CMPX_LT_I16
4219
4220 Inst_VOPC__V_CMPX_LT_I16::~Inst_VOPC__V_CMPX_LT_I16()
4221 {
4222 } // ~Inst_VOPC__V_CMPX_LT_I16
4223
4224 // --- description from .arch file ---
4225 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4226 void
4227 Inst_VOPC__V_CMPX_LT_I16::execute(GPUDynInstPtr gpuDynInst)
4228 {
4229 Wavefront *wf = gpuDynInst->wavefront();
4230 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4231 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4232 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4233
4234 src0.readSrc();
4235 src1.read();
4236
4237 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4238 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4239
4240 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4241 if (wf->execMask(lane)) {
4242 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4243 }
4244 }
4245
4246 wf->execMask() = vcc.rawData();
4247 vcc.write();
4248 } // execute
4249 // --- Inst_VOPC__V_CMPX_EQ_I16 class methods ---
4250
4251 Inst_VOPC__V_CMPX_EQ_I16::Inst_VOPC__V_CMPX_EQ_I16(InFmt_VOPC *iFmt)
4252 : Inst_VOPC(iFmt, "v_cmpx_eq_i16")
4253 {
4254 setFlag(ALU);
4255 setFlag(WritesEXEC);
4256 } // Inst_VOPC__V_CMPX_EQ_I16
4257
4258 Inst_VOPC__V_CMPX_EQ_I16::~Inst_VOPC__V_CMPX_EQ_I16()
4259 {
4260 } // ~Inst_VOPC__V_CMPX_EQ_I16
4261
4262 // --- description from .arch file ---
4263 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4264 void
4265 Inst_VOPC__V_CMPX_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
4266 {
4267 Wavefront *wf = gpuDynInst->wavefront();
4268 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4269 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4270 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4271
4272 src0.readSrc();
4273 src1.read();
4274
4275 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4276 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4277
4278 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4279 if (wf->execMask(lane)) {
4280 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4281 }
4282 }
4283
4284 wf->execMask() = vcc.rawData();
4285 vcc.write();
4286 } // execute
4287 // --- Inst_VOPC__V_CMPX_LE_I16 class methods ---
4288
4289 Inst_VOPC__V_CMPX_LE_I16::Inst_VOPC__V_CMPX_LE_I16(InFmt_VOPC *iFmt)
4290 : Inst_VOPC(iFmt, "v_cmpx_le_i16")
4291 {
4292 setFlag(ALU);
4293 setFlag(WritesEXEC);
4294 } // Inst_VOPC__V_CMPX_LE_I16
4295
4296 Inst_VOPC__V_CMPX_LE_I16::~Inst_VOPC__V_CMPX_LE_I16()
4297 {
4298 } // ~Inst_VOPC__V_CMPX_LE_I16
4299
4300 // --- description from .arch file ---
4301 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4302 void
4303 Inst_VOPC__V_CMPX_LE_I16::execute(GPUDynInstPtr gpuDynInst)
4304 {
4305 Wavefront *wf = gpuDynInst->wavefront();
4306 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4307 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4308 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4309
4310 src0.readSrc();
4311 src1.read();
4312
4313 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4314 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4315
4316 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4317 if (wf->execMask(lane)) {
4318 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4319 }
4320 }
4321
4322 wf->execMask() = vcc.rawData();
4323 vcc.write();
4324 } // execute
4325 // --- Inst_VOPC__V_CMPX_GT_I16 class methods ---
4326
4327 Inst_VOPC__V_CMPX_GT_I16::Inst_VOPC__V_CMPX_GT_I16(InFmt_VOPC *iFmt)
4328 : Inst_VOPC(iFmt, "v_cmpx_gt_i16")
4329 {
4330 setFlag(ALU);
4331 setFlag(WritesEXEC);
4332 } // Inst_VOPC__V_CMPX_GT_I16
4333
4334 Inst_VOPC__V_CMPX_GT_I16::~Inst_VOPC__V_CMPX_GT_I16()
4335 {
4336 } // ~Inst_VOPC__V_CMPX_GT_I16
4337
4338 // --- description from .arch file ---
4339 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4340 void
4341 Inst_VOPC__V_CMPX_GT_I16::execute(GPUDynInstPtr gpuDynInst)
4342 {
4343 Wavefront *wf = gpuDynInst->wavefront();
4344 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4345 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4346 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4347
4348 src0.readSrc();
4349 src1.read();
4350
4351 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4352 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4353
4354 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4355 if (wf->execMask(lane)) {
4356 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4357 }
4358 }
4359
4360 wf->execMask() = vcc.rawData();
4361 vcc.write();
4362 } // execute
4363 // --- Inst_VOPC__V_CMPX_NE_I16 class methods ---
4364
4365 Inst_VOPC__V_CMPX_NE_I16::Inst_VOPC__V_CMPX_NE_I16(InFmt_VOPC *iFmt)
4366 : Inst_VOPC(iFmt, "v_cmpx_ne_i16")
4367 {
4368 setFlag(ALU);
4369 setFlag(WritesEXEC);
4370 } // Inst_VOPC__V_CMPX_NE_I16
4371
4372 Inst_VOPC__V_CMPX_NE_I16::~Inst_VOPC__V_CMPX_NE_I16()
4373 {
4374 } // ~Inst_VOPC__V_CMPX_NE_I16
4375
4376 // --- description from .arch file ---
4377 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4378 void
4379 Inst_VOPC__V_CMPX_NE_I16::execute(GPUDynInstPtr gpuDynInst)
4380 {
4381 Wavefront *wf = gpuDynInst->wavefront();
4382 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4383 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4384 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4385
4386 src0.readSrc();
4387 src1.read();
4388
4389 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4390 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4391
4392 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4393 if (wf->execMask(lane)) {
4394 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4395 }
4396 }
4397
4398 wf->execMask() = vcc.rawData();
4399 vcc.write();
4400 } // execute
4401 // --- Inst_VOPC__V_CMPX_GE_I16 class methods ---
4402
4403 Inst_VOPC__V_CMPX_GE_I16::Inst_VOPC__V_CMPX_GE_I16(InFmt_VOPC *iFmt)
4404 : Inst_VOPC(iFmt, "v_cmpx_ge_i16")
4405 {
4406 setFlag(ALU);
4407 setFlag(WritesEXEC);
4408 } // Inst_VOPC__V_CMPX_GE_I16
4409
4410 Inst_VOPC__V_CMPX_GE_I16::~Inst_VOPC__V_CMPX_GE_I16()
4411 {
4412 } // ~Inst_VOPC__V_CMPX_GE_I16
4413
4414 // --- description from .arch file ---
4415 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4416 void
4417 Inst_VOPC__V_CMPX_GE_I16::execute(GPUDynInstPtr gpuDynInst)
4418 {
4419 Wavefront *wf = gpuDynInst->wavefront();
4420 ConstVecOperandI16 src0(gpuDynInst, instData.SRC0);
4421 ConstVecOperandI16 src1(gpuDynInst, instData.VSRC1);
4422 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4423
4424 src0.readSrc();
4425 src1.read();
4426
4427 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4428 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4429
4430 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4431 if (wf->execMask(lane)) {
4432 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4433 }
4434 }
4435
4436 wf->execMask() = vcc.rawData();
4437 vcc.write();
4438 } // execute
4439 // --- Inst_VOPC__V_CMPX_T_I16 class methods ---
4440
4441 Inst_VOPC__V_CMPX_T_I16::Inst_VOPC__V_CMPX_T_I16(InFmt_VOPC *iFmt)
4442 : Inst_VOPC(iFmt, "v_cmpx_t_i16")
4443 {
4444 setFlag(ALU);
4445 setFlag(WritesEXEC);
4446 } // Inst_VOPC__V_CMPX_T_I16
4447
4448 Inst_VOPC__V_CMPX_T_I16::~Inst_VOPC__V_CMPX_T_I16()
4449 {
4450 } // ~Inst_VOPC__V_CMPX_T_I16
4451
4452 // --- description from .arch file ---
4453 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
4454 void
4455 Inst_VOPC__V_CMPX_T_I16::execute(GPUDynInstPtr gpuDynInst)
4456 {
4457 Wavefront *wf = gpuDynInst->wavefront();
4458 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4459
4460 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4461 if (wf->execMask(lane)) {
4462 vcc.setBit(lane, 1);
4463 }
4464 }
4465
4466 wf->execMask() = vcc.rawData();
4467 vcc.write();
4468 } // execute
4469 // --- Inst_VOPC__V_CMPX_F_U16 class methods ---
4470
4471 Inst_VOPC__V_CMPX_F_U16::Inst_VOPC__V_CMPX_F_U16(InFmt_VOPC *iFmt)
4472 : Inst_VOPC(iFmt, "v_cmpx_f_u16")
4473 {
4474 setFlag(ALU);
4475 setFlag(WritesEXEC);
4476 } // Inst_VOPC__V_CMPX_F_U16
4477
4478 Inst_VOPC__V_CMPX_F_U16::~Inst_VOPC__V_CMPX_F_U16()
4479 {
4480 } // ~Inst_VOPC__V_CMPX_F_U16
4481
4482 // --- description from .arch file ---
4483 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
4484 void
4485 Inst_VOPC__V_CMPX_F_U16::execute(GPUDynInstPtr gpuDynInst)
4486 {
4487 Wavefront *wf = gpuDynInst->wavefront();
4488 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4489
4490 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4491 if (wf->execMask(lane)) {
4492 vcc.setBit(lane, 0);
4493 }
4494 }
4495
4496 wf->execMask() = vcc.rawData();
4497 vcc.write();
4498 } // execute
4499 // --- Inst_VOPC__V_CMPX_LT_U16 class methods ---
4500
4501 Inst_VOPC__V_CMPX_LT_U16::Inst_VOPC__V_CMPX_LT_U16(InFmt_VOPC *iFmt)
4502 : Inst_VOPC(iFmt, "v_cmpx_lt_u16")
4503 {
4504 setFlag(ALU);
4505 setFlag(WritesEXEC);
4506 } // Inst_VOPC__V_CMPX_LT_U16
4507
4508 Inst_VOPC__V_CMPX_LT_U16::~Inst_VOPC__V_CMPX_LT_U16()
4509 {
4510 } // ~Inst_VOPC__V_CMPX_LT_U16
4511
4512 // --- description from .arch file ---
4513 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4514 void
4515 Inst_VOPC__V_CMPX_LT_U16::execute(GPUDynInstPtr gpuDynInst)
4516 {
4517 Wavefront *wf = gpuDynInst->wavefront();
4518 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4519 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4520 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4521
4522 src0.readSrc();
4523 src1.read();
4524
4525 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4526 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4527
4528 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4529 if (wf->execMask(lane)) {
4530 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4531 }
4532 }
4533
4534 wf->execMask() = vcc.rawData();
4535 vcc.write();
4536 } // execute
4537 // --- Inst_VOPC__V_CMPX_EQ_U16 class methods ---
4538
4539 Inst_VOPC__V_CMPX_EQ_U16::Inst_VOPC__V_CMPX_EQ_U16(InFmt_VOPC *iFmt)
4540 : Inst_VOPC(iFmt, "v_cmpx_eq_u16")
4541 {
4542 setFlag(ALU);
4543 setFlag(WritesEXEC);
4544 } // Inst_VOPC__V_CMPX_EQ_U16
4545
4546 Inst_VOPC__V_CMPX_EQ_U16::~Inst_VOPC__V_CMPX_EQ_U16()
4547 {
4548 } // ~Inst_VOPC__V_CMPX_EQ_U16
4549
4550 // --- description from .arch file ---
4551 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4552 void
4553 Inst_VOPC__V_CMPX_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
4554 {
4555 Wavefront *wf = gpuDynInst->wavefront();
4556 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4557 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4558 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4559
4560 src0.readSrc();
4561 src1.read();
4562
4563 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4564 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4565
4566 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4567 if (wf->execMask(lane)) {
4568 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4569 }
4570 }
4571
4572 wf->execMask() = vcc.rawData();
4573 vcc.write();
4574 } // execute
4575 // --- Inst_VOPC__V_CMPX_LE_U16 class methods ---
4576
4577 Inst_VOPC__V_CMPX_LE_U16::Inst_VOPC__V_CMPX_LE_U16(InFmt_VOPC *iFmt)
4578 : Inst_VOPC(iFmt, "v_cmpx_le_u16")
4579 {
4580 setFlag(ALU);
4581 setFlag(WritesEXEC);
4582 } // Inst_VOPC__V_CMPX_LE_U16
4583
4584 Inst_VOPC__V_CMPX_LE_U16::~Inst_VOPC__V_CMPX_LE_U16()
4585 {
4586 } // ~Inst_VOPC__V_CMPX_LE_U16
4587
4588 // --- description from .arch file ---
4589 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4590 void
4591 Inst_VOPC__V_CMPX_LE_U16::execute(GPUDynInstPtr gpuDynInst)
4592 {
4593 Wavefront *wf = gpuDynInst->wavefront();
4594 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4595 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4596 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4597
4598 src0.readSrc();
4599 src1.read();
4600
4601 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4602 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4603
4604 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4605 if (wf->execMask(lane)) {
4606 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4607 }
4608 }
4609
4610 wf->execMask() = vcc.rawData();
4611 vcc.write();
4612 } // execute
4613 // --- Inst_VOPC__V_CMPX_GT_U16 class methods ---
4614
4615 Inst_VOPC__V_CMPX_GT_U16::Inst_VOPC__V_CMPX_GT_U16(InFmt_VOPC *iFmt)
4616 : Inst_VOPC(iFmt, "v_cmpx_gt_u16")
4617 {
4618 setFlag(ALU);
4619 setFlag(WritesEXEC);
4620 } // Inst_VOPC__V_CMPX_GT_U16
4621
4622 Inst_VOPC__V_CMPX_GT_U16::~Inst_VOPC__V_CMPX_GT_U16()
4623 {
4624 } // ~Inst_VOPC__V_CMPX_GT_U16
4625
4626 // --- description from .arch file ---
4627 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4628 void
4629 Inst_VOPC__V_CMPX_GT_U16::execute(GPUDynInstPtr gpuDynInst)
4630 {
4631 Wavefront *wf = gpuDynInst->wavefront();
4632 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4633 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4634 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4635
4636 src0.readSrc();
4637 src1.read();
4638
4639 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4640 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4641
4642 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4643 if (wf->execMask(lane)) {
4644 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4645 }
4646 }
4647
4648 wf->execMask() = vcc.rawData();
4649 vcc.write();
4650 } // execute
4651 // --- Inst_VOPC__V_CMPX_NE_U16 class methods ---
4652
4653 Inst_VOPC__V_CMPX_NE_U16::Inst_VOPC__V_CMPX_NE_U16(InFmt_VOPC *iFmt)
4654 : Inst_VOPC(iFmt, "v_cmpx_ne_u16")
4655 {
4656 setFlag(ALU);
4657 setFlag(WritesEXEC);
4658 } // Inst_VOPC__V_CMPX_NE_U16
4659
4660 Inst_VOPC__V_CMPX_NE_U16::~Inst_VOPC__V_CMPX_NE_U16()
4661 {
4662 } // ~Inst_VOPC__V_CMPX_NE_U16
4663
4664 // --- description from .arch file ---
4665 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4666 void
4667 Inst_VOPC__V_CMPX_NE_U16::execute(GPUDynInstPtr gpuDynInst)
4668 {
4669 Wavefront *wf = gpuDynInst->wavefront();
4670 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4671 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4672 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4673
4674 src0.readSrc();
4675 src1.read();
4676
4677 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4678 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4679
4680 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4681 if (wf->execMask(lane)) {
4682 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4683 }
4684 }
4685
4686 wf->execMask() = vcc.rawData();
4687 vcc.write();
4688 } // execute
4689 // --- Inst_VOPC__V_CMPX_GE_U16 class methods ---
4690
4691 Inst_VOPC__V_CMPX_GE_U16::Inst_VOPC__V_CMPX_GE_U16(InFmt_VOPC *iFmt)
4692 : Inst_VOPC(iFmt, "v_cmpx_ge_u16")
4693 {
4694 setFlag(ALU);
4695 setFlag(WritesEXEC);
4696 } // Inst_VOPC__V_CMPX_GE_U16
4697
4698 Inst_VOPC__V_CMPX_GE_U16::~Inst_VOPC__V_CMPX_GE_U16()
4699 {
4700 } // ~Inst_VOPC__V_CMPX_GE_U16
4701
4702 // --- description from .arch file ---
4703 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4704 void
4705 Inst_VOPC__V_CMPX_GE_U16::execute(GPUDynInstPtr gpuDynInst)
4706 {
4707 Wavefront *wf = gpuDynInst->wavefront();
4708 ConstVecOperandU16 src0(gpuDynInst, instData.SRC0);
4709 ConstVecOperandU16 src1(gpuDynInst, instData.VSRC1);
4710 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4711
4712 src0.readSrc();
4713 src1.read();
4714
4715 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4716 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4717
4718 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4719 if (wf->execMask(lane)) {
4720 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4721 }
4722 }
4723
4724 wf->execMask() = vcc.rawData();
4725 vcc.write();
4726 } // execute
4727 // --- Inst_VOPC__V_CMPX_T_U16 class methods ---
4728
4729 Inst_VOPC__V_CMPX_T_U16::Inst_VOPC__V_CMPX_T_U16(InFmt_VOPC *iFmt)
4730 : Inst_VOPC(iFmt, "v_cmpx_t_u16")
4731 {
4732 setFlag(ALU);
4733 setFlag(WritesEXEC);
4734 } // Inst_VOPC__V_CMPX_T_U16
4735
4736 Inst_VOPC__V_CMPX_T_U16::~Inst_VOPC__V_CMPX_T_U16()
4737 {
4738 } // ~Inst_VOPC__V_CMPX_T_U16
4739
4740 // --- description from .arch file ---
4741 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
4742 void
4743 Inst_VOPC__V_CMPX_T_U16::execute(GPUDynInstPtr gpuDynInst)
4744 {
4745 Wavefront *wf = gpuDynInst->wavefront();
4746 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4747
4748 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4749 if (wf->execMask(lane)) {
4750 vcc.setBit(lane, 1);
4751 }
4752 }
4753
4754 wf->execMask() = vcc.rawData();
4755 vcc.write();
4756 } // execute
4757 // --- Inst_VOPC__V_CMP_F_I32 class methods ---
4758
4759 Inst_VOPC__V_CMP_F_I32::Inst_VOPC__V_CMP_F_I32(InFmt_VOPC *iFmt)
4760 : Inst_VOPC(iFmt, "v_cmp_f_i32")
4761 {
4762 setFlag(ALU);
4763 } // Inst_VOPC__V_CMP_F_I32
4764
4765 Inst_VOPC__V_CMP_F_I32::~Inst_VOPC__V_CMP_F_I32()
4766 {
4767 } // ~Inst_VOPC__V_CMP_F_I32
4768
4769 // --- description from .arch file ---
4770 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
4771 void
4772 Inst_VOPC__V_CMP_F_I32::execute(GPUDynInstPtr gpuDynInst)
4773 {
4774 Wavefront *wf = gpuDynInst->wavefront();
4775 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4776
4777 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4778 if (wf->execMask(lane)) {
4779 vcc.setBit(lane, 0);
4780 }
4781 }
4782
4783 vcc.write();
4784 } // execute
4785 // --- Inst_VOPC__V_CMP_LT_I32 class methods ---
4786
4787 Inst_VOPC__V_CMP_LT_I32::Inst_VOPC__V_CMP_LT_I32(InFmt_VOPC *iFmt)
4788 : Inst_VOPC(iFmt, "v_cmp_lt_i32")
4789 {
4790 setFlag(ALU);
4791 } // Inst_VOPC__V_CMP_LT_I32
4792
4793 Inst_VOPC__V_CMP_LT_I32::~Inst_VOPC__V_CMP_LT_I32()
4794 {
4795 } // ~Inst_VOPC__V_CMP_LT_I32
4796
4797 // --- description from .arch file ---
4798 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4799 void
4800 Inst_VOPC__V_CMP_LT_I32::execute(GPUDynInstPtr gpuDynInst)
4801 {
4802 Wavefront *wf = gpuDynInst->wavefront();
4803 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4804 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4805 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4806
4807 src0.readSrc();
4808 src1.read();
4809
4810 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4811 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4812
4813 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4814 if (wf->execMask(lane)) {
4815 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4816 }
4817 }
4818
4819 vcc.write();
4820 } // execute
4821 // --- Inst_VOPC__V_CMP_EQ_I32 class methods ---
4822
4823 Inst_VOPC__V_CMP_EQ_I32::Inst_VOPC__V_CMP_EQ_I32(InFmt_VOPC *iFmt)
4824 : Inst_VOPC(iFmt, "v_cmp_eq_i32")
4825 {
4826 setFlag(ALU);
4827 } // Inst_VOPC__V_CMP_EQ_I32
4828
4829 Inst_VOPC__V_CMP_EQ_I32::~Inst_VOPC__V_CMP_EQ_I32()
4830 {
4831 } // ~Inst_VOPC__V_CMP_EQ_I32
4832
4833 // --- description from .arch file ---
4834 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4835 void
4836 Inst_VOPC__V_CMP_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
4837 {
4838 Wavefront *wf = gpuDynInst->wavefront();
4839 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4840 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4841 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4842
4843 src0.readSrc();
4844 src1.read();
4845
4846 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4847 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4848
4849 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4850 if (wf->execMask(lane)) {
4851 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4852 }
4853 }
4854
4855 vcc.write();
4856 } // execute
4857 // --- Inst_VOPC__V_CMP_LE_I32 class methods ---
4858
4859 Inst_VOPC__V_CMP_LE_I32::Inst_VOPC__V_CMP_LE_I32(InFmt_VOPC *iFmt)
4860 : Inst_VOPC(iFmt, "v_cmp_le_i32")
4861 {
4862 setFlag(ALU);
4863 } // Inst_VOPC__V_CMP_LE_I32
4864
4865 Inst_VOPC__V_CMP_LE_I32::~Inst_VOPC__V_CMP_LE_I32()
4866 {
4867 } // ~Inst_VOPC__V_CMP_LE_I32
4868
4869 // --- description from .arch file ---
4870 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4871 void
4872 Inst_VOPC__V_CMP_LE_I32::execute(GPUDynInstPtr gpuDynInst)
4873 {
4874 Wavefront *wf = gpuDynInst->wavefront();
4875 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4876 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4877 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4878
4879 src0.readSrc();
4880 src1.read();
4881
4882 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4883 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4884
4885 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4886 if (wf->execMask(lane)) {
4887 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4888 }
4889 }
4890
4891 vcc.write();
4892 } // execute
4893 // --- Inst_VOPC__V_CMP_GT_I32 class methods ---
4894
4895 Inst_VOPC__V_CMP_GT_I32::Inst_VOPC__V_CMP_GT_I32(InFmt_VOPC *iFmt)
4896 : Inst_VOPC(iFmt, "v_cmp_gt_i32")
4897 {
4898 setFlag(ALU);
4899 } // Inst_VOPC__V_CMP_GT_I32
4900
4901 Inst_VOPC__V_CMP_GT_I32::~Inst_VOPC__V_CMP_GT_I32()
4902 {
4903 } // ~Inst_VOPC__V_CMP_GT_I32
4904
4905 // --- description from .arch file ---
4906 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4907 void
4908 Inst_VOPC__V_CMP_GT_I32::execute(GPUDynInstPtr gpuDynInst)
4909 {
4910 Wavefront *wf = gpuDynInst->wavefront();
4911 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4912 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4913 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4914
4915 src0.readSrc();
4916 src1.read();
4917
4918 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4919 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4920
4921 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4922 if (wf->execMask(lane)) {
4923 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4924 }
4925 }
4926
4927 vcc.write();
4928 } // execute
4929 // --- Inst_VOPC__V_CMP_NE_I32 class methods ---
4930
4931 Inst_VOPC__V_CMP_NE_I32::Inst_VOPC__V_CMP_NE_I32(InFmt_VOPC *iFmt)
4932 : Inst_VOPC(iFmt, "v_cmp_ne_i32")
4933 {
4934 setFlag(ALU);
4935 } // Inst_VOPC__V_CMP_NE_I32
4936
4937 Inst_VOPC__V_CMP_NE_I32::~Inst_VOPC__V_CMP_NE_I32()
4938 {
4939 } // ~Inst_VOPC__V_CMP_NE_I32
4940
4941 // --- description from .arch file ---
4942 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4943 void
4944 Inst_VOPC__V_CMP_NE_I32::execute(GPUDynInstPtr gpuDynInst)
4945 {
4946 Wavefront *wf = gpuDynInst->wavefront();
4947 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4948 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4949 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4950
4951 src0.readSrc();
4952 src1.read();
4953
4954 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4955 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4956
4957 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4958 if (wf->execMask(lane)) {
4959 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4960 }
4961 }
4962
4963 vcc.write();
4964 } // execute
4965 // --- Inst_VOPC__V_CMP_GE_I32 class methods ---
4966
4967 Inst_VOPC__V_CMP_GE_I32::Inst_VOPC__V_CMP_GE_I32(InFmt_VOPC *iFmt)
4968 : Inst_VOPC(iFmt, "v_cmp_ge_i32")
4969 {
4970 setFlag(ALU);
4971 } // Inst_VOPC__V_CMP_GE_I32
4972
4973 Inst_VOPC__V_CMP_GE_I32::~Inst_VOPC__V_CMP_GE_I32()
4974 {
4975 } // ~Inst_VOPC__V_CMP_GE_I32
4976
4977 // --- description from .arch file ---
4978 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4979 void
4980 Inst_VOPC__V_CMP_GE_I32::execute(GPUDynInstPtr gpuDynInst)
4981 {
4982 Wavefront *wf = gpuDynInst->wavefront();
4983 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
4984 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
4985 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
4986
4987 src0.readSrc();
4988 src1.read();
4989
4990 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
4991 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
4992
4993 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4994 if (wf->execMask(lane)) {
4995 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4996 }
4997 }
4998
4999 vcc.write();
5000 } // execute
5001 // --- Inst_VOPC__V_CMP_T_I32 class methods ---
5002
5003 Inst_VOPC__V_CMP_T_I32::Inst_VOPC__V_CMP_T_I32(InFmt_VOPC *iFmt)
5004 : Inst_VOPC(iFmt, "v_cmp_t_i32")
5005 {
5006 setFlag(ALU);
5007 } // Inst_VOPC__V_CMP_T_I32
5008
5009 Inst_VOPC__V_CMP_T_I32::~Inst_VOPC__V_CMP_T_I32()
5010 {
5011 } // ~Inst_VOPC__V_CMP_T_I32
5012
5013 // --- description from .arch file ---
5014 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
5015 void
5016 Inst_VOPC__V_CMP_T_I32::execute(GPUDynInstPtr gpuDynInst)
5017 {
5018 Wavefront *wf = gpuDynInst->wavefront();
5019 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5020
5021 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5022 if (wf->execMask(lane)) {
5023 vcc.setBit(lane, 1);
5024 }
5025 }
5026
5027 vcc.write();
5028 } // execute
5029 // --- Inst_VOPC__V_CMP_F_U32 class methods ---
5030
5031 Inst_VOPC__V_CMP_F_U32::Inst_VOPC__V_CMP_F_U32(InFmt_VOPC *iFmt)
5032 : Inst_VOPC(iFmt, "v_cmp_f_u32")
5033 {
5034 setFlag(ALU);
5035 } // Inst_VOPC__V_CMP_F_U32
5036
5037 Inst_VOPC__V_CMP_F_U32::~Inst_VOPC__V_CMP_F_U32()
5038 {
5039 } // ~Inst_VOPC__V_CMP_F_U32
5040
5041 // --- description from .arch file ---
5042 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
5043 void
5044 Inst_VOPC__V_CMP_F_U32::execute(GPUDynInstPtr gpuDynInst)
5045 {
5046 Wavefront *wf = gpuDynInst->wavefront();
5047 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5048
5049 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5050 if (wf->execMask(lane)) {
5051 vcc.setBit(lane, 0);
5052 }
5053 }
5054
5055 vcc.write();
5056 } // execute
5057 // --- Inst_VOPC__V_CMP_LT_U32 class methods ---
5058
5059 Inst_VOPC__V_CMP_LT_U32::Inst_VOPC__V_CMP_LT_U32(InFmt_VOPC *iFmt)
5060 : Inst_VOPC(iFmt, "v_cmp_lt_u32")
5061 {
5062 setFlag(ALU);
5063 } // Inst_VOPC__V_CMP_LT_U32
5064
5065 Inst_VOPC__V_CMP_LT_U32::~Inst_VOPC__V_CMP_LT_U32()
5066 {
5067 } // ~Inst_VOPC__V_CMP_LT_U32
5068
5069 // --- description from .arch file ---
5070 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5071 void
5072 Inst_VOPC__V_CMP_LT_U32::execute(GPUDynInstPtr gpuDynInst)
5073 {
5074 Wavefront *wf = gpuDynInst->wavefront();
5075 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5076 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5077 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5078
5079 src0.readSrc();
5080 src1.read();
5081
5082 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5083 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5084
5085 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5086 if (wf->execMask(lane)) {
5087 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5088 }
5089 }
5090
5091 vcc.write();
5092 } // execute
5093 // --- Inst_VOPC__V_CMP_EQ_U32 class methods ---
5094
5095 Inst_VOPC__V_CMP_EQ_U32::Inst_VOPC__V_CMP_EQ_U32(InFmt_VOPC *iFmt)
5096 : Inst_VOPC(iFmt, "v_cmp_eq_u32")
5097 {
5098 setFlag(ALU);
5099 } // Inst_VOPC__V_CMP_EQ_U32
5100
5101 Inst_VOPC__V_CMP_EQ_U32::~Inst_VOPC__V_CMP_EQ_U32()
5102 {
5103 } // ~Inst_VOPC__V_CMP_EQ_U32
5104
5105 // --- description from .arch file ---
5106 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5107 void
5108 Inst_VOPC__V_CMP_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
5109 {
5110 Wavefront *wf = gpuDynInst->wavefront();
5111 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5112 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5113 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5114
5115 src0.readSrc();
5116 src1.read();
5117
5118 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5119 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5120
5121 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5122 if (wf->execMask(lane)) {
5123 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5124 }
5125 }
5126
5127 vcc.write();
5128 } // execute
5129 // --- Inst_VOPC__V_CMP_LE_U32 class methods ---
5130
5131 Inst_VOPC__V_CMP_LE_U32::Inst_VOPC__V_CMP_LE_U32(InFmt_VOPC *iFmt)
5132 : Inst_VOPC(iFmt, "v_cmp_le_u32")
5133 {
5134 setFlag(ALU);
5135 } // Inst_VOPC__V_CMP_LE_U32
5136
5137 Inst_VOPC__V_CMP_LE_U32::~Inst_VOPC__V_CMP_LE_U32()
5138 {
5139 } // ~Inst_VOPC__V_CMP_LE_U32
5140
5141 // --- description from .arch file ---
5142 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5143 void
5144 Inst_VOPC__V_CMP_LE_U32::execute(GPUDynInstPtr gpuDynInst)
5145 {
5146 Wavefront *wf = gpuDynInst->wavefront();
5147 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5148 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5149 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5150
5151 src0.readSrc();
5152 src1.read();
5153
5154 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5155 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5156
5157 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5158 if (wf->execMask(lane)) {
5159 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
5160 }
5161 }
5162
5163 vcc.write();
5164 } // execute
5165 // --- Inst_VOPC__V_CMP_GT_U32 class methods ---
5166
5167 Inst_VOPC__V_CMP_GT_U32::Inst_VOPC__V_CMP_GT_U32(InFmt_VOPC *iFmt)
5168 : Inst_VOPC(iFmt, "v_cmp_gt_u32")
5169 {
5170 setFlag(ALU);
5171 } // Inst_VOPC__V_CMP_GT_U32
5172
5173 Inst_VOPC__V_CMP_GT_U32::~Inst_VOPC__V_CMP_GT_U32()
5174 {
5175 } // ~Inst_VOPC__V_CMP_GT_U32
5176
5177 // --- description from .arch file ---
5178 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
5179 void
5180 Inst_VOPC__V_CMP_GT_U32::execute(GPUDynInstPtr gpuDynInst)
5181 {
5182 Wavefront *wf = gpuDynInst->wavefront();
5183 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5184 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5185 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5186
5187 src0.readSrc();
5188 src1.read();
5189
5190 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5191 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5192
5193 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5194 if (wf->execMask(lane)) {
5195 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
5196 }
5197 }
5198
5199 vcc.write();
5200 } // execute
5201 // --- Inst_VOPC__V_CMP_NE_U32 class methods ---
5202
5203 Inst_VOPC__V_CMP_NE_U32::Inst_VOPC__V_CMP_NE_U32(InFmt_VOPC *iFmt)
5204 : Inst_VOPC(iFmt, "v_cmp_ne_u32")
5205 {
5206 setFlag(ALU);
5207 } // Inst_VOPC__V_CMP_NE_U32
5208
5209 Inst_VOPC__V_CMP_NE_U32::~Inst_VOPC__V_CMP_NE_U32()
5210 {
5211 } // ~Inst_VOPC__V_CMP_NE_U32
5212
5213 // --- description from .arch file ---
5214 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
5215 void
5216 Inst_VOPC__V_CMP_NE_U32::execute(GPUDynInstPtr gpuDynInst)
5217 {
5218 Wavefront *wf = gpuDynInst->wavefront();
5219 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5220 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5221 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5222
5223 src0.readSrc();
5224 src1.read();
5225
5226 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5227 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5228
5229 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5230 if (wf->execMask(lane)) {
5231 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
5232 }
5233 }
5234
5235 vcc.write();
5236 } // execute
5237 // --- Inst_VOPC__V_CMP_GE_U32 class methods ---
5238
5239 Inst_VOPC__V_CMP_GE_U32::Inst_VOPC__V_CMP_GE_U32(InFmt_VOPC *iFmt)
5240 : Inst_VOPC(iFmt, "v_cmp_ge_u32")
5241 {
5242 setFlag(ALU);
5243 } // Inst_VOPC__V_CMP_GE_U32
5244
5245 Inst_VOPC__V_CMP_GE_U32::~Inst_VOPC__V_CMP_GE_U32()
5246 {
5247 } // ~Inst_VOPC__V_CMP_GE_U32
5248
5249 // --- description from .arch file ---
5250 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
5251 void
5252 Inst_VOPC__V_CMP_GE_U32::execute(GPUDynInstPtr gpuDynInst)
5253 {
5254 Wavefront *wf = gpuDynInst->wavefront();
5255 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5256 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5257 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5258
5259 src0.readSrc();
5260 src1.read();
5261
5262 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5263 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5264
5265 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5266 if (wf->execMask(lane)) {
5267 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
5268 }
5269 }
5270
5271 vcc.write();
5272 } // execute
5273 // --- Inst_VOPC__V_CMP_T_U32 class methods ---
5274
5275 Inst_VOPC__V_CMP_T_U32::Inst_VOPC__V_CMP_T_U32(InFmt_VOPC *iFmt)
5276 : Inst_VOPC(iFmt, "v_cmp_t_u32")
5277 {
5278 setFlag(ALU);
5279 } // Inst_VOPC__V_CMP_T_U32
5280
5281 Inst_VOPC__V_CMP_T_U32::~Inst_VOPC__V_CMP_T_U32()
5282 {
5283 } // ~Inst_VOPC__V_CMP_T_U32
5284
5285 // --- description from .arch file ---
5286 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
5287 void
5288 Inst_VOPC__V_CMP_T_U32::execute(GPUDynInstPtr gpuDynInst)
5289 {
5290 Wavefront *wf = gpuDynInst->wavefront();
5291 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5292
5293 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5294 if (wf->execMask(lane)) {
5295 vcc.setBit(lane, 1);
5296 }
5297 }
5298
5299 vcc.write();
5300 } // execute
5301 // --- Inst_VOPC__V_CMPX_F_I32 class methods ---
5302
5303 Inst_VOPC__V_CMPX_F_I32::Inst_VOPC__V_CMPX_F_I32(InFmt_VOPC *iFmt)
5304 : Inst_VOPC(iFmt, "v_cmpx_f_i32")
5305 {
5306 setFlag(ALU);
5307 setFlag(WritesEXEC);
5308 } // Inst_VOPC__V_CMPX_F_I32
5309
5310 Inst_VOPC__V_CMPX_F_I32::~Inst_VOPC__V_CMPX_F_I32()
5311 {
5312 } // ~Inst_VOPC__V_CMPX_F_I32
5313
5314 // --- description from .arch file ---
5315 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
5316 void
5317 Inst_VOPC__V_CMPX_F_I32::execute(GPUDynInstPtr gpuDynInst)
5318 {
5319 Wavefront *wf = gpuDynInst->wavefront();
5320 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5321
5322 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5323 if (wf->execMask(lane)) {
5324 vcc.setBit(lane, 0);
5325 }
5326 }
5327
5328 wf->execMask() = vcc.rawData();
5329 vcc.write();
5330 } // execute
5331 // --- Inst_VOPC__V_CMPX_LT_I32 class methods ---
5332
5333 Inst_VOPC__V_CMPX_LT_I32::Inst_VOPC__V_CMPX_LT_I32(InFmt_VOPC *iFmt)
5334 : Inst_VOPC(iFmt, "v_cmpx_lt_i32")
5335 {
5336 setFlag(ALU);
5337 setFlag(WritesEXEC);
5338 } // Inst_VOPC__V_CMPX_LT_I32
5339
5340 Inst_VOPC__V_CMPX_LT_I32::~Inst_VOPC__V_CMPX_LT_I32()
5341 {
5342 } // ~Inst_VOPC__V_CMPX_LT_I32
5343
5344 // --- description from .arch file ---
5345 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5346 void
5347 Inst_VOPC__V_CMPX_LT_I32::execute(GPUDynInstPtr gpuDynInst)
5348 {
5349 Wavefront *wf = gpuDynInst->wavefront();
5350 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
5351 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
5352 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5353
5354 src0.readSrc();
5355 src1.read();
5356
5357 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5358 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5359
5360 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5361 if (wf->execMask(lane)) {
5362 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5363 }
5364 }
5365
5366 wf->execMask() = vcc.rawData();
5367 vcc.write();
5368 } // execute
5369 // --- Inst_VOPC__V_CMPX_EQ_I32 class methods ---
5370
5371 Inst_VOPC__V_CMPX_EQ_I32::Inst_VOPC__V_CMPX_EQ_I32(InFmt_VOPC *iFmt)
5372 : Inst_VOPC(iFmt, "v_cmpx_eq_i32")
5373 {
5374 setFlag(ALU);
5375 setFlag(WritesEXEC);
5376 } // Inst_VOPC__V_CMPX_EQ_I32
5377
5378 Inst_VOPC__V_CMPX_EQ_I32::~Inst_VOPC__V_CMPX_EQ_I32()
5379 {
5380 } // ~Inst_VOPC__V_CMPX_EQ_I32
5381
5382 // --- description from .arch file ---
5383 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5384 void
5385 Inst_VOPC__V_CMPX_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
5386 {
5387 Wavefront *wf = gpuDynInst->wavefront();
5388 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
5389 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
5390 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5391
5392 src0.readSrc();
5393 src1.read();
5394
5395 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5396 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5397
5398 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5399 if (wf->execMask(lane)) {
5400 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5401 }
5402 }
5403
5404 wf->execMask() = vcc.rawData();
5405 vcc.write();
5406 } // execute
5407 // --- Inst_VOPC__V_CMPX_LE_I32 class methods ---
5408
5409 Inst_VOPC__V_CMPX_LE_I32::Inst_VOPC__V_CMPX_LE_I32(InFmt_VOPC *iFmt)
5410 : Inst_VOPC(iFmt, "v_cmpx_le_i32")
5411 {
5412 setFlag(ALU);
5413 setFlag(WritesEXEC);
5414 } // Inst_VOPC__V_CMPX_LE_I32
5415
5416 Inst_VOPC__V_CMPX_LE_I32::~Inst_VOPC__V_CMPX_LE_I32()
5417 {
5418 } // ~Inst_VOPC__V_CMPX_LE_I32
5419
5420 // --- description from .arch file ---
5421 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5422 void
5423 Inst_VOPC__V_CMPX_LE_I32::execute(GPUDynInstPtr gpuDynInst)
5424 {
5425 Wavefront *wf = gpuDynInst->wavefront();
5426 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
5427 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
5428 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5429
5430 src0.readSrc();
5431 src1.read();
5432
5433 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5434 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5435
5436 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5437 if (wf->execMask(lane)) {
5438 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
5439 }
5440 }
5441
5442 wf->execMask() = vcc.rawData();
5443 vcc.write();
5444 } // execute
5445 // --- Inst_VOPC__V_CMPX_GT_I32 class methods ---
5446
5447 Inst_VOPC__V_CMPX_GT_I32::Inst_VOPC__V_CMPX_GT_I32(InFmt_VOPC *iFmt)
5448 : Inst_VOPC(iFmt, "v_cmpx_gt_i32")
5449 {
5450 setFlag(ALU);
5451 setFlag(WritesEXEC);
5452 } // Inst_VOPC__V_CMPX_GT_I32
5453
5454 Inst_VOPC__V_CMPX_GT_I32::~Inst_VOPC__V_CMPX_GT_I32()
5455 {
5456 } // ~Inst_VOPC__V_CMPX_GT_I32
5457
5458 // --- description from .arch file ---
5459 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
5460 void
5461 Inst_VOPC__V_CMPX_GT_I32::execute(GPUDynInstPtr gpuDynInst)
5462 {
5463 Wavefront *wf = gpuDynInst->wavefront();
5464 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
5465 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
5466 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5467
5468 src0.readSrc();
5469 src1.read();
5470
5471 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5472 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5473
5474 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5475 if (wf->execMask(lane)) {
5476 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
5477 }
5478 }
5479
5480 wf->execMask() = vcc.rawData();
5481 vcc.write();
5482 } // execute
5483 // --- Inst_VOPC__V_CMPX_NE_I32 class methods ---
5484
5485 Inst_VOPC__V_CMPX_NE_I32::Inst_VOPC__V_CMPX_NE_I32(InFmt_VOPC *iFmt)
5486 : Inst_VOPC(iFmt, "v_cmpx_ne_i32")
5487 {
5488 setFlag(ALU);
5489 setFlag(WritesEXEC);
5490 } // Inst_VOPC__V_CMPX_NE_I32
5491
5492 Inst_VOPC__V_CMPX_NE_I32::~Inst_VOPC__V_CMPX_NE_I32()
5493 {
5494 } // ~Inst_VOPC__V_CMPX_NE_I32
5495
5496 // --- description from .arch file ---
5497 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
5498 void
5499 Inst_VOPC__V_CMPX_NE_I32::execute(GPUDynInstPtr gpuDynInst)
5500 {
5501 Wavefront *wf = gpuDynInst->wavefront();
5502 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
5503 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
5504 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5505
5506 src0.readSrc();
5507 src1.read();
5508
5509 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5510 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5511
5512 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5513 if (wf->execMask(lane)) {
5514 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
5515 }
5516 }
5517
5518 wf->execMask() = vcc.rawData();
5519 vcc.write();
5520 } // execute
5521 // --- Inst_VOPC__V_CMPX_GE_I32 class methods ---
5522
5523 Inst_VOPC__V_CMPX_GE_I32::Inst_VOPC__V_CMPX_GE_I32(InFmt_VOPC *iFmt)
5524 : Inst_VOPC(iFmt, "v_cmpx_ge_i32")
5525 {
5526 setFlag(ALU);
5527 setFlag(WritesEXEC);
5528 } // Inst_VOPC__V_CMPX_GE_I32
5529
5530 Inst_VOPC__V_CMPX_GE_I32::~Inst_VOPC__V_CMPX_GE_I32()
5531 {
5532 } // ~Inst_VOPC__V_CMPX_GE_I32
5533
5534 // --- description from .arch file ---
5535 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
5536 void
5537 Inst_VOPC__V_CMPX_GE_I32::execute(GPUDynInstPtr gpuDynInst)
5538 {
5539 Wavefront *wf = gpuDynInst->wavefront();
5540 ConstVecOperandI32 src0(gpuDynInst, instData.SRC0);
5541 ConstVecOperandI32 src1(gpuDynInst, instData.VSRC1);
5542 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5543
5544 src0.readSrc();
5545 src1.read();
5546
5547 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5548 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5549
5550 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5551 if (wf->execMask(lane)) {
5552 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
5553 }
5554 }
5555
5556 wf->execMask() = vcc.rawData();
5557 vcc.write();
5558 } // execute
5559 // --- Inst_VOPC__V_CMPX_T_I32 class methods ---
5560
5561 Inst_VOPC__V_CMPX_T_I32::Inst_VOPC__V_CMPX_T_I32(InFmt_VOPC *iFmt)
5562 : Inst_VOPC(iFmt, "v_cmpx_t_i32")
5563 {
5564 setFlag(ALU);
5565 setFlag(WritesEXEC);
5566 } // Inst_VOPC__V_CMPX_T_I32
5567
5568 Inst_VOPC__V_CMPX_T_I32::~Inst_VOPC__V_CMPX_T_I32()
5569 {
5570 } // ~Inst_VOPC__V_CMPX_T_I32
5571
5572 // --- description from .arch file ---
5573 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
5574 void
5575 Inst_VOPC__V_CMPX_T_I32::execute(GPUDynInstPtr gpuDynInst)
5576 {
5577 Wavefront *wf = gpuDynInst->wavefront();
5578 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5579
5580 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5581 if (wf->execMask(lane)) {
5582 vcc.setBit(lane, 1);
5583 }
5584 }
5585
5586 wf->execMask() = vcc.rawData();
5587 vcc.write();
5588 } // execute
5589 // --- Inst_VOPC__V_CMPX_F_U32 class methods ---
5590
5591 Inst_VOPC__V_CMPX_F_U32::Inst_VOPC__V_CMPX_F_U32(InFmt_VOPC *iFmt)
5592 : Inst_VOPC(iFmt, "v_cmpx_f_u32")
5593 {
5594 setFlag(ALU);
5595 setFlag(WritesEXEC);
5596 } // Inst_VOPC__V_CMPX_F_U32
5597
5598 Inst_VOPC__V_CMPX_F_U32::~Inst_VOPC__V_CMPX_F_U32()
5599 {
5600 } // ~Inst_VOPC__V_CMPX_F_U32
5601
5602 // --- description from .arch file ---
5603 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
5604 void
5605 Inst_VOPC__V_CMPX_F_U32::execute(GPUDynInstPtr gpuDynInst)
5606 {
5607 Wavefront *wf = gpuDynInst->wavefront();
5608 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5609
5610 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5611 if (wf->execMask(lane)) {
5612 vcc.setBit(lane, 0);
5613 }
5614 }
5615
5616 wf->execMask() = vcc.rawData();
5617 vcc.write();
5618 } // execute
5619 // --- Inst_VOPC__V_CMPX_LT_U32 class methods ---
5620
5621 Inst_VOPC__V_CMPX_LT_U32::Inst_VOPC__V_CMPX_LT_U32(InFmt_VOPC *iFmt)
5622 : Inst_VOPC(iFmt, "v_cmpx_lt_u32")
5623 {
5624 setFlag(ALU);
5625 setFlag(WritesEXEC);
5626 } // Inst_VOPC__V_CMPX_LT_U32
5627
5628 Inst_VOPC__V_CMPX_LT_U32::~Inst_VOPC__V_CMPX_LT_U32()
5629 {
5630 } // ~Inst_VOPC__V_CMPX_LT_U32
5631
5632 // --- description from .arch file ---
5633 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5634 void
5635 Inst_VOPC__V_CMPX_LT_U32::execute(GPUDynInstPtr gpuDynInst)
5636 {
5637 Wavefront *wf = gpuDynInst->wavefront();
5638 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5639 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5640 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5641
5642 src0.readSrc();
5643 src1.read();
5644
5645 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5646 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5647
5648 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5649 if (wf->execMask(lane)) {
5650 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5651 }
5652 }
5653
5654 wf->execMask() = vcc.rawData();
5655 vcc.write();
5656 } // execute
5657 // --- Inst_VOPC__V_CMPX_EQ_U32 class methods ---
5658
5659 Inst_VOPC__V_CMPX_EQ_U32::Inst_VOPC__V_CMPX_EQ_U32(InFmt_VOPC *iFmt)
5660 : Inst_VOPC(iFmt, "v_cmpx_eq_u32")
5661 {
5662 setFlag(ALU);
5663 setFlag(WritesEXEC);
5664 } // Inst_VOPC__V_CMPX_EQ_U32
5665
5666 Inst_VOPC__V_CMPX_EQ_U32::~Inst_VOPC__V_CMPX_EQ_U32()
5667 {
5668 } // ~Inst_VOPC__V_CMPX_EQ_U32
5669
5670 // --- description from .arch file ---
5671 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5672 void
5673 Inst_VOPC__V_CMPX_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
5674 {
5675 Wavefront *wf = gpuDynInst->wavefront();
5676 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5677 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5678 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5679
5680 src0.readSrc();
5681 src1.read();
5682
5683 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5684 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5685
5686 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5687 if (wf->execMask(lane)) {
5688 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5689 }
5690 }
5691
5692 wf->execMask() = vcc.rawData();
5693 vcc.write();
5694 } // execute
5695 // --- Inst_VOPC__V_CMPX_LE_U32 class methods ---
5696
5697 Inst_VOPC__V_CMPX_LE_U32::Inst_VOPC__V_CMPX_LE_U32(InFmt_VOPC *iFmt)
5698 : Inst_VOPC(iFmt, "v_cmpx_le_u32")
5699 {
5700 setFlag(ALU);
5701 setFlag(WritesEXEC);
5702 } // Inst_VOPC__V_CMPX_LE_U32
5703
5704 Inst_VOPC__V_CMPX_LE_U32::~Inst_VOPC__V_CMPX_LE_U32()
5705 {
5706 } // ~Inst_VOPC__V_CMPX_LE_U32
5707
5708 // --- description from .arch file ---
5709 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5710 void
5711 Inst_VOPC__V_CMPX_LE_U32::execute(GPUDynInstPtr gpuDynInst)
5712 {
5713 Wavefront *wf = gpuDynInst->wavefront();
5714 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5715 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5716 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5717
5718 src0.readSrc();
5719 src1.read();
5720
5721 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5722 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5723
5724 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5725 if (wf->execMask(lane)) {
5726 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
5727 }
5728 }
5729
5730 wf->execMask() = vcc.rawData();
5731 vcc.write();
5732 } // execute
5733 // --- Inst_VOPC__V_CMPX_GT_U32 class methods ---
5734
5735 Inst_VOPC__V_CMPX_GT_U32::Inst_VOPC__V_CMPX_GT_U32(InFmt_VOPC *iFmt)
5736 : Inst_VOPC(iFmt, "v_cmpx_gt_u32")
5737 {
5738 setFlag(ALU);
5739 setFlag(WritesEXEC);
5740 } // Inst_VOPC__V_CMPX_GT_U32
5741
5742 Inst_VOPC__V_CMPX_GT_U32::~Inst_VOPC__V_CMPX_GT_U32()
5743 {
5744 } // ~Inst_VOPC__V_CMPX_GT_U32
5745
5746 // --- description from .arch file ---
5747 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
5748 void
5749 Inst_VOPC__V_CMPX_GT_U32::execute(GPUDynInstPtr gpuDynInst)
5750 {
5751 Wavefront *wf = gpuDynInst->wavefront();
5752 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5753 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5754 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5755
5756 src0.readSrc();
5757 src1.read();
5758
5759 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5760 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5761
5762 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5763 if (wf->execMask(lane)) {
5764 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
5765 }
5766 }
5767
5768 wf->execMask() = vcc.rawData();
5769 vcc.write();
5770 } // execute
5771 // --- Inst_VOPC__V_CMPX_NE_U32 class methods ---
5772
5773 Inst_VOPC__V_CMPX_NE_U32::Inst_VOPC__V_CMPX_NE_U32(InFmt_VOPC *iFmt)
5774 : Inst_VOPC(iFmt, "v_cmpx_ne_u32")
5775 {
5776 setFlag(ALU);
5777 setFlag(WritesEXEC);
5778 } // Inst_VOPC__V_CMPX_NE_U32
5779
5780 Inst_VOPC__V_CMPX_NE_U32::~Inst_VOPC__V_CMPX_NE_U32()
5781 {
5782 } // ~Inst_VOPC__V_CMPX_NE_U32
5783
5784 // --- description from .arch file ---
5785 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
5786 void
5787 Inst_VOPC__V_CMPX_NE_U32::execute(GPUDynInstPtr gpuDynInst)
5788 {
5789 Wavefront *wf = gpuDynInst->wavefront();
5790 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5791 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5792 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5793
5794 src0.readSrc();
5795 src1.read();
5796
5797 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5798 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5799
5800 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5801 if (wf->execMask(lane)) {
5802 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
5803 }
5804 }
5805
5806 wf->execMask() = vcc.rawData();
5807 vcc.write();
5808 } // execute
5809 // --- Inst_VOPC__V_CMPX_GE_U32 class methods ---
5810
5811 Inst_VOPC__V_CMPX_GE_U32::Inst_VOPC__V_CMPX_GE_U32(InFmt_VOPC *iFmt)
5812 : Inst_VOPC(iFmt, "v_cmpx_ge_u32")
5813 {
5814 setFlag(ALU);
5815 setFlag(WritesEXEC);
5816 } // Inst_VOPC__V_CMPX_GE_U32
5817
5818 Inst_VOPC__V_CMPX_GE_U32::~Inst_VOPC__V_CMPX_GE_U32()
5819 {
5820 } // ~Inst_VOPC__V_CMPX_GE_U32
5821
5822 // --- description from .arch file ---
5823 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
5824 void
5825 Inst_VOPC__V_CMPX_GE_U32::execute(GPUDynInstPtr gpuDynInst)
5826 {
5827 Wavefront *wf = gpuDynInst->wavefront();
5828 ConstVecOperandU32 src0(gpuDynInst, instData.SRC0);
5829 ConstVecOperandU32 src1(gpuDynInst, instData.VSRC1);
5830 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5831
5832 src0.readSrc();
5833 src1.read();
5834
5835 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5836 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5837
5838 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5839 if (wf->execMask(lane)) {
5840 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
5841 }
5842 }
5843
5844 wf->execMask() = vcc.rawData();
5845 vcc.write();
5846 } // execute
5847 // --- Inst_VOPC__V_CMPX_T_U32 class methods ---
5848
5849 Inst_VOPC__V_CMPX_T_U32::Inst_VOPC__V_CMPX_T_U32(InFmt_VOPC *iFmt)
5850 : Inst_VOPC(iFmt, "v_cmpx_t_u32")
5851 {
5852 setFlag(ALU);
5853 setFlag(WritesEXEC);
5854 } // Inst_VOPC__V_CMPX_T_U32
5855
5856 Inst_VOPC__V_CMPX_T_U32::~Inst_VOPC__V_CMPX_T_U32()
5857 {
5858 } // ~Inst_VOPC__V_CMPX_T_U32
5859
5860 // --- description from .arch file ---
5861 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
5862 void
5863 Inst_VOPC__V_CMPX_T_U32::execute(GPUDynInstPtr gpuDynInst)
5864 {
5865 Wavefront *wf = gpuDynInst->wavefront();
5866 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5867
5868 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5869 if (wf->execMask(lane)) {
5870 vcc.setBit(lane, 1);
5871 }
5872 }
5873
5874 wf->execMask() = vcc.rawData();
5875 vcc.write();
5876 } // execute
5877 // --- Inst_VOPC__V_CMP_F_I64 class methods ---
5878
5879 Inst_VOPC__V_CMP_F_I64::Inst_VOPC__V_CMP_F_I64(InFmt_VOPC *iFmt)
5880 : Inst_VOPC(iFmt, "v_cmp_f_i64")
5881 {
5882 setFlag(ALU);
5883 } // Inst_VOPC__V_CMP_F_I64
5884
5885 Inst_VOPC__V_CMP_F_I64::~Inst_VOPC__V_CMP_F_I64()
5886 {
5887 } // ~Inst_VOPC__V_CMP_F_I64
5888
5889 // --- description from .arch file ---
5890 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
5891 void
5892 Inst_VOPC__V_CMP_F_I64::execute(GPUDynInstPtr gpuDynInst)
5893 {
5894 Wavefront *wf = gpuDynInst->wavefront();
5895 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5896
5897 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5898 if (wf->execMask(lane)) {
5899 vcc.setBit(lane, 0);
5900 }
5901 }
5902
5903 vcc.write();
5904 } // execute
5905 // --- Inst_VOPC__V_CMP_LT_I64 class methods ---
5906
5907 Inst_VOPC__V_CMP_LT_I64::Inst_VOPC__V_CMP_LT_I64(InFmt_VOPC *iFmt)
5908 : Inst_VOPC(iFmt, "v_cmp_lt_i64")
5909 {
5910 setFlag(ALU);
5911 } // Inst_VOPC__V_CMP_LT_I64
5912
5913 Inst_VOPC__V_CMP_LT_I64::~Inst_VOPC__V_CMP_LT_I64()
5914 {
5915 } // ~Inst_VOPC__V_CMP_LT_I64
5916
5917 // --- description from .arch file ---
5918 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5919 void
5920 Inst_VOPC__V_CMP_LT_I64::execute(GPUDynInstPtr gpuDynInst)
5921 {
5922 Wavefront *wf = gpuDynInst->wavefront();
5923 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
5924 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
5925 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5926
5927 src0.readSrc();
5928 src1.read();
5929
5930 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5931 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5932
5933 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5934 if (wf->execMask(lane)) {
5935 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5936 }
5937 }
5938
5939 vcc.write();
5940 } // execute
5941 // --- Inst_VOPC__V_CMP_EQ_I64 class methods ---
5942
5943 Inst_VOPC__V_CMP_EQ_I64::Inst_VOPC__V_CMP_EQ_I64(InFmt_VOPC *iFmt)
5944 : Inst_VOPC(iFmt, "v_cmp_eq_i64")
5945 {
5946 setFlag(ALU);
5947 } // Inst_VOPC__V_CMP_EQ_I64
5948
5949 Inst_VOPC__V_CMP_EQ_I64::~Inst_VOPC__V_CMP_EQ_I64()
5950 {
5951 } // ~Inst_VOPC__V_CMP_EQ_I64
5952
5953 // --- description from .arch file ---
5954 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5955 void
5956 Inst_VOPC__V_CMP_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
5957 {
5958 Wavefront *wf = gpuDynInst->wavefront();
5959 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
5960 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
5961 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5962
5963 src0.readSrc();
5964 src1.read();
5965
5966 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
5967 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
5968
5969 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5970 if (wf->execMask(lane)) {
5971 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5972 }
5973 }
5974
5975 vcc.write();
5976 } // execute
5977 // --- Inst_VOPC__V_CMP_LE_I64 class methods ---
5978
5979 Inst_VOPC__V_CMP_LE_I64::Inst_VOPC__V_CMP_LE_I64(InFmt_VOPC *iFmt)
5980 : Inst_VOPC(iFmt, "v_cmp_le_i64")
5981 {
5982 setFlag(ALU);
5983 } // Inst_VOPC__V_CMP_LE_I64
5984
5985 Inst_VOPC__V_CMP_LE_I64::~Inst_VOPC__V_CMP_LE_I64()
5986 {
5987 } // ~Inst_VOPC__V_CMP_LE_I64
5988
5989 // --- description from .arch file ---
5990 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5991 void
5992 Inst_VOPC__V_CMP_LE_I64::execute(GPUDynInstPtr gpuDynInst)
5993 {
5994 Wavefront *wf = gpuDynInst->wavefront();
5995 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
5996 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
5997 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
5998
5999 src0.readSrc();
6000 src1.read();
6001
6002 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6003 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6004
6005 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6006 if (wf->execMask(lane)) {
6007 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6008 }
6009 }
6010
6011 vcc.write();
6012 } // execute
6013 // --- Inst_VOPC__V_CMP_GT_I64 class methods ---
6014
6015 Inst_VOPC__V_CMP_GT_I64::Inst_VOPC__V_CMP_GT_I64(InFmt_VOPC *iFmt)
6016 : Inst_VOPC(iFmt, "v_cmp_gt_i64")
6017 {
6018 setFlag(ALU);
6019 } // Inst_VOPC__V_CMP_GT_I64
6020
6021 Inst_VOPC__V_CMP_GT_I64::~Inst_VOPC__V_CMP_GT_I64()
6022 {
6023 } // ~Inst_VOPC__V_CMP_GT_I64
6024
6025 // --- description from .arch file ---
6026 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6027 void
6028 Inst_VOPC__V_CMP_GT_I64::execute(GPUDynInstPtr gpuDynInst)
6029 {
6030 Wavefront *wf = gpuDynInst->wavefront();
6031 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6032 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6033 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6034
6035 src0.readSrc();
6036 src1.read();
6037
6038 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6039 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6040
6041 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6042 if (wf->execMask(lane)) {
6043 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6044 }
6045 }
6046
6047 vcc.write();
6048 } // execute
6049 // --- Inst_VOPC__V_CMP_NE_I64 class methods ---
6050
6051 Inst_VOPC__V_CMP_NE_I64::Inst_VOPC__V_CMP_NE_I64(InFmt_VOPC *iFmt)
6052 : Inst_VOPC(iFmt, "v_cmp_ne_i64")
6053 {
6054 setFlag(ALU);
6055 } // Inst_VOPC__V_CMP_NE_I64
6056
6057 Inst_VOPC__V_CMP_NE_I64::~Inst_VOPC__V_CMP_NE_I64()
6058 {
6059 } // ~Inst_VOPC__V_CMP_NE_I64
6060
6061 // --- description from .arch file ---
6062 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6063 void
6064 Inst_VOPC__V_CMP_NE_I64::execute(GPUDynInstPtr gpuDynInst)
6065 {
6066 Wavefront *wf = gpuDynInst->wavefront();
6067 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6068 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6069 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6070
6071 src0.readSrc();
6072 src1.read();
6073
6074 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6075 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6076
6077 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6078 if (wf->execMask(lane)) {
6079 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6080 }
6081 }
6082
6083 vcc.write();
6084 } // execute
6085 // --- Inst_VOPC__V_CMP_GE_I64 class methods ---
6086
6087 Inst_VOPC__V_CMP_GE_I64::Inst_VOPC__V_CMP_GE_I64(InFmt_VOPC *iFmt)
6088 : Inst_VOPC(iFmt, "v_cmp_ge_i64")
6089 {
6090 setFlag(ALU);
6091 } // Inst_VOPC__V_CMP_GE_I64
6092
6093 Inst_VOPC__V_CMP_GE_I64::~Inst_VOPC__V_CMP_GE_I64()
6094 {
6095 } // ~Inst_VOPC__V_CMP_GE_I64
6096
6097 // --- description from .arch file ---
6098 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6099 void
6100 Inst_VOPC__V_CMP_GE_I64::execute(GPUDynInstPtr gpuDynInst)
6101 {
6102 Wavefront *wf = gpuDynInst->wavefront();
6103 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6104 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6105 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6106
6107 src0.readSrc();
6108 src1.read();
6109
6110 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6111 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6112
6113 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6114 if (wf->execMask(lane)) {
6115 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6116 }
6117 }
6118
6119 vcc.write();
6120 } // execute
6121 // --- Inst_VOPC__V_CMP_T_I64 class methods ---
6122
6123 Inst_VOPC__V_CMP_T_I64::Inst_VOPC__V_CMP_T_I64(InFmt_VOPC *iFmt)
6124 : Inst_VOPC(iFmt, "v_cmp_t_i64")
6125 {
6126 setFlag(ALU);
6127 } // Inst_VOPC__V_CMP_T_I64
6128
6129 Inst_VOPC__V_CMP_T_I64::~Inst_VOPC__V_CMP_T_I64()
6130 {
6131 } // ~Inst_VOPC__V_CMP_T_I64
6132
6133 // --- description from .arch file ---
6134 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
6135 void
6136 Inst_VOPC__V_CMP_T_I64::execute(GPUDynInstPtr gpuDynInst)
6137 {
6138 Wavefront *wf = gpuDynInst->wavefront();
6139 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6140
6141 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6142 if (wf->execMask(lane)) {
6143 vcc.setBit(lane, 1);
6144 }
6145 }
6146
6147 vcc.write();
6148 } // execute
6149 // --- Inst_VOPC__V_CMP_F_U64 class methods ---
6150
6151 Inst_VOPC__V_CMP_F_U64::Inst_VOPC__V_CMP_F_U64(InFmt_VOPC *iFmt)
6152 : Inst_VOPC(iFmt, "v_cmp_f_u64")
6153 {
6154 setFlag(ALU);
6155 } // Inst_VOPC__V_CMP_F_U64
6156
6157 Inst_VOPC__V_CMP_F_U64::~Inst_VOPC__V_CMP_F_U64()
6158 {
6159 } // ~Inst_VOPC__V_CMP_F_U64
6160
6161 // --- description from .arch file ---
6162 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
6163 void
6164 Inst_VOPC__V_CMP_F_U64::execute(GPUDynInstPtr gpuDynInst)
6165 {
6166 Wavefront *wf = gpuDynInst->wavefront();
6167 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6168
6169 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6170 if (wf->execMask(lane)) {
6171 vcc.setBit(lane, 0);
6172 }
6173 }
6174
6175 vcc.write();
6176 } // execute
6177 // --- Inst_VOPC__V_CMP_LT_U64 class methods ---
6178
6179 Inst_VOPC__V_CMP_LT_U64::Inst_VOPC__V_CMP_LT_U64(InFmt_VOPC *iFmt)
6180 : Inst_VOPC(iFmt, "v_cmp_lt_u64")
6181 {
6182 setFlag(ALU);
6183 } // Inst_VOPC__V_CMP_LT_U64
6184
6185 Inst_VOPC__V_CMP_LT_U64::~Inst_VOPC__V_CMP_LT_U64()
6186 {
6187 } // ~Inst_VOPC__V_CMP_LT_U64
6188
6189 // --- description from .arch file ---
6190 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
6191 void
6192 Inst_VOPC__V_CMP_LT_U64::execute(GPUDynInstPtr gpuDynInst)
6193 {
6194 Wavefront *wf = gpuDynInst->wavefront();
6195 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6196 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6197 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6198
6199 src0.readSrc();
6200 src1.read();
6201
6202 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6203 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6204
6205 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6206 if (wf->execMask(lane)) {
6207 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
6208 }
6209 }
6210
6211 vcc.write();
6212 } // execute
6213 // --- Inst_VOPC__V_CMP_EQ_U64 class methods ---
6214
6215 Inst_VOPC__V_CMP_EQ_U64::Inst_VOPC__V_CMP_EQ_U64(InFmt_VOPC *iFmt)
6216 : Inst_VOPC(iFmt, "v_cmp_eq_u64")
6217 {
6218 setFlag(ALU);
6219 } // Inst_VOPC__V_CMP_EQ_U64
6220
6221 Inst_VOPC__V_CMP_EQ_U64::~Inst_VOPC__V_CMP_EQ_U64()
6222 {
6223 } // ~Inst_VOPC__V_CMP_EQ_U64
6224
6225 // --- description from .arch file ---
6226 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
6227 void
6228 Inst_VOPC__V_CMP_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
6229 {
6230 Wavefront *wf = gpuDynInst->wavefront();
6231 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6232 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6233 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6234
6235 src0.readSrc();
6236 src1.read();
6237
6238 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6239 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6240
6241 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6242 if (wf->execMask(lane)) {
6243 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
6244 }
6245 }
6246
6247 vcc.write();
6248 } // execute
6249 // --- Inst_VOPC__V_CMP_LE_U64 class methods ---
6250
6251 Inst_VOPC__V_CMP_LE_U64::Inst_VOPC__V_CMP_LE_U64(InFmt_VOPC *iFmt)
6252 : Inst_VOPC(iFmt, "v_cmp_le_u64")
6253 {
6254 setFlag(ALU);
6255 } // Inst_VOPC__V_CMP_LE_U64
6256
6257 Inst_VOPC__V_CMP_LE_U64::~Inst_VOPC__V_CMP_LE_U64()
6258 {
6259 } // ~Inst_VOPC__V_CMP_LE_U64
6260
6261 // --- description from .arch file ---
6262 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
6263 void
6264 Inst_VOPC__V_CMP_LE_U64::execute(GPUDynInstPtr gpuDynInst)
6265 {
6266 Wavefront *wf = gpuDynInst->wavefront();
6267 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6268 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6269 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6270
6271 src0.readSrc();
6272 src1.read();
6273
6274 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6275 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6276
6277 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6278 if (wf->execMask(lane)) {
6279 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6280 }
6281 }
6282
6283 vcc.write();
6284 } // execute
6285 // --- Inst_VOPC__V_CMP_GT_U64 class methods ---
6286
6287 Inst_VOPC__V_CMP_GT_U64::Inst_VOPC__V_CMP_GT_U64(InFmt_VOPC *iFmt)
6288 : Inst_VOPC(iFmt, "v_cmp_gt_u64")
6289 {
6290 setFlag(ALU);
6291 } // Inst_VOPC__V_CMP_GT_U64
6292
6293 Inst_VOPC__V_CMP_GT_U64::~Inst_VOPC__V_CMP_GT_U64()
6294 {
6295 } // ~Inst_VOPC__V_CMP_GT_U64
6296
6297 // --- description from .arch file ---
6298 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6299 void
6300 Inst_VOPC__V_CMP_GT_U64::execute(GPUDynInstPtr gpuDynInst)
6301 {
6302 Wavefront *wf = gpuDynInst->wavefront();
6303 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6304 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6305 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6306
6307 src0.readSrc();
6308 src1.read();
6309
6310 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6311 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6312
6313 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6314 if (wf->execMask(lane)) {
6315 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6316 }
6317 }
6318
6319 vcc.write();
6320 } // execute
6321 // --- Inst_VOPC__V_CMP_NE_U64 class methods ---
6322
6323 Inst_VOPC__V_CMP_NE_U64::Inst_VOPC__V_CMP_NE_U64(InFmt_VOPC *iFmt)
6324 : Inst_VOPC(iFmt, "v_cmp_ne_u64")
6325 {
6326 setFlag(ALU);
6327 } // Inst_VOPC__V_CMP_NE_U64
6328
6329 Inst_VOPC__V_CMP_NE_U64::~Inst_VOPC__V_CMP_NE_U64()
6330 {
6331 } // ~Inst_VOPC__V_CMP_NE_U64
6332
6333 // --- description from .arch file ---
6334 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6335 void
6336 Inst_VOPC__V_CMP_NE_U64::execute(GPUDynInstPtr gpuDynInst)
6337 {
6338 Wavefront *wf = gpuDynInst->wavefront();
6339 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6340 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6341 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6342
6343 src0.readSrc();
6344 src1.read();
6345
6346 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6347 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6348
6349 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6350 if (wf->execMask(lane)) {
6351 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6352 }
6353 }
6354
6355 vcc.write();
6356 } // execute
6357 // --- Inst_VOPC__V_CMP_GE_U64 class methods ---
6358
6359 Inst_VOPC__V_CMP_GE_U64::Inst_VOPC__V_CMP_GE_U64(InFmt_VOPC *iFmt)
6360 : Inst_VOPC(iFmt, "v_cmp_ge_u64")
6361 {
6362 setFlag(ALU);
6363 } // Inst_VOPC__V_CMP_GE_U64
6364
6365 Inst_VOPC__V_CMP_GE_U64::~Inst_VOPC__V_CMP_GE_U64()
6366 {
6367 } // ~Inst_VOPC__V_CMP_GE_U64
6368
6369 // --- description from .arch file ---
6370 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6371 void
6372 Inst_VOPC__V_CMP_GE_U64::execute(GPUDynInstPtr gpuDynInst)
6373 {
6374 Wavefront *wf = gpuDynInst->wavefront();
6375 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6376 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6377 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6378
6379 src0.readSrc();
6380 src1.read();
6381
6382 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6383 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6384
6385 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6386 if (wf->execMask(lane)) {
6387 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6388 }
6389 }
6390
6391 vcc.write();
6392 } // execute
6393 // --- Inst_VOPC__V_CMP_T_U64 class methods ---
6394
6395 Inst_VOPC__V_CMP_T_U64::Inst_VOPC__V_CMP_T_U64(InFmt_VOPC *iFmt)
6396 : Inst_VOPC(iFmt, "v_cmp_t_u64")
6397 {
6398 setFlag(ALU);
6399 } // Inst_VOPC__V_CMP_T_U64
6400
6401 Inst_VOPC__V_CMP_T_U64::~Inst_VOPC__V_CMP_T_U64()
6402 {
6403 } // ~Inst_VOPC__V_CMP_T_U64
6404
6405 // --- description from .arch file ---
6406 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
6407 void
6408 Inst_VOPC__V_CMP_T_U64::execute(GPUDynInstPtr gpuDynInst)
6409 {
6410 Wavefront *wf = gpuDynInst->wavefront();
6411 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6412
6413 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6414 if (wf->execMask(lane)) {
6415 vcc.setBit(lane, 1);
6416 }
6417 }
6418
6419 vcc.write();
6420 } // execute
6421 // --- Inst_VOPC__V_CMPX_F_I64 class methods ---
6422
6423 Inst_VOPC__V_CMPX_F_I64::Inst_VOPC__V_CMPX_F_I64(InFmt_VOPC *iFmt)
6424 : Inst_VOPC(iFmt, "v_cmpx_f_i64")
6425 {
6426 setFlag(ALU);
6427 setFlag(WritesEXEC);
6428 } // Inst_VOPC__V_CMPX_F_I64
6429
6430 Inst_VOPC__V_CMPX_F_I64::~Inst_VOPC__V_CMPX_F_I64()
6431 {
6432 } // ~Inst_VOPC__V_CMPX_F_I64
6433
6434 // --- description from .arch file ---
6435 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
6436 void
6437 Inst_VOPC__V_CMPX_F_I64::execute(GPUDynInstPtr gpuDynInst)
6438 {
6439 Wavefront *wf = gpuDynInst->wavefront();
6440 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6441
6442 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6443 if (wf->execMask(lane)) {
6444 vcc.setBit(lane, 0);
6445 }
6446 }
6447
6448 wf->execMask() = vcc.rawData();
6449 vcc.write();
6450 } // execute
6451 // --- Inst_VOPC__V_CMPX_LT_I64 class methods ---
6452
6453 Inst_VOPC__V_CMPX_LT_I64::Inst_VOPC__V_CMPX_LT_I64(InFmt_VOPC *iFmt)
6454 : Inst_VOPC(iFmt, "v_cmpx_lt_i64")
6455 {
6456 setFlag(ALU);
6457 setFlag(WritesEXEC);
6458 } // Inst_VOPC__V_CMPX_LT_I64
6459
6460 Inst_VOPC__V_CMPX_LT_I64::~Inst_VOPC__V_CMPX_LT_I64()
6461 {
6462 } // ~Inst_VOPC__V_CMPX_LT_I64
6463
6464 // --- description from .arch file ---
6465 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
6466 void
6467 Inst_VOPC__V_CMPX_LT_I64::execute(GPUDynInstPtr gpuDynInst)
6468 {
6469 Wavefront *wf = gpuDynInst->wavefront();
6470 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6471 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6472 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6473
6474 src0.readSrc();
6475 src1.read();
6476
6477 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6478 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6479
6480 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6481 if (wf->execMask(lane)) {
6482 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
6483 }
6484 }
6485
6486 wf->execMask() = vcc.rawData();
6487 vcc.write();
6488 } // execute
6489 // --- Inst_VOPC__V_CMPX_EQ_I64 class methods ---
6490
6491 Inst_VOPC__V_CMPX_EQ_I64::Inst_VOPC__V_CMPX_EQ_I64(InFmt_VOPC *iFmt)
6492 : Inst_VOPC(iFmt, "v_cmpx_eq_i64")
6493 {
6494 setFlag(ALU);
6495 setFlag(WritesEXEC);
6496 } // Inst_VOPC__V_CMPX_EQ_I64
6497
6498 Inst_VOPC__V_CMPX_EQ_I64::~Inst_VOPC__V_CMPX_EQ_I64()
6499 {
6500 } // ~Inst_VOPC__V_CMPX_EQ_I64
6501
6502 // --- description from .arch file ---
6503 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
6504 void
6505 Inst_VOPC__V_CMPX_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
6506 {
6507 Wavefront *wf = gpuDynInst->wavefront();
6508 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6509 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6510 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6511
6512 src0.readSrc();
6513 src1.read();
6514
6515 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6516 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6517
6518 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6519 if (wf->execMask(lane)) {
6520 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
6521 }
6522 }
6523
6524 wf->execMask() = vcc.rawData();
6525 vcc.write();
6526 } // execute
6527 // --- Inst_VOPC__V_CMPX_LE_I64 class methods ---
6528
6529 Inst_VOPC__V_CMPX_LE_I64::Inst_VOPC__V_CMPX_LE_I64(InFmt_VOPC *iFmt)
6530 : Inst_VOPC(iFmt, "v_cmpx_le_i64")
6531 {
6532 setFlag(ALU);
6533 setFlag(WritesEXEC);
6534 } // Inst_VOPC__V_CMPX_LE_I64
6535
6536 Inst_VOPC__V_CMPX_LE_I64::~Inst_VOPC__V_CMPX_LE_I64()
6537 {
6538 } // ~Inst_VOPC__V_CMPX_LE_I64
6539
6540 // --- description from .arch file ---
6541 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
6542 void
6543 Inst_VOPC__V_CMPX_LE_I64::execute(GPUDynInstPtr gpuDynInst)
6544 {
6545 Wavefront *wf = gpuDynInst->wavefront();
6546 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6547 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6548 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6549
6550 src0.readSrc();
6551 src1.read();
6552
6553 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6554 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6555
6556 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6557 if (wf->execMask(lane)) {
6558 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6559 }
6560 }
6561
6562 wf->execMask() = vcc.rawData();
6563 vcc.write();
6564 } // execute
6565 // --- Inst_VOPC__V_CMPX_GT_I64 class methods ---
6566
6567 Inst_VOPC__V_CMPX_GT_I64::Inst_VOPC__V_CMPX_GT_I64(InFmt_VOPC *iFmt)
6568 : Inst_VOPC(iFmt, "v_cmpx_gt_i64")
6569 {
6570 setFlag(ALU);
6571 setFlag(WritesEXEC);
6572 } // Inst_VOPC__V_CMPX_GT_I64
6573
6574 Inst_VOPC__V_CMPX_GT_I64::~Inst_VOPC__V_CMPX_GT_I64()
6575 {
6576 } // ~Inst_VOPC__V_CMPX_GT_I64
6577
6578 // --- description from .arch file ---
6579 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6580 void
6581 Inst_VOPC__V_CMPX_GT_I64::execute(GPUDynInstPtr gpuDynInst)
6582 {
6583 Wavefront *wf = gpuDynInst->wavefront();
6584 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6585 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6586 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6587
6588 src0.readSrc();
6589 src1.read();
6590
6591 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6592 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6593
6594 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6595 if (wf->execMask(lane)) {
6596 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6597 }
6598 }
6599
6600 wf->execMask() = vcc.rawData();
6601 vcc.write();
6602 } // execute
6603 // --- Inst_VOPC__V_CMPX_NE_I64 class methods ---
6604
6605 Inst_VOPC__V_CMPX_NE_I64::Inst_VOPC__V_CMPX_NE_I64(InFmt_VOPC *iFmt)
6606 : Inst_VOPC(iFmt, "v_cmpx_ne_i64")
6607 {
6608 setFlag(ALU);
6609 setFlag(WritesEXEC);
6610 } // Inst_VOPC__V_CMPX_NE_I64
6611
6612 Inst_VOPC__V_CMPX_NE_I64::~Inst_VOPC__V_CMPX_NE_I64()
6613 {
6614 } // ~Inst_VOPC__V_CMPX_NE_I64
6615
6616 // --- description from .arch file ---
6617 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6618 void
6619 Inst_VOPC__V_CMPX_NE_I64::execute(GPUDynInstPtr gpuDynInst)
6620 {
6621 Wavefront *wf = gpuDynInst->wavefront();
6622 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6623 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6624 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6625
6626 src0.readSrc();
6627 src1.read();
6628
6629 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6630 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6631
6632 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6633 if (wf->execMask(lane)) {
6634 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6635 }
6636 }
6637
6638 wf->execMask() = vcc.rawData();
6639 vcc.write();
6640 } // execute
6641 // --- Inst_VOPC__V_CMPX_GE_I64 class methods ---
6642
6643 Inst_VOPC__V_CMPX_GE_I64::Inst_VOPC__V_CMPX_GE_I64(InFmt_VOPC *iFmt)
6644 : Inst_VOPC(iFmt, "v_cmpx_ge_i64")
6645 {
6646 setFlag(ALU);
6647 setFlag(WritesEXEC);
6648 } // Inst_VOPC__V_CMPX_GE_I64
6649
6650 Inst_VOPC__V_CMPX_GE_I64::~Inst_VOPC__V_CMPX_GE_I64()
6651 {
6652 } // ~Inst_VOPC__V_CMPX_GE_I64
6653
6654 // --- description from .arch file ---
6655 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6656 void
6657 Inst_VOPC__V_CMPX_GE_I64::execute(GPUDynInstPtr gpuDynInst)
6658 {
6659 Wavefront *wf = gpuDynInst->wavefront();
6660 ConstVecOperandI64 src0(gpuDynInst, instData.SRC0);
6661 ConstVecOperandI64 src1(gpuDynInst, instData.VSRC1);
6662 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6663
6664 src0.readSrc();
6665 src1.read();
6666
6667 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6668 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6669
6670 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6671 if (wf->execMask(lane)) {
6672 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6673 }
6674 }
6675
6676 wf->execMask() = vcc.rawData();
6677 vcc.write();
6678 } // execute
6679 // --- Inst_VOPC__V_CMPX_T_I64 class methods ---
6680
6681 Inst_VOPC__V_CMPX_T_I64::Inst_VOPC__V_CMPX_T_I64(InFmt_VOPC *iFmt)
6682 : Inst_VOPC(iFmt, "v_cmpx_t_i64")
6683 {
6684 setFlag(ALU);
6685 setFlag(WritesEXEC);
6686 } // Inst_VOPC__V_CMPX_T_I64
6687
6688 Inst_VOPC__V_CMPX_T_I64::~Inst_VOPC__V_CMPX_T_I64()
6689 {
6690 } // ~Inst_VOPC__V_CMPX_T_I64
6691
6692 // --- description from .arch file ---
6693 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
6694 void
6695 Inst_VOPC__V_CMPX_T_I64::execute(GPUDynInstPtr gpuDynInst)
6696 {
6697 Wavefront *wf = gpuDynInst->wavefront();
6698 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6699
6700 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6701 if (wf->execMask(lane)) {
6702 vcc.setBit(lane, 1);
6703 }
6704 }
6705
6706 wf->execMask() = vcc.rawData();
6707 vcc.write();
6708 } // execute
6709 // --- Inst_VOPC__V_CMPX_F_U64 class methods ---
6710
6711 Inst_VOPC__V_CMPX_F_U64::Inst_VOPC__V_CMPX_F_U64(InFmt_VOPC *iFmt)
6712 : Inst_VOPC(iFmt, "v_cmpx_f_u64")
6713 {
6714 setFlag(ALU);
6715 setFlag(WritesEXEC);
6716 } // Inst_VOPC__V_CMPX_F_U64
6717
6718 Inst_VOPC__V_CMPX_F_U64::~Inst_VOPC__V_CMPX_F_U64()
6719 {
6720 } // ~Inst_VOPC__V_CMPX_F_U64
6721
6722 // --- description from .arch file ---
6723 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
6724 void
6725 Inst_VOPC__V_CMPX_F_U64::execute(GPUDynInstPtr gpuDynInst)
6726 {
6727 Wavefront *wf = gpuDynInst->wavefront();
6728 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6729
6730 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6731 if (wf->execMask(lane)) {
6732 vcc.setBit(lane, 0);
6733 }
6734 }
6735
6736 wf->execMask() = vcc.rawData();
6737 vcc.write();
6738 } // execute
6739 // --- Inst_VOPC__V_CMPX_LT_U64 class methods ---
6740
6741 Inst_VOPC__V_CMPX_LT_U64::Inst_VOPC__V_CMPX_LT_U64(InFmt_VOPC *iFmt)
6742 : Inst_VOPC(iFmt, "v_cmpx_lt_u64")
6743 {
6744 setFlag(ALU);
6745 setFlag(WritesEXEC);
6746 } // Inst_VOPC__V_CMPX_LT_U64
6747
6748 Inst_VOPC__V_CMPX_LT_U64::~Inst_VOPC__V_CMPX_LT_U64()
6749 {
6750 } // ~Inst_VOPC__V_CMPX_LT_U64
6751
6752 // --- description from .arch file ---
6753 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
6754 void
6755 Inst_VOPC__V_CMPX_LT_U64::execute(GPUDynInstPtr gpuDynInst)
6756 {
6757 Wavefront *wf = gpuDynInst->wavefront();
6758 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6759 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6760 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6761
6762 src0.readSrc();
6763 src1.read();
6764
6765 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6766 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6767
6768 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6769 if (wf->execMask(lane)) {
6770 vcc.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
6771 }
6772 }
6773
6774 wf->execMask() = vcc.rawData();
6775 vcc.write();
6776 } // execute
6777 // --- Inst_VOPC__V_CMPX_EQ_U64 class methods ---
6778
6779 Inst_VOPC__V_CMPX_EQ_U64::Inst_VOPC__V_CMPX_EQ_U64(InFmt_VOPC *iFmt)
6780 : Inst_VOPC(iFmt, "v_cmpx_eq_u64")
6781 {
6782 setFlag(ALU);
6783 setFlag(WritesEXEC);
6784 } // Inst_VOPC__V_CMPX_EQ_U64
6785
6786 Inst_VOPC__V_CMPX_EQ_U64::~Inst_VOPC__V_CMPX_EQ_U64()
6787 {
6788 } // ~Inst_VOPC__V_CMPX_EQ_U64
6789
6790 // --- description from .arch file ---
6791 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
6792 void
6793 Inst_VOPC__V_CMPX_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
6794 {
6795 Wavefront *wf = gpuDynInst->wavefront();
6796 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6797 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6798 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6799
6800 src0.readSrc();
6801 src1.read();
6802
6803 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6804 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6805
6806 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6807 if (wf->execMask(lane)) {
6808 vcc.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
6809 }
6810 }
6811
6812 wf->execMask() = vcc.rawData();
6813 vcc.write();
6814 } // execute
6815 // --- Inst_VOPC__V_CMPX_LE_U64 class methods ---
6816
6817 Inst_VOPC__V_CMPX_LE_U64::Inst_VOPC__V_CMPX_LE_U64(InFmt_VOPC *iFmt)
6818 : Inst_VOPC(iFmt, "v_cmpx_le_u64")
6819 {
6820 setFlag(ALU);
6821 setFlag(WritesEXEC);
6822 } // Inst_VOPC__V_CMPX_LE_U64
6823
6824 Inst_VOPC__V_CMPX_LE_U64::~Inst_VOPC__V_CMPX_LE_U64()
6825 {
6826 } // ~Inst_VOPC__V_CMPX_LE_U64
6827
6828 // --- description from .arch file ---
6829 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
6830 void
6831 Inst_VOPC__V_CMPX_LE_U64::execute(GPUDynInstPtr gpuDynInst)
6832 {
6833 Wavefront *wf = gpuDynInst->wavefront();
6834 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6835 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6836 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6837
6838 src0.readSrc();
6839 src1.read();
6840
6841 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6842 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6843
6844 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6845 if (wf->execMask(lane)) {
6846 vcc.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6847 }
6848 }
6849
6850 wf->execMask() = vcc.rawData();
6851 vcc.write();
6852 } // execute
6853 // --- Inst_VOPC__V_CMPX_GT_U64 class methods ---
6854
6855 Inst_VOPC__V_CMPX_GT_U64::Inst_VOPC__V_CMPX_GT_U64(InFmt_VOPC *iFmt)
6856 : Inst_VOPC(iFmt, "v_cmpx_gt_u64")
6857 {
6858 setFlag(ALU);
6859 setFlag(WritesEXEC);
6860 } // Inst_VOPC__V_CMPX_GT_U64
6861
6862 Inst_VOPC__V_CMPX_GT_U64::~Inst_VOPC__V_CMPX_GT_U64()
6863 {
6864 } // ~Inst_VOPC__V_CMPX_GT_U64
6865
6866 // --- description from .arch file ---
6867 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6868 void
6869 Inst_VOPC__V_CMPX_GT_U64::execute(GPUDynInstPtr gpuDynInst)
6870 {
6871 Wavefront *wf = gpuDynInst->wavefront();
6872 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6873 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6874 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6875
6876 src0.readSrc();
6877 src1.read();
6878
6879 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6880 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6881
6882 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6883 if (wf->execMask(lane)) {
6884 vcc.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6885 }
6886 }
6887
6888 wf->execMask() = vcc.rawData();
6889 vcc.write();
6890 } // execute
6891 // --- Inst_VOPC__V_CMPX_NE_U64 class methods ---
6892
6893 Inst_VOPC__V_CMPX_NE_U64::Inst_VOPC__V_CMPX_NE_U64(InFmt_VOPC *iFmt)
6894 : Inst_VOPC(iFmt, "v_cmpx_ne_u64")
6895 {
6896 setFlag(ALU);
6897 setFlag(WritesEXEC);
6898 } // Inst_VOPC__V_CMPX_NE_U64
6899
6900 Inst_VOPC__V_CMPX_NE_U64::~Inst_VOPC__V_CMPX_NE_U64()
6901 {
6902 } // ~Inst_VOPC__V_CMPX_NE_U64
6903
6904 // --- description from .arch file ---
6905 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6906 void
6907 Inst_VOPC__V_CMPX_NE_U64::execute(GPUDynInstPtr gpuDynInst)
6908 {
6909 Wavefront *wf = gpuDynInst->wavefront();
6910 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6911 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6912 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6913
6914 src0.readSrc();
6915 src1.read();
6916
6917 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6918 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6919
6920 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6921 if (wf->execMask(lane)) {
6922 vcc.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6923 }
6924 }
6925
6926 wf->execMask() = vcc.rawData();
6927 vcc.write();
6928 } // execute
6929 // --- Inst_VOPC__V_CMPX_GE_U64 class methods ---
6930
6931 Inst_VOPC__V_CMPX_GE_U64::Inst_VOPC__V_CMPX_GE_U64(InFmt_VOPC *iFmt)
6932 : Inst_VOPC(iFmt, "v_cmpx_ge_u64")
6933 {
6934 setFlag(ALU);
6935 setFlag(WritesEXEC);
6936 } // Inst_VOPC__V_CMPX_GE_U64
6937
6938 Inst_VOPC__V_CMPX_GE_U64::~Inst_VOPC__V_CMPX_GE_U64()
6939 {
6940 } // ~Inst_VOPC__V_CMPX_GE_U64
6941
6942 // --- description from .arch file ---
6943 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6944 void
6945 Inst_VOPC__V_CMPX_GE_U64::execute(GPUDynInstPtr gpuDynInst)
6946 {
6947 Wavefront *wf = gpuDynInst->wavefront();
6948 ConstVecOperandU64 src0(gpuDynInst, instData.SRC0);
6949 ConstVecOperandU64 src1(gpuDynInst, instData.VSRC1);
6950 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6951
6952 src0.readSrc();
6953 src1.read();
6954
6955 panic_if(isSDWAInst(), "SDWA not supported for %s", _opcode);
6956 panic_if(isDPPInst(), "DPP not supported for %s", _opcode);
6957
6958 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6959 if (wf->execMask(lane)) {
6960 vcc.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6961 }
6962 }
6963
6964 wf->execMask() = vcc.rawData();
6965 vcc.write();
6966 } // execute
6967 // --- Inst_VOPC__V_CMPX_T_U64 class methods ---
6968
6969 Inst_VOPC__V_CMPX_T_U64::Inst_VOPC__V_CMPX_T_U64(InFmt_VOPC *iFmt)
6970 : Inst_VOPC(iFmt, "v_cmpx_t_u64")
6971 {
6972 setFlag(ALU);
6973 setFlag(WritesEXEC);
6974 } // Inst_VOPC__V_CMPX_T_U64
6975
6976 Inst_VOPC__V_CMPX_T_U64::~Inst_VOPC__V_CMPX_T_U64()
6977 {
6978 } // ~Inst_VOPC__V_CMPX_T_U64
6979
6980 // --- description from .arch file ---
6981 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
6982 void
6983 Inst_VOPC__V_CMPX_T_U64::execute(GPUDynInstPtr gpuDynInst)
6984 {
6985 Wavefront *wf = gpuDynInst->wavefront();
6986 ScalarOperandU64 vcc(gpuDynInst, REG_VCC_LO);
6987
6988 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6989 if (wf->execMask(lane)) {
6990 vcc.setBit(lane, 1);
6991 }
6992 }
6993
6994 wf->execMask() = vcc.rawData();
6995 vcc.write();
6996 } // execute
6997} // namespace VegaISA
6998} // namespace gem5
gem5::GPUStaticInst::setFlag
void setFlag(Flags flag)
Definition gpu_static_inst.hh:250
gem5::GPUStaticInst::_opcode
const std::string _opcode
Definition gpu_static_inst.hh:304
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16::~Inst_VOPC__V_CMPX_CLASS_F16
~Inst_VOPC__V_CMPX_CLASS_F16()
Definition vopc.cc:555
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16::Inst_VOPC__V_CMPX_CLASS_F16
Inst_VOPC__V_CMPX_CLASS_F16(InFmt_VOPC *)
Definition vopc.cc:547
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:575
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32::Inst_VOPC__V_CMPX_CLASS_F32
Inst_VOPC__V_CMPX_CLASS_F32(InFmt_VOPC *)
Definition vopc.cc:158
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:185
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32::~Inst_VOPC__V_CMPX_CLASS_F32
~Inst_VOPC__V_CMPX_CLASS_F32()
Definition vopc.cc:166
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64::Inst_VOPC__V_CMPX_CLASS_F64
Inst_VOPC__V_CMPX_CLASS_F64(InFmt_VOPC *)
Definition vopc.cc:395
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64::~Inst_VOPC__V_CMPX_CLASS_F64
~Inst_VOPC__V_CMPX_CLASS_F64()
Definition vopc.cc:403
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:422
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16::~Inst_VOPC__V_CMPX_EQ_F16
~Inst_VOPC__V_CMPX_EQ_F16()
Definition vopc.cc:951
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16::Inst_VOPC__V_CMPX_EQ_F16
Inst_VOPC__V_CMPX_EQ_F16(InFmt_VOPC *)
Definition vopc.cc:943
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:958
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32::~Inst_VOPC__V_CMPX_EQ_F32
~Inst_VOPC__V_CMPX_EQ_F32()
Definition vopc.cc:1897
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1904
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32::Inst_VOPC__V_CMPX_EQ_F32
Inst_VOPC__V_CMPX_EQ_F32(InFmt_VOPC *)
Definition vopc.cc:1889
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3098
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64::~Inst_VOPC__V_CMPX_EQ_F64
~Inst_VOPC__V_CMPX_EQ_F64()
Definition vopc.cc:3091
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64::Inst_VOPC__V_CMPX_EQ_F64
Inst_VOPC__V_CMPX_EQ_F64(InFmt_VOPC *)
Definition vopc.cc:3083
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4265
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16::~Inst_VOPC__V_CMPX_EQ_I16
~Inst_VOPC__V_CMPX_EQ_I16()
Definition vopc.cc:4258
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16::Inst_VOPC__V_CMPX_EQ_I16
Inst_VOPC__V_CMPX_EQ_I16(InFmt_VOPC *)
Definition vopc.cc:4251
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32::~Inst_VOPC__V_CMPX_EQ_I32
~Inst_VOPC__V_CMPX_EQ_I32()
Definition vopc.cc:5378
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5385
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32::Inst_VOPC__V_CMPX_EQ_I32
Inst_VOPC__V_CMPX_EQ_I32(InFmt_VOPC *)
Definition vopc.cc:5371
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64::Inst_VOPC__V_CMPX_EQ_I64
Inst_VOPC__V_CMPX_EQ_I64(InFmt_VOPC *)
Definition vopc.cc:6491
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6505
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64::~Inst_VOPC__V_CMPX_EQ_I64
~Inst_VOPC__V_CMPX_EQ_I64()
Definition vopc.cc:6498
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16::Inst_VOPC__V_CMPX_EQ_U16
Inst_VOPC__V_CMPX_EQ_U16(InFmt_VOPC *)
Definition vopc.cc:4539
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16::~Inst_VOPC__V_CMPX_EQ_U16
~Inst_VOPC__V_CMPX_EQ_U16()
Definition vopc.cc:4546
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4553
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5673
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32::~Inst_VOPC__V_CMPX_EQ_U32
~Inst_VOPC__V_CMPX_EQ_U32()
Definition vopc.cc:5666
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32::Inst_VOPC__V_CMPX_EQ_U32
Inst_VOPC__V_CMPX_EQ_U32(InFmt_VOPC *)
Definition vopc.cc:5659
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64::~Inst_VOPC__V_CMPX_EQ_U64
~Inst_VOPC__V_CMPX_EQ_U64()
Definition vopc.cc:6786
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6793
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64::Inst_VOPC__V_CMPX_EQ_U64
Inst_VOPC__V_CMPX_EQ_U64(InFmt_VOPC *)
Definition vopc.cc:6779
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16::~Inst_VOPC__V_CMPX_F_F16
~Inst_VOPC__V_CMPX_F_F16()
Definition vopc.cc:909
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16::Inst_VOPC__V_CMPX_F_F16
Inst_VOPC__V_CMPX_F_F16(InFmt_VOPC *)
Definition vopc.cc:901
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:916
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32::Inst_VOPC__V_CMPX_F_F32
Inst_VOPC__V_CMPX_F_F32(InFmt_VOPC *)
Definition vopc.cc:1819
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32::~Inst_VOPC__V_CMPX_F_F32
~Inst_VOPC__V_CMPX_F_F32()
Definition vopc.cc:1827
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1834
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3028
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64::~Inst_VOPC__V_CMPX_F_F64
~Inst_VOPC__V_CMPX_F_F64()
Definition vopc.cc:3021
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64::Inst_VOPC__V_CMPX_F_F64
Inst_VOPC__V_CMPX_F_F64(InFmt_VOPC *)
Definition vopc.cc:3013
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16::~Inst_VOPC__V_CMPX_F_I16
~Inst_VOPC__V_CMPX_F_I16()
Definition vopc.cc:4190
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16::Inst_VOPC__V_CMPX_F_I16
Inst_VOPC__V_CMPX_F_I16(InFmt_VOPC *)
Definition vopc.cc:4183
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4197
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32::~Inst_VOPC__V_CMPX_F_I32
~Inst_VOPC__V_CMPX_F_I32()
Definition vopc.cc:5310
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5317
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32::Inst_VOPC__V_CMPX_F_I32
Inst_VOPC__V_CMPX_F_I32(InFmt_VOPC *)
Definition vopc.cc:5303
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6437
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64::~Inst_VOPC__V_CMPX_F_I64
~Inst_VOPC__V_CMPX_F_I64()
Definition vopc.cc:6430
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64::Inst_VOPC__V_CMPX_F_I64
Inst_VOPC__V_CMPX_F_I64(InFmt_VOPC *)
Definition vopc.cc:6423
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16::~Inst_VOPC__V_CMPX_F_U16
~Inst_VOPC__V_CMPX_F_U16()
Definition vopc.cc:4478
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16::Inst_VOPC__V_CMPX_F_U16
Inst_VOPC__V_CMPX_F_U16(InFmt_VOPC *)
Definition vopc.cc:4471
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4485
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32::Inst_VOPC__V_CMPX_F_U32
Inst_VOPC__V_CMPX_F_U32(InFmt_VOPC *)
Definition vopc.cc:5591
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32::~Inst_VOPC__V_CMPX_F_U32
~Inst_VOPC__V_CMPX_F_U32()
Definition vopc.cc:5598
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5605
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64::~Inst_VOPC__V_CMPX_F_U64
~Inst_VOPC__V_CMPX_F_U64()
Definition vopc.cc:6718
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64::Inst_VOPC__V_CMPX_F_U64
Inst_VOPC__V_CMPX_F_U64(InFmt_VOPC *)
Definition vopc.cc:6711
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6725
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1042
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16::Inst_VOPC__V_CMPX_GE_F16
Inst_VOPC__V_CMPX_GE_F16(InFmt_VOPC *)
Definition vopc.cc:1027
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16::~Inst_VOPC__V_CMPX_GE_F16
~Inst_VOPC__V_CMPX_GE_F16()
Definition vopc.cc:1035
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32::~Inst_VOPC__V_CMPX_GE_F32
~Inst_VOPC__V_CMPX_GE_F32()
Definition vopc.cc:2054
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2061
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32::Inst_VOPC__V_CMPX_GE_F32
Inst_VOPC__V_CMPX_GE_F32(InFmt_VOPC *)
Definition vopc.cc:2046
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64::Inst_VOPC__V_CMPX_GE_F64
Inst_VOPC__V_CMPX_GE_F64(InFmt_VOPC *)
Definition vopc.cc:3240
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3255
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64::~Inst_VOPC__V_CMPX_GE_F64
~Inst_VOPC__V_CMPX_GE_F64()
Definition vopc.cc:3248
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16::Inst_VOPC__V_CMPX_GE_I16
Inst_VOPC__V_CMPX_GE_I16(InFmt_VOPC *)
Definition vopc.cc:4403
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4417
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16::~Inst_VOPC__V_CMPX_GE_I16
~Inst_VOPC__V_CMPX_GE_I16()
Definition vopc.cc:4410
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5537
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32::~Inst_VOPC__V_CMPX_GE_I32
~Inst_VOPC__V_CMPX_GE_I32()
Definition vopc.cc:5530
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32::Inst_VOPC__V_CMPX_GE_I32
Inst_VOPC__V_CMPX_GE_I32(InFmt_VOPC *)
Definition vopc.cc:5523
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64::~Inst_VOPC__V_CMPX_GE_I64
~Inst_VOPC__V_CMPX_GE_I64()
Definition vopc.cc:6650
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6657
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64::Inst_VOPC__V_CMPX_GE_I64
Inst_VOPC__V_CMPX_GE_I64(InFmt_VOPC *)
Definition vopc.cc:6643
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4705
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16::~Inst_VOPC__V_CMPX_GE_U16
~Inst_VOPC__V_CMPX_GE_U16()
Definition vopc.cc:4698
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16::Inst_VOPC__V_CMPX_GE_U16
Inst_VOPC__V_CMPX_GE_U16(InFmt_VOPC *)
Definition vopc.cc:4691
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32::~Inst_VOPC__V_CMPX_GE_U32
~Inst_VOPC__V_CMPX_GE_U32()
Definition vopc.cc:5818
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5825
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32::Inst_VOPC__V_CMPX_GE_U32
Inst_VOPC__V_CMPX_GE_U32(InFmt_VOPC *)
Definition vopc.cc:5811
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6945
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64::~Inst_VOPC__V_CMPX_GE_U64
~Inst_VOPC__V_CMPX_GE_U64()
Definition vopc.cc:6938
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64::Inst_VOPC__V_CMPX_GE_U64
Inst_VOPC__V_CMPX_GE_U64(InFmt_VOPC *)
Definition vopc.cc:6931
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16::Inst_VOPC__V_CMPX_GT_F16
Inst_VOPC__V_CMPX_GT_F16(InFmt_VOPC *)
Definition vopc.cc:985
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1000
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16::~Inst_VOPC__V_CMPX_GT_F16
~Inst_VOPC__V_CMPX_GT_F16()
Definition vopc.cc:993
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1982
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32::Inst_VOPC__V_CMPX_GT_F32
Inst_VOPC__V_CMPX_GT_F32(InFmt_VOPC *)
Definition vopc.cc:1967
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32::~Inst_VOPC__V_CMPX_GT_F32
~Inst_VOPC__V_CMPX_GT_F32()
Definition vopc.cc:1975
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64::~Inst_VOPC__V_CMPX_GT_F64
~Inst_VOPC__V_CMPX_GT_F64()
Definition vopc.cc:3169
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64::Inst_VOPC__V_CMPX_GT_F64
Inst_VOPC__V_CMPX_GT_F64(InFmt_VOPC *)
Definition vopc.cc:3161
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3176
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16::~Inst_VOPC__V_CMPX_GT_I16
~Inst_VOPC__V_CMPX_GT_I16()
Definition vopc.cc:4334
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4341
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16::Inst_VOPC__V_CMPX_GT_I16
Inst_VOPC__V_CMPX_GT_I16(InFmt_VOPC *)
Definition vopc.cc:4327
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5461
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32::~Inst_VOPC__V_CMPX_GT_I32
~Inst_VOPC__V_CMPX_GT_I32()
Definition vopc.cc:5454
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32::Inst_VOPC__V_CMPX_GT_I32
Inst_VOPC__V_CMPX_GT_I32(InFmt_VOPC *)
Definition vopc.cc:5447
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64::Inst_VOPC__V_CMPX_GT_I64
Inst_VOPC__V_CMPX_GT_I64(InFmt_VOPC *)
Definition vopc.cc:6567
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64::~Inst_VOPC__V_CMPX_GT_I64
~Inst_VOPC__V_CMPX_GT_I64()
Definition vopc.cc:6574
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6581
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4629
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16::~Inst_VOPC__V_CMPX_GT_U16
~Inst_VOPC__V_CMPX_GT_U16()
Definition vopc.cc:4622
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16::Inst_VOPC__V_CMPX_GT_U16
Inst_VOPC__V_CMPX_GT_U16(InFmt_VOPC *)
Definition vopc.cc:4615
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5749
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32::~Inst_VOPC__V_CMPX_GT_U32
~Inst_VOPC__V_CMPX_GT_U32()
Definition vopc.cc:5742
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32::Inst_VOPC__V_CMPX_GT_U32
Inst_VOPC__V_CMPX_GT_U32(InFmt_VOPC *)
Definition vopc.cc:5735
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64::Inst_VOPC__V_CMPX_GT_U64
Inst_VOPC__V_CMPX_GT_U64(InFmt_VOPC *)
Definition vopc.cc:6855
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64::~Inst_VOPC__V_CMPX_GT_U64
~Inst_VOPC__V_CMPX_GT_U64()
Definition vopc.cc:6862
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6869
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:979
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16::Inst_VOPC__V_CMPX_LE_F16
Inst_VOPC__V_CMPX_LE_F16(InFmt_VOPC *)
Definition vopc.cc:964
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16::~Inst_VOPC__V_CMPX_LE_F16
~Inst_VOPC__V_CMPX_LE_F16()
Definition vopc.cc:972
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32::Inst_VOPC__V_CMPX_LE_F32
Inst_VOPC__V_CMPX_LE_F32(InFmt_VOPC *)
Definition vopc.cc:1928
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1943
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32::~Inst_VOPC__V_CMPX_LE_F32
~Inst_VOPC__V_CMPX_LE_F32()
Definition vopc.cc:1936
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3137
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64::Inst_VOPC__V_CMPX_LE_F64
Inst_VOPC__V_CMPX_LE_F64(InFmt_VOPC *)
Definition vopc.cc:3122
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64::~Inst_VOPC__V_CMPX_LE_F64
~Inst_VOPC__V_CMPX_LE_F64()
Definition vopc.cc:3130
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16::Inst_VOPC__V_CMPX_LE_I16
Inst_VOPC__V_CMPX_LE_I16(InFmt_VOPC *)
Definition vopc.cc:4289
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4303
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16::~Inst_VOPC__V_CMPX_LE_I16
~Inst_VOPC__V_CMPX_LE_I16()
Definition vopc.cc:4296
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32::~Inst_VOPC__V_CMPX_LE_I32
~Inst_VOPC__V_CMPX_LE_I32()
Definition vopc.cc:5416
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5423
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32::Inst_VOPC__V_CMPX_LE_I32
Inst_VOPC__V_CMPX_LE_I32(InFmt_VOPC *)
Definition vopc.cc:5409
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64::~Inst_VOPC__V_CMPX_LE_I64
~Inst_VOPC__V_CMPX_LE_I64()
Definition vopc.cc:6536
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64::Inst_VOPC__V_CMPX_LE_I64
Inst_VOPC__V_CMPX_LE_I64(InFmt_VOPC *)
Definition vopc.cc:6529
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6543
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16::~Inst_VOPC__V_CMPX_LE_U16
~Inst_VOPC__V_CMPX_LE_U16()
Definition vopc.cc:4584
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16::Inst_VOPC__V_CMPX_LE_U16
Inst_VOPC__V_CMPX_LE_U16(InFmt_VOPC *)
Definition vopc.cc:4577
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4591
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5711
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32::~Inst_VOPC__V_CMPX_LE_U32
~Inst_VOPC__V_CMPX_LE_U32()
Definition vopc.cc:5704
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32::Inst_VOPC__V_CMPX_LE_U32
Inst_VOPC__V_CMPX_LE_U32(InFmt_VOPC *)
Definition vopc.cc:5697
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64::~Inst_VOPC__V_CMPX_LE_U64
~Inst_VOPC__V_CMPX_LE_U64()
Definition vopc.cc:6824
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6831
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64::Inst_VOPC__V_CMPX_LE_U64
Inst_VOPC__V_CMPX_LE_U64(InFmt_VOPC *)
Definition vopc.cc:6817
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16::Inst_VOPC__V_CMPX_LG_F16
Inst_VOPC__V_CMPX_LG_F16(InFmt_VOPC *)
Definition vopc.cc:1006
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16::~Inst_VOPC__V_CMPX_LG_F16
~Inst_VOPC__V_CMPX_LG_F16()
Definition vopc.cc:1014
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1021
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32::~Inst_VOPC__V_CMPX_LG_F32
~Inst_VOPC__V_CMPX_LG_F32()
Definition vopc.cc:2014
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2021
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32::Inst_VOPC__V_CMPX_LG_F32
Inst_VOPC__V_CMPX_LG_F32(InFmt_VOPC *)
Definition vopc.cc:2006
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3215
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64::Inst_VOPC__V_CMPX_LG_F64
Inst_VOPC__V_CMPX_LG_F64(InFmt_VOPC *)
Definition vopc.cc:3200
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64::~Inst_VOPC__V_CMPX_LG_F64
~Inst_VOPC__V_CMPX_LG_F64()
Definition vopc.cc:3208
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16::Inst_VOPC__V_CMPX_LT_F16
Inst_VOPC__V_CMPX_LT_F16(InFmt_VOPC *)
Definition vopc.cc:922
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16::~Inst_VOPC__V_CMPX_LT_F16
~Inst_VOPC__V_CMPX_LT_F16()
Definition vopc.cc:930
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:937
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32::~Inst_VOPC__V_CMPX_LT_F32
~Inst_VOPC__V_CMPX_LT_F32()
Definition vopc.cc:1858
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1865
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32::Inst_VOPC__V_CMPX_LT_F32
Inst_VOPC__V_CMPX_LT_F32(InFmt_VOPC *)
Definition vopc.cc:1850
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64::Inst_VOPC__V_CMPX_LT_F64
Inst_VOPC__V_CMPX_LT_F64(InFmt_VOPC *)
Definition vopc.cc:3044
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64::~Inst_VOPC__V_CMPX_LT_F64
~Inst_VOPC__V_CMPX_LT_F64()
Definition vopc.cc:3052
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3059
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4227
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16::Inst_VOPC__V_CMPX_LT_I16
Inst_VOPC__V_CMPX_LT_I16(InFmt_VOPC *)
Definition vopc.cc:4213
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16::~Inst_VOPC__V_CMPX_LT_I16
~Inst_VOPC__V_CMPX_LT_I16()
Definition vopc.cc:4220
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5347
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32::Inst_VOPC__V_CMPX_LT_I32
Inst_VOPC__V_CMPX_LT_I32(InFmt_VOPC *)
Definition vopc.cc:5333
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32::~Inst_VOPC__V_CMPX_LT_I32
~Inst_VOPC__V_CMPX_LT_I32()
Definition vopc.cc:5340
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64::~Inst_VOPC__V_CMPX_LT_I64
~Inst_VOPC__V_CMPX_LT_I64()
Definition vopc.cc:6460
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64::Inst_VOPC__V_CMPX_LT_I64
Inst_VOPC__V_CMPX_LT_I64(InFmt_VOPC *)
Definition vopc.cc:6453
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6467
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4515
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16::~Inst_VOPC__V_CMPX_LT_U16
~Inst_VOPC__V_CMPX_LT_U16()
Definition vopc.cc:4508
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16::Inst_VOPC__V_CMPX_LT_U16
Inst_VOPC__V_CMPX_LT_U16(InFmt_VOPC *)
Definition vopc.cc:4501
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5635
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32::Inst_VOPC__V_CMPX_LT_U32
Inst_VOPC__V_CMPX_LT_U32(InFmt_VOPC *)
Definition vopc.cc:5621
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32::~Inst_VOPC__V_CMPX_LT_U32
~Inst_VOPC__V_CMPX_LT_U32()
Definition vopc.cc:5628
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64::~Inst_VOPC__V_CMPX_LT_U64
~Inst_VOPC__V_CMPX_LT_U64()
Definition vopc.cc:6748
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6755
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64::Inst_VOPC__V_CMPX_LT_U64
Inst_VOPC__V_CMPX_LT_U64(InFmt_VOPC *)
Definition vopc.cc:6741
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16::~Inst_VOPC__V_CMPX_NEQ_F16
~Inst_VOPC__V_CMPX_NEQ_F16()
Definition vopc.cc:1184
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1191
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16::Inst_VOPC__V_CMPX_NEQ_F16
Inst_VOPC__V_CMPX_NEQ_F16(InFmt_VOPC *)
Definition vopc.cc:1176
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2339
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32::Inst_VOPC__V_CMPX_NEQ_F32
Inst_VOPC__V_CMPX_NEQ_F32(InFmt_VOPC *)
Definition vopc.cc:2324
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32::~Inst_VOPC__V_CMPX_NEQ_F32
~Inst_VOPC__V_CMPX_NEQ_F32()
Definition vopc.cc:2332
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64::Inst_VOPC__V_CMPX_NEQ_F64
Inst_VOPC__V_CMPX_NEQ_F64(InFmt_VOPC *)
Definition vopc.cc:3518
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64::~Inst_VOPC__V_CMPX_NEQ_F64
~Inst_VOPC__V_CMPX_NEQ_F64()
Definition vopc.cc:3526
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3533
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4379
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16::Inst_VOPC__V_CMPX_NE_I16
Inst_VOPC__V_CMPX_NE_I16(InFmt_VOPC *)
Definition vopc.cc:4365
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16::~Inst_VOPC__V_CMPX_NE_I16
~Inst_VOPC__V_CMPX_NE_I16()
Definition vopc.cc:4372
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32::Inst_VOPC__V_CMPX_NE_I32
Inst_VOPC__V_CMPX_NE_I32(InFmt_VOPC *)
Definition vopc.cc:5485
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32::~Inst_VOPC__V_CMPX_NE_I32
~Inst_VOPC__V_CMPX_NE_I32()
Definition vopc.cc:5492
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5499
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64::~Inst_VOPC__V_CMPX_NE_I64
~Inst_VOPC__V_CMPX_NE_I64()
Definition vopc.cc:6612
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6619
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64::Inst_VOPC__V_CMPX_NE_I64
Inst_VOPC__V_CMPX_NE_I64(InFmt_VOPC *)
Definition vopc.cc:6605
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4667
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16::~Inst_VOPC__V_CMPX_NE_U16
~Inst_VOPC__V_CMPX_NE_U16()
Definition vopc.cc:4660
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16::Inst_VOPC__V_CMPX_NE_U16
Inst_VOPC__V_CMPX_NE_U16(InFmt_VOPC *)
Definition vopc.cc:4653
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32::~Inst_VOPC__V_CMPX_NE_U32
~Inst_VOPC__V_CMPX_NE_U32()
Definition vopc.cc:5780
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5787
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32::Inst_VOPC__V_CMPX_NE_U32
Inst_VOPC__V_CMPX_NE_U32(InFmt_VOPC *)
Definition vopc.cc:5773
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64::Inst_VOPC__V_CMPX_NE_U64
Inst_VOPC__V_CMPX_NE_U64(InFmt_VOPC *)
Definition vopc.cc:6893
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6907
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64::~Inst_VOPC__V_CMPX_NE_U64
~Inst_VOPC__V_CMPX_NE_U64()
Definition vopc.cc:6900
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16::~Inst_VOPC__V_CMPX_NGE_F16
~Inst_VOPC__V_CMPX_NGE_F16()
Definition vopc.cc:1100
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16::Inst_VOPC__V_CMPX_NGE_F16
Inst_VOPC__V_CMPX_NGE_F16(InFmt_VOPC *)
Definition vopc.cc:1092
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1107
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32::Inst_VOPC__V_CMPX_NGE_F32
Inst_VOPC__V_CMPX_NGE_F32(InFmt_VOPC *)
Definition vopc.cc:2167
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32::~Inst_VOPC__V_CMPX_NGE_F32
~Inst_VOPC__V_CMPX_NGE_F32()
Definition vopc.cc:2175
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2182
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3376
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64::Inst_VOPC__V_CMPX_NGE_F64
Inst_VOPC__V_CMPX_NGE_F64(InFmt_VOPC *)
Definition vopc.cc:3361
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64::~Inst_VOPC__V_CMPX_NGE_F64
~Inst_VOPC__V_CMPX_NGE_F64()
Definition vopc.cc:3369
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1149
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16::Inst_VOPC__V_CMPX_NGT_F16
Inst_VOPC__V_CMPX_NGT_F16(InFmt_VOPC *)
Definition vopc.cc:1134
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16::~Inst_VOPC__V_CMPX_NGT_F16
~Inst_VOPC__V_CMPX_NGT_F16()
Definition vopc.cc:1142
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32::~Inst_VOPC__V_CMPX_NGT_F32
~Inst_VOPC__V_CMPX_NGT_F32()
Definition vopc.cc:2254
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2261
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32::Inst_VOPC__V_CMPX_NGT_F32
Inst_VOPC__V_CMPX_NGT_F32(InFmt_VOPC *)
Definition vopc.cc:2246
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3455
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64::~Inst_VOPC__V_CMPX_NGT_F64
~Inst_VOPC__V_CMPX_NGT_F64()
Definition vopc.cc:3448
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64::Inst_VOPC__V_CMPX_NGT_F64
Inst_VOPC__V_CMPX_NGT_F64(InFmt_VOPC *)
Definition vopc.cc:3440
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1170
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16::Inst_VOPC__V_CMPX_NLE_F16
Inst_VOPC__V_CMPX_NLE_F16(InFmt_VOPC *)
Definition vopc.cc:1155
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16::~Inst_VOPC__V_CMPX_NLE_F16
~Inst_VOPC__V_CMPX_NLE_F16()
Definition vopc.cc:1163
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32::Inst_VOPC__V_CMPX_NLE_F32
Inst_VOPC__V_CMPX_NLE_F32(InFmt_VOPC *)
Definition vopc.cc:2285
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32::~Inst_VOPC__V_CMPX_NLE_F32
~Inst_VOPC__V_CMPX_NLE_F32()
Definition vopc.cc:2293
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2300
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64::~Inst_VOPC__V_CMPX_NLE_F64
~Inst_VOPC__V_CMPX_NLE_F64()
Definition vopc.cc:3487
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64::Inst_VOPC__V_CMPX_NLE_F64
Inst_VOPC__V_CMPX_NLE_F64(InFmt_VOPC *)
Definition vopc.cc:3479
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3494
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1128
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16::~Inst_VOPC__V_CMPX_NLG_F16
~Inst_VOPC__V_CMPX_NLG_F16()
Definition vopc.cc:1121
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16::Inst_VOPC__V_CMPX_NLG_F16
Inst_VOPC__V_CMPX_NLG_F16(InFmt_VOPC *)
Definition vopc.cc:1113
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32::Inst_VOPC__V_CMPX_NLG_F32
Inst_VOPC__V_CMPX_NLG_F32(InFmt_VOPC *)
Definition vopc.cc:2206
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32::~Inst_VOPC__V_CMPX_NLG_F32
~Inst_VOPC__V_CMPX_NLG_F32()
Definition vopc.cc:2214
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2221
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3415
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64::~Inst_VOPC__V_CMPX_NLG_F64
~Inst_VOPC__V_CMPX_NLG_F64()
Definition vopc.cc:3408
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64::Inst_VOPC__V_CMPX_NLG_F64
Inst_VOPC__V_CMPX_NLG_F64(InFmt_VOPC *)
Definition vopc.cc:3400
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16::Inst_VOPC__V_CMPX_NLT_F16
Inst_VOPC__V_CMPX_NLT_F16(InFmt_VOPC *)
Definition vopc.cc:1197
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1212
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16::~Inst_VOPC__V_CMPX_NLT_F16
~Inst_VOPC__V_CMPX_NLT_F16()
Definition vopc.cc:1205
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2378
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32::Inst_VOPC__V_CMPX_NLT_F32
Inst_VOPC__V_CMPX_NLT_F32(InFmt_VOPC *)
Definition vopc.cc:2363
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32::~Inst_VOPC__V_CMPX_NLT_F32
~Inst_VOPC__V_CMPX_NLT_F32()
Definition vopc.cc:2371
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64::Inst_VOPC__V_CMPX_NLT_F64
Inst_VOPC__V_CMPX_NLT_F64(InFmt_VOPC *)
Definition vopc.cc:3557
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3572
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64::~Inst_VOPC__V_CMPX_NLT_F64
~Inst_VOPC__V_CMPX_NLT_F64()
Definition vopc.cc:3565
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1064
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16::Inst_VOPC__V_CMPX_O_F16
Inst_VOPC__V_CMPX_O_F16(InFmt_VOPC *)
Definition vopc.cc:1048
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16::~Inst_VOPC__V_CMPX_O_F16
~Inst_VOPC__V_CMPX_O_F16()
Definition vopc.cc:1056
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2101
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32::Inst_VOPC__V_CMPX_O_F32
Inst_VOPC__V_CMPX_O_F32(InFmt_VOPC *)
Definition vopc.cc:2085
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32::~Inst_VOPC__V_CMPX_O_F32
~Inst_VOPC__V_CMPX_O_F32()
Definition vopc.cc:2093
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3295
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64::~Inst_VOPC__V_CMPX_O_F64
~Inst_VOPC__V_CMPX_O_F64()
Definition vopc.cc:3287
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64::Inst_VOPC__V_CMPX_O_F64
Inst_VOPC__V_CMPX_O_F64(InFmt_VOPC *)
Definition vopc.cc:3279
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16::Inst_VOPC__V_CMPX_TRU_F16
Inst_VOPC__V_CMPX_TRU_F16(InFmt_VOPC *)
Definition vopc.cc:1218
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16::~Inst_VOPC__V_CMPX_TRU_F16
~Inst_VOPC__V_CMPX_TRU_F16()
Definition vopc.cc:1226
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1233
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32::~Inst_VOPC__V_CMPX_TRU_F32
~Inst_VOPC__V_CMPX_TRU_F32()
Definition vopc.cc:2410
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2417
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32::Inst_VOPC__V_CMPX_TRU_F32
Inst_VOPC__V_CMPX_TRU_F32(InFmt_VOPC *)
Definition vopc.cc:2402
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3611
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64::Inst_VOPC__V_CMPX_TRU_F64
Inst_VOPC__V_CMPX_TRU_F64(InFmt_VOPC *)
Definition vopc.cc:3596
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64::~Inst_VOPC__V_CMPX_TRU_F64
~Inst_VOPC__V_CMPX_TRU_F64()
Definition vopc.cc:3604
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16::Inst_VOPC__V_CMPX_T_I16
Inst_VOPC__V_CMPX_T_I16(InFmt_VOPC *)
Definition vopc.cc:4441
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16::~Inst_VOPC__V_CMPX_T_I16
~Inst_VOPC__V_CMPX_T_I16()
Definition vopc.cc:4448
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4455
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32::~Inst_VOPC__V_CMPX_T_I32
~Inst_VOPC__V_CMPX_T_I32()
Definition vopc.cc:5568
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32::Inst_VOPC__V_CMPX_T_I32
Inst_VOPC__V_CMPX_T_I32(InFmt_VOPC *)
Definition vopc.cc:5561
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5575
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6695
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64::~Inst_VOPC__V_CMPX_T_I64
~Inst_VOPC__V_CMPX_T_I64()
Definition vopc.cc:6688
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64::Inst_VOPC__V_CMPX_T_I64
Inst_VOPC__V_CMPX_T_I64(InFmt_VOPC *)
Definition vopc.cc:6681
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16::Inst_VOPC__V_CMPX_T_U16
Inst_VOPC__V_CMPX_T_U16(InFmt_VOPC *)
Definition vopc.cc:4729
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16::~Inst_VOPC__V_CMPX_T_U16
~Inst_VOPC__V_CMPX_T_U16()
Definition vopc.cc:4736
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4743
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5863
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32::~Inst_VOPC__V_CMPX_T_U32
~Inst_VOPC__V_CMPX_T_U32()
Definition vopc.cc:5856
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32::Inst_VOPC__V_CMPX_T_U32
Inst_VOPC__V_CMPX_T_U32(InFmt_VOPC *)
Definition vopc.cc:5849
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6983
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64::Inst_VOPC__V_CMPX_T_U64
Inst_VOPC__V_CMPX_T_U64(InFmt_VOPC *)
Definition vopc.cc:6969
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64::~Inst_VOPC__V_CMPX_T_U64
~Inst_VOPC__V_CMPX_T_U64()
Definition vopc.cc:6976
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16::Inst_VOPC__V_CMPX_U_F16
Inst_VOPC__V_CMPX_U_F16(InFmt_VOPC *)
Definition vopc.cc:1070
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16::~Inst_VOPC__V_CMPX_U_F16
~Inst_VOPC__V_CMPX_U_F16()
Definition vopc.cc:1078
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1086
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32::~Inst_VOPC__V_CMPX_U_F32
~Inst_VOPC__V_CMPX_U_F32()
Definition vopc.cc:2134
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2142
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32::Inst_VOPC__V_CMPX_U_F32
Inst_VOPC__V_CMPX_U_F32(InFmt_VOPC *)
Definition vopc.cc:2126
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3336
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64::Inst_VOPC__V_CMPX_U_F64
Inst_VOPC__V_CMPX_U_F64(InFmt_VOPC *)
Definition vopc.cc:3320
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64::~Inst_VOPC__V_CMPX_U_F64
~Inst_VOPC__V_CMPX_U_F64()
Definition vopc.cc:3328
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16::Inst_VOPC__V_CMP_CLASS_F16
Inst_VOPC__V_CMP_CLASS_F16(InFmt_VOPC *)
Definition vopc.cc:515
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16::~Inst_VOPC__V_CMP_CLASS_F16
~Inst_VOPC__V_CMP_CLASS_F16()
Definition vopc.cc:522
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:541
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:67
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32::~Inst_VOPC__V_CMP_CLASS_F32
~Inst_VOPC__V_CMP_CLASS_F32()
Definition vopc.cc:48
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32::Inst_VOPC__V_CMP_CLASS_F32
Inst_VOPC__V_CMP_CLASS_F32(InFmt_VOPC *)
Definition vopc.cc:41
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64::~Inst_VOPC__V_CMP_CLASS_F64
~Inst_VOPC__V_CMP_CLASS_F64()
Definition vopc.cc:284
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:303
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64::Inst_VOPC__V_CMP_CLASS_F64
Inst_VOPC__V_CMP_CLASS_F64(InFmt_VOPC *)
Definition vopc.cc:277
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16::Inst_VOPC__V_CMP_EQ_F16
Inst_VOPC__V_CMP_EQ_F16(InFmt_VOPC *)
Definition vopc.cc:621
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:635
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16::~Inst_VOPC__V_CMP_EQ_F16
~Inst_VOPC__V_CMP_EQ_F16()
Definition vopc.cc:628
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1319
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32::~Inst_VOPC__V_CMP_EQ_F32
~Inst_VOPC__V_CMP_EQ_F32()
Definition vopc.cc:1312
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32::Inst_VOPC__V_CMP_EQ_F32
Inst_VOPC__V_CMP_EQ_F32(InFmt_VOPC *)
Definition vopc.cc:1305
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64::~Inst_VOPC__V_CMP_EQ_F64
~Inst_VOPC__V_CMP_EQ_F64()
Definition vopc.cc:2506
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2513
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64::Inst_VOPC__V_CMP_EQ_F64
Inst_VOPC__V_CMP_EQ_F64(InFmt_VOPC *)
Definition vopc.cc:2499
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16::Inst_VOPC__V_CMP_EQ_I16
Inst_VOPC__V_CMP_EQ_I16(InFmt_VOPC *)
Definition vopc.cc:3691
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16::~Inst_VOPC__V_CMP_EQ_I16
~Inst_VOPC__V_CMP_EQ_I16()
Definition vopc.cc:3697
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3704
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4836
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32::Inst_VOPC__V_CMP_EQ_I32
Inst_VOPC__V_CMP_EQ_I32(InFmt_VOPC *)
Definition vopc.cc:4823
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32::~Inst_VOPC__V_CMP_EQ_I32
~Inst_VOPC__V_CMP_EQ_I32()
Definition vopc.cc:4829
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5956
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64::Inst_VOPC__V_CMP_EQ_I64
Inst_VOPC__V_CMP_EQ_I64(InFmt_VOPC *)
Definition vopc.cc:5943
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64::~Inst_VOPC__V_CMP_EQ_I64
~Inst_VOPC__V_CMP_EQ_I64()
Definition vopc.cc:5949
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3976
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16::Inst_VOPC__V_CMP_EQ_U16
Inst_VOPC__V_CMP_EQ_U16(InFmt_VOPC *)
Definition vopc.cc:3963
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16::~Inst_VOPC__V_CMP_EQ_U16
~Inst_VOPC__V_CMP_EQ_U16()
Definition vopc.cc:3969
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32::Inst_VOPC__V_CMP_EQ_U32
Inst_VOPC__V_CMP_EQ_U32(InFmt_VOPC *)
Definition vopc.cc:5095
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5108
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32::~Inst_VOPC__V_CMP_EQ_U32
~Inst_VOPC__V_CMP_EQ_U32()
Definition vopc.cc:5101
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64::~Inst_VOPC__V_CMP_EQ_U64
~Inst_VOPC__V_CMP_EQ_U64()
Definition vopc.cc:6221
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6228
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64::Inst_VOPC__V_CMP_EQ_U64
Inst_VOPC__V_CMP_EQ_U64(InFmt_VOPC *)
Definition vopc.cc:6215
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16::Inst_VOPC__V_CMP_F_F16
Inst_VOPC__V_CMP_F_F16(InFmt_VOPC *)
Definition vopc.cc:581
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16::~Inst_VOPC__V_CMP_F_F16
~Inst_VOPC__V_CMP_F_F16()
Definition vopc.cc:588
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:595
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32::~Inst_VOPC__V_CMP_F_F32
~Inst_VOPC__V_CMP_F_F32()
Definition vopc.cc:1246
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32::Inst_VOPC__V_CMP_F_F32
Inst_VOPC__V_CMP_F_F32(InFmt_VOPC *)
Definition vopc.cc:1239
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1253
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2447
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64::Inst_VOPC__V_CMP_F_F64
Inst_VOPC__V_CMP_F_F64(InFmt_VOPC *)
Definition vopc.cc:2433
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64::~Inst_VOPC__V_CMP_F_F64
~Inst_VOPC__V_CMP_F_F64()
Definition vopc.cc:2440
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16::~Inst_VOPC__V_CMP_F_I16
~Inst_VOPC__V_CMP_F_I16()
Definition vopc.cc:3633
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3640
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16::Inst_VOPC__V_CMP_F_I16
Inst_VOPC__V_CMP_F_I16(InFmt_VOPC *)
Definition vopc.cc:3627
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4772
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32::~Inst_VOPC__V_CMP_F_I32
~Inst_VOPC__V_CMP_F_I32()
Definition vopc.cc:4765
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32::Inst_VOPC__V_CMP_F_I32
Inst_VOPC__V_CMP_F_I32(InFmt_VOPC *)
Definition vopc.cc:4759
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64::~Inst_VOPC__V_CMP_F_I64
~Inst_VOPC__V_CMP_F_I64()
Definition vopc.cc:5885
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64::Inst_VOPC__V_CMP_F_I64
Inst_VOPC__V_CMP_F_I64(InFmt_VOPC *)
Definition vopc.cc:5879
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5892
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3912
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16::Inst_VOPC__V_CMP_F_U16
Inst_VOPC__V_CMP_F_U16(InFmt_VOPC *)
Definition vopc.cc:3899
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16::~Inst_VOPC__V_CMP_F_U16
~Inst_VOPC__V_CMP_F_U16()
Definition vopc.cc:3905
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32::~Inst_VOPC__V_CMP_F_U32
~Inst_VOPC__V_CMP_F_U32()
Definition vopc.cc:5037
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5044
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32::Inst_VOPC__V_CMP_F_U32
Inst_VOPC__V_CMP_F_U32(InFmt_VOPC *)
Definition vopc.cc:5031
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6164
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64::~Inst_VOPC__V_CMP_F_U64
~Inst_VOPC__V_CMP_F_U64()
Definition vopc.cc:6157
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64::Inst_VOPC__V_CMP_F_U64
Inst_VOPC__V_CMP_F_U64(InFmt_VOPC *)
Definition vopc.cc:6151
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16::~Inst_VOPC__V_CMP_GE_F16
~Inst_VOPC__V_CMP_GE_F16()
Definition vopc.cc:708
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:715
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16::Inst_VOPC__V_CMP_GE_F16
Inst_VOPC__V_CMP_GE_F16(InFmt_VOPC *)
Definition vopc.cc:701
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1468
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32::~Inst_VOPC__V_CMP_GE_F32
~Inst_VOPC__V_CMP_GE_F32()
Definition vopc.cc:1461
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32::Inst_VOPC__V_CMP_GE_F32
Inst_VOPC__V_CMP_GE_F32(InFmt_VOPC *)
Definition vopc.cc:1454
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2662
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64::~Inst_VOPC__V_CMP_GE_F64
~Inst_VOPC__V_CMP_GE_F64()
Definition vopc.cc:2655
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64::Inst_VOPC__V_CMP_GE_F64
Inst_VOPC__V_CMP_GE_F64(InFmt_VOPC *)
Definition vopc.cc:2648
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16::~Inst_VOPC__V_CMP_GE_I16
~Inst_VOPC__V_CMP_GE_I16()
Definition vopc.cc:3841
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16::Inst_VOPC__V_CMP_GE_I16
Inst_VOPC__V_CMP_GE_I16(InFmt_VOPC *)
Definition vopc.cc:3835
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3848
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32::~Inst_VOPC__V_CMP_GE_I32
~Inst_VOPC__V_CMP_GE_I32()
Definition vopc.cc:4973
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32::Inst_VOPC__V_CMP_GE_I32
Inst_VOPC__V_CMP_GE_I32(InFmt_VOPC *)
Definition vopc.cc:4967
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4980
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64::~Inst_VOPC__V_CMP_GE_I64
~Inst_VOPC__V_CMP_GE_I64()
Definition vopc.cc:6093
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6100
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64::Inst_VOPC__V_CMP_GE_I64
Inst_VOPC__V_CMP_GE_I64(InFmt_VOPC *)
Definition vopc.cc:6087
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16::Inst_VOPC__V_CMP_GE_U16
Inst_VOPC__V_CMP_GE_U16(InFmt_VOPC *)
Definition vopc.cc:4119
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4132
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16::~Inst_VOPC__V_CMP_GE_U16
~Inst_VOPC__V_CMP_GE_U16()
Definition vopc.cc:4125
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5252
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32::~Inst_VOPC__V_CMP_GE_U32
~Inst_VOPC__V_CMP_GE_U32()
Definition vopc.cc:5245
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32::Inst_VOPC__V_CMP_GE_U32
Inst_VOPC__V_CMP_GE_U32(InFmt_VOPC *)
Definition vopc.cc:5239
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64::Inst_VOPC__V_CMP_GE_U64
Inst_VOPC__V_CMP_GE_U64(InFmt_VOPC *)
Definition vopc.cc:6359
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64::~Inst_VOPC__V_CMP_GE_U64
~Inst_VOPC__V_CMP_GE_U64()
Definition vopc.cc:6365
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6372
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16::~Inst_VOPC__V_CMP_GT_F16
~Inst_VOPC__V_CMP_GT_F16()
Definition vopc.cc:668
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:675
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16::Inst_VOPC__V_CMP_GT_F16
Inst_VOPC__V_CMP_GT_F16(InFmt_VOPC *)
Definition vopc.cc:661
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32::Inst_VOPC__V_CMP_GT_F32
Inst_VOPC__V_CMP_GT_F32(InFmt_VOPC *)
Definition vopc.cc:1379
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1393
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32::~Inst_VOPC__V_CMP_GT_F32
~Inst_VOPC__V_CMP_GT_F32()
Definition vopc.cc:1386
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2587
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64::Inst_VOPC__V_CMP_GT_F64
Inst_VOPC__V_CMP_GT_F64(InFmt_VOPC *)
Definition vopc.cc:2573
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64::~Inst_VOPC__V_CMP_GT_F64
~Inst_VOPC__V_CMP_GT_F64()
Definition vopc.cc:2580
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16::~Inst_VOPC__V_CMP_GT_I16
~Inst_VOPC__V_CMP_GT_I16()
Definition vopc.cc:3769
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3776
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16::Inst_VOPC__V_CMP_GT_I16
Inst_VOPC__V_CMP_GT_I16(InFmt_VOPC *)
Definition vopc.cc:3763
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32::~Inst_VOPC__V_CMP_GT_I32
~Inst_VOPC__V_CMP_GT_I32()
Definition vopc.cc:4901
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4908
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32::Inst_VOPC__V_CMP_GT_I32
Inst_VOPC__V_CMP_GT_I32(InFmt_VOPC *)
Definition vopc.cc:4895
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6028
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64::Inst_VOPC__V_CMP_GT_I64
Inst_VOPC__V_CMP_GT_I64(InFmt_VOPC *)
Definition vopc.cc:6015
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64::~Inst_VOPC__V_CMP_GT_I64
~Inst_VOPC__V_CMP_GT_I64()
Definition vopc.cc:6021
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4053
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16::Inst_VOPC__V_CMP_GT_U16
Inst_VOPC__V_CMP_GT_U16(InFmt_VOPC *)
Definition vopc.cc:4040
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16::~Inst_VOPC__V_CMP_GT_U16
~Inst_VOPC__V_CMP_GT_U16()
Definition vopc.cc:4046
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32::Inst_VOPC__V_CMP_GT_U32
Inst_VOPC__V_CMP_GT_U32(InFmt_VOPC *)
Definition vopc.cc:5167
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5180
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32::~Inst_VOPC__V_CMP_GT_U32
~Inst_VOPC__V_CMP_GT_U32()
Definition vopc.cc:5173
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64::~Inst_VOPC__V_CMP_GT_U64
~Inst_VOPC__V_CMP_GT_U64()
Definition vopc.cc:6293
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6300
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64::Inst_VOPC__V_CMP_GT_U64
Inst_VOPC__V_CMP_GT_U64(InFmt_VOPC *)
Definition vopc.cc:6287
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:655
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16::Inst_VOPC__V_CMP_LE_F16
Inst_VOPC__V_CMP_LE_F16(InFmt_VOPC *)
Definition vopc.cc:641
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16::~Inst_VOPC__V_CMP_LE_F16
~Inst_VOPC__V_CMP_LE_F16()
Definition vopc.cc:648
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1356
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32::Inst_VOPC__V_CMP_LE_F32
Inst_VOPC__V_CMP_LE_F32(InFmt_VOPC *)
Definition vopc.cc:1342
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32::~Inst_VOPC__V_CMP_LE_F32
~Inst_VOPC__V_CMP_LE_F32()
Definition vopc.cc:1349
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64::Inst_VOPC__V_CMP_LE_F64
Inst_VOPC__V_CMP_LE_F64(InFmt_VOPC *)
Definition vopc.cc:2536
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2550
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64::~Inst_VOPC__V_CMP_LE_F64
~Inst_VOPC__V_CMP_LE_F64()
Definition vopc.cc:2543
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16::~Inst_VOPC__V_CMP_LE_I16
~Inst_VOPC__V_CMP_LE_I16()
Definition vopc.cc:3733
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16::Inst_VOPC__V_CMP_LE_I16
Inst_VOPC__V_CMP_LE_I16(InFmt_VOPC *)
Definition vopc.cc:3727
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3740
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32::Inst_VOPC__V_CMP_LE_I32
Inst_VOPC__V_CMP_LE_I32(InFmt_VOPC *)
Definition vopc.cc:4859
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32::~Inst_VOPC__V_CMP_LE_I32
~Inst_VOPC__V_CMP_LE_I32()
Definition vopc.cc:4865
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4872
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64::Inst_VOPC__V_CMP_LE_I64
Inst_VOPC__V_CMP_LE_I64(InFmt_VOPC *)
Definition vopc.cc:5979
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64::~Inst_VOPC__V_CMP_LE_I64
~Inst_VOPC__V_CMP_LE_I64()
Definition vopc.cc:5985
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5992
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16::Inst_VOPC__V_CMP_LE_U16
Inst_VOPC__V_CMP_LE_U16(InFmt_VOPC *)
Definition vopc.cc:4004
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16::~Inst_VOPC__V_CMP_LE_U16
~Inst_VOPC__V_CMP_LE_U16()
Definition vopc.cc:4010
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4017
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32::~Inst_VOPC__V_CMP_LE_U32
~Inst_VOPC__V_CMP_LE_U32()
Definition vopc.cc:5137
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5144
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32::Inst_VOPC__V_CMP_LE_U32
Inst_VOPC__V_CMP_LE_U32(InFmt_VOPC *)
Definition vopc.cc:5131
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64::~Inst_VOPC__V_CMP_LE_U64
~Inst_VOPC__V_CMP_LE_U64()
Definition vopc.cc:6257
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6264
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64::Inst_VOPC__V_CMP_LE_U64
Inst_VOPC__V_CMP_LE_U64(InFmt_VOPC *)
Definition vopc.cc:6251
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16::~Inst_VOPC__V_CMP_LG_F16
~Inst_VOPC__V_CMP_LG_F16()
Definition vopc.cc:688
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16::Inst_VOPC__V_CMP_LG_F16
Inst_VOPC__V_CMP_LG_F16(InFmt_VOPC *)
Definition vopc.cc:681
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:695
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32::~Inst_VOPC__V_CMP_LG_F32
~Inst_VOPC__V_CMP_LG_F32()
Definition vopc.cc:1423
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32::Inst_VOPC__V_CMP_LG_F32
Inst_VOPC__V_CMP_LG_F32(InFmt_VOPC *)
Definition vopc.cc:1416
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1430
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2624
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64::~Inst_VOPC__V_CMP_LG_F64
~Inst_VOPC__V_CMP_LG_F64()
Definition vopc.cc:2617
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64::Inst_VOPC__V_CMP_LG_F64
Inst_VOPC__V_CMP_LG_F64(InFmt_VOPC *)
Definition vopc.cc:2610
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:615
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16::~Inst_VOPC__V_CMP_LT_F16
~Inst_VOPC__V_CMP_LT_F16()
Definition vopc.cc:608
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16::Inst_VOPC__V_CMP_LT_F16
Inst_VOPC__V_CMP_LT_F16(InFmt_VOPC *)
Definition vopc.cc:601
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32::~Inst_VOPC__V_CMP_LT_F32
~Inst_VOPC__V_CMP_LT_F32()
Definition vopc.cc:1275
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32::Inst_VOPC__V_CMP_LT_F32
Inst_VOPC__V_CMP_LT_F32(InFmt_VOPC *)
Definition vopc.cc:1268
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1282
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64::Inst_VOPC__V_CMP_LT_F64
Inst_VOPC__V_CMP_LT_F64(InFmt_VOPC *)
Definition vopc.cc:2462
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64::~Inst_VOPC__V_CMP_LT_F64
~Inst_VOPC__V_CMP_LT_F64()
Definition vopc.cc:2469
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2476
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16::~Inst_VOPC__V_CMP_LT_I16
~Inst_VOPC__V_CMP_LT_I16()
Definition vopc.cc:3661
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3668
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16::Inst_VOPC__V_CMP_LT_I16
Inst_VOPC__V_CMP_LT_I16(InFmt_VOPC *)
Definition vopc.cc:3655
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32::Inst_VOPC__V_CMP_LT_I32
Inst_VOPC__V_CMP_LT_I32(InFmt_VOPC *)
Definition vopc.cc:4787
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32::~Inst_VOPC__V_CMP_LT_I32
~Inst_VOPC__V_CMP_LT_I32()
Definition vopc.cc:4793
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4800
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64::Inst_VOPC__V_CMP_LT_I64
Inst_VOPC__V_CMP_LT_I64(InFmt_VOPC *)
Definition vopc.cc:5907
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64::~Inst_VOPC__V_CMP_LT_I64
~Inst_VOPC__V_CMP_LT_I64()
Definition vopc.cc:5913
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5920
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16::Inst_VOPC__V_CMP_LT_U16
Inst_VOPC__V_CMP_LT_U16(InFmt_VOPC *)
Definition vopc.cc:3927
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16::~Inst_VOPC__V_CMP_LT_U16
~Inst_VOPC__V_CMP_LT_U16()
Definition vopc.cc:3933
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3940
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32::Inst_VOPC__V_CMP_LT_U32
Inst_VOPC__V_CMP_LT_U32(InFmt_VOPC *)
Definition vopc.cc:5059
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5072
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32::~Inst_VOPC__V_CMP_LT_U32
~Inst_VOPC__V_CMP_LT_U32()
Definition vopc.cc:5065
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64::~Inst_VOPC__V_CMP_LT_U64
~Inst_VOPC__V_CMP_LT_U64()
Definition vopc.cc:6185
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6192
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64::Inst_VOPC__V_CMP_LT_U64
Inst_VOPC__V_CMP_LT_U64(InFmt_VOPC *)
Definition vopc.cc:6179
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16::Inst_VOPC__V_CMP_NEQ_F16
Inst_VOPC__V_CMP_NEQ_F16(InFmt_VOPC *)
Definition vopc.cc:841
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16::~Inst_VOPC__V_CMP_NEQ_F16
~Inst_VOPC__V_CMP_NEQ_F16()
Definition vopc.cc:848
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:855
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32::~Inst_VOPC__V_CMP_NEQ_F32
~Inst_VOPC__V_CMP_NEQ_F32()
Definition vopc.cc:1723
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1730
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32::Inst_VOPC__V_CMP_NEQ_F32
Inst_VOPC__V_CMP_NEQ_F32(InFmt_VOPC *)
Definition vopc.cc:1716
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64::Inst_VOPC__V_CMP_NEQ_F64
Inst_VOPC__V_CMP_NEQ_F64(InFmt_VOPC *)
Definition vopc.cc:2910
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2924
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64::~Inst_VOPC__V_CMP_NEQ_F64
~Inst_VOPC__V_CMP_NEQ_F64()
Definition vopc.cc:2917
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3812
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16::~Inst_VOPC__V_CMP_NE_I16
~Inst_VOPC__V_CMP_NE_I16()
Definition vopc.cc:3805
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16::Inst_VOPC__V_CMP_NE_I16
Inst_VOPC__V_CMP_NE_I16(InFmt_VOPC *)
Definition vopc.cc:3799
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32::~Inst_VOPC__V_CMP_NE_I32
~Inst_VOPC__V_CMP_NE_I32()
Definition vopc.cc:4937
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32::Inst_VOPC__V_CMP_NE_I32
Inst_VOPC__V_CMP_NE_I32(InFmt_VOPC *)
Definition vopc.cc:4931
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4944
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6064
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64::~Inst_VOPC__V_CMP_NE_I64
~Inst_VOPC__V_CMP_NE_I64()
Definition vopc.cc:6057
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64::Inst_VOPC__V_CMP_NE_I64
Inst_VOPC__V_CMP_NE_I64(InFmt_VOPC *)
Definition vopc.cc:6051
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16::~Inst_VOPC__V_CMP_NE_U16
~Inst_VOPC__V_CMP_NE_U16()
Definition vopc.cc:4082
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4089
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16::Inst_VOPC__V_CMP_NE_U16
Inst_VOPC__V_CMP_NE_U16(InFmt_VOPC *)
Definition vopc.cc:4076
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32::Inst_VOPC__V_CMP_NE_U32
Inst_VOPC__V_CMP_NE_U32(InFmt_VOPC *)
Definition vopc.cc:5203
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5216
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32::~Inst_VOPC__V_CMP_NE_U32
~Inst_VOPC__V_CMP_NE_U32()
Definition vopc.cc:5209
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64::Inst_VOPC__V_CMP_NE_U64
Inst_VOPC__V_CMP_NE_U64(InFmt_VOPC *)
Definition vopc.cc:6323
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6336
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64::~Inst_VOPC__V_CMP_NE_U64
~Inst_VOPC__V_CMP_NE_U64()
Definition vopc.cc:6329
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:775
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16::Inst_VOPC__V_CMP_NGE_F16
Inst_VOPC__V_CMP_NGE_F16(InFmt_VOPC *)
Definition vopc.cc:761
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16::~Inst_VOPC__V_CMP_NGE_F16
~Inst_VOPC__V_CMP_NGE_F16()
Definition vopc.cc:768
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1581
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32::Inst_VOPC__V_CMP_NGE_F32
Inst_VOPC__V_CMP_NGE_F32(InFmt_VOPC *)
Definition vopc.cc:1567
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32::~Inst_VOPC__V_CMP_NGE_F32
~Inst_VOPC__V_CMP_NGE_F32()
Definition vopc.cc:1574
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2775
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64::~Inst_VOPC__V_CMP_NGE_F64
~Inst_VOPC__V_CMP_NGE_F64()
Definition vopc.cc:2768
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64::Inst_VOPC__V_CMP_NGE_F64
Inst_VOPC__V_CMP_NGE_F64(InFmt_VOPC *)
Definition vopc.cc:2761
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16::Inst_VOPC__V_CMP_NGT_F16
Inst_VOPC__V_CMP_NGT_F16(InFmt_VOPC *)
Definition vopc.cc:801
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:815
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16::~Inst_VOPC__V_CMP_NGT_F16
~Inst_VOPC__V_CMP_NGT_F16()
Definition vopc.cc:808
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32::Inst_VOPC__V_CMP_NGT_F32
Inst_VOPC__V_CMP_NGT_F32(InFmt_VOPC *)
Definition vopc.cc:1642
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32::~Inst_VOPC__V_CMP_NGT_F32
~Inst_VOPC__V_CMP_NGT_F32()
Definition vopc.cc:1649
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1656
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64::~Inst_VOPC__V_CMP_NGT_F64
~Inst_VOPC__V_CMP_NGT_F64()
Definition vopc.cc:2843
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64::Inst_VOPC__V_CMP_NGT_F64
Inst_VOPC__V_CMP_NGT_F64(InFmt_VOPC *)
Definition vopc.cc:2836
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2850
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:835
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16::~Inst_VOPC__V_CMP_NLE_F16
~Inst_VOPC__V_CMP_NLE_F16()
Definition vopc.cc:828
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16::Inst_VOPC__V_CMP_NLE_F16
Inst_VOPC__V_CMP_NLE_F16(InFmt_VOPC *)
Definition vopc.cc:821
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32::Inst_VOPC__V_CMP_NLE_F32
Inst_VOPC__V_CMP_NLE_F32(InFmt_VOPC *)
Definition vopc.cc:1679
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32::~Inst_VOPC__V_CMP_NLE_F32
~Inst_VOPC__V_CMP_NLE_F32()
Definition vopc.cc:1686
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1693
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2887
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64::~Inst_VOPC__V_CMP_NLE_F64
~Inst_VOPC__V_CMP_NLE_F64()
Definition vopc.cc:2880
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64::Inst_VOPC__V_CMP_NLE_F64
Inst_VOPC__V_CMP_NLE_F64(InFmt_VOPC *)
Definition vopc.cc:2873
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16::Inst_VOPC__V_CMP_NLG_F16
Inst_VOPC__V_CMP_NLG_F16(InFmt_VOPC *)
Definition vopc.cc:781
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:795
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16::~Inst_VOPC__V_CMP_NLG_F16
~Inst_VOPC__V_CMP_NLG_F16()
Definition vopc.cc:788
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32::~Inst_VOPC__V_CMP_NLG_F32
~Inst_VOPC__V_CMP_NLG_F32()
Definition vopc.cc:1611
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1618
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32::Inst_VOPC__V_CMP_NLG_F32
Inst_VOPC__V_CMP_NLG_F32(InFmt_VOPC *)
Definition vopc.cc:1604
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2812
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64::~Inst_VOPC__V_CMP_NLG_F64
~Inst_VOPC__V_CMP_NLG_F64()
Definition vopc.cc:2805
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64::Inst_VOPC__V_CMP_NLG_F64
Inst_VOPC__V_CMP_NLG_F64(InFmt_VOPC *)
Definition vopc.cc:2798
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16::Inst_VOPC__V_CMP_NLT_F16
Inst_VOPC__V_CMP_NLT_F16(InFmt_VOPC *)
Definition vopc.cc:861
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:875
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16::~Inst_VOPC__V_CMP_NLT_F16
~Inst_VOPC__V_CMP_NLT_F16()
Definition vopc.cc:868
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32::~Inst_VOPC__V_CMP_NLT_F32
~Inst_VOPC__V_CMP_NLT_F32()
Definition vopc.cc:1760
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32::Inst_VOPC__V_CMP_NLT_F32
Inst_VOPC__V_CMP_NLT_F32(InFmt_VOPC *)
Definition vopc.cc:1753
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1767
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64::Inst_VOPC__V_CMP_NLT_F64
Inst_VOPC__V_CMP_NLT_F64(InFmt_VOPC *)
Definition vopc.cc:2947
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64::~Inst_VOPC__V_CMP_NLT_F64
~Inst_VOPC__V_CMP_NLT_F64()
Definition vopc.cc:2954
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2961
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16::~Inst_VOPC__V_CMP_O_F16
~Inst_VOPC__V_CMP_O_F16()
Definition vopc.cc:728
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16::Inst_VOPC__V_CMP_O_F16
Inst_VOPC__V_CMP_O_F16(InFmt_VOPC *)
Definition vopc.cc:721
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:735
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1505
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32::~Inst_VOPC__V_CMP_O_F32
~Inst_VOPC__V_CMP_O_F32()
Definition vopc.cc:1498
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32::Inst_VOPC__V_CMP_O_F32
Inst_VOPC__V_CMP_O_F32(InFmt_VOPC *)
Definition vopc.cc:1491
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64::~Inst_VOPC__V_CMP_O_F64
~Inst_VOPC__V_CMP_O_F64()
Definition vopc.cc:2692
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64::Inst_VOPC__V_CMP_O_F64
Inst_VOPC__V_CMP_O_F64(InFmt_VOPC *)
Definition vopc.cc:2685
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2699
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16::Inst_VOPC__V_CMP_TRU_F16
Inst_VOPC__V_CMP_TRU_F16(InFmt_VOPC *)
Definition vopc.cc:881
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:895
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16::~Inst_VOPC__V_CMP_TRU_F16
~Inst_VOPC__V_CMP_TRU_F16()
Definition vopc.cc:888
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32::~Inst_VOPC__V_CMP_TRU_F32
~Inst_VOPC__V_CMP_TRU_F32()
Definition vopc.cc:1797
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1804
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32::Inst_VOPC__V_CMP_TRU_F32
Inst_VOPC__V_CMP_TRU_F32(InFmt_VOPC *)
Definition vopc.cc:1790
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64::~Inst_VOPC__V_CMP_TRU_F64
~Inst_VOPC__V_CMP_TRU_F64()
Definition vopc.cc:2991
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64::Inst_VOPC__V_CMP_TRU_F64
Inst_VOPC__V_CMP_TRU_F64(InFmt_VOPC *)
Definition vopc.cc:2984
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2998
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16::~Inst_VOPC__V_CMP_T_I16
~Inst_VOPC__V_CMP_T_I16()
Definition vopc.cc:3877
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16::Inst_VOPC__V_CMP_T_I16
Inst_VOPC__V_CMP_T_I16(InFmt_VOPC *)
Definition vopc.cc:3871
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:3884
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32::Inst_VOPC__V_CMP_T_I32
Inst_VOPC__V_CMP_T_I32(InFmt_VOPC *)
Definition vopc.cc:5003
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32::~Inst_VOPC__V_CMP_T_I32
~Inst_VOPC__V_CMP_T_I32()
Definition vopc.cc:5009
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5016
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64::~Inst_VOPC__V_CMP_T_I64
~Inst_VOPC__V_CMP_T_I64()
Definition vopc.cc:6129
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6136
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64::Inst_VOPC__V_CMP_T_I64
Inst_VOPC__V_CMP_T_I64(InFmt_VOPC *)
Definition vopc.cc:6123
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16::~Inst_VOPC__V_CMP_T_U16
~Inst_VOPC__V_CMP_T_U16()
Definition vopc.cc:4161
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16::Inst_VOPC__V_CMP_T_U16
Inst_VOPC__V_CMP_T_U16(InFmt_VOPC *)
Definition vopc.cc:4155
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:4168
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:5288
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32::Inst_VOPC__V_CMP_T_U32
Inst_VOPC__V_CMP_T_U32(InFmt_VOPC *)
Definition vopc.cc:5275
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32::~Inst_VOPC__V_CMP_T_U32
~Inst_VOPC__V_CMP_T_U32()
Definition vopc.cc:5281
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:6408
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64::~Inst_VOPC__V_CMP_T_U64
~Inst_VOPC__V_CMP_T_U64()
Definition vopc.cc:6401
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64::Inst_VOPC__V_CMP_T_U64
Inst_VOPC__V_CMP_T_U64(InFmt_VOPC *)
Definition vopc.cc:6395
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16::Inst_VOPC__V_CMP_U_F16
Inst_VOPC__V_CMP_U_F16(InFmt_VOPC *)
Definition vopc.cc:741
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16::~Inst_VOPC__V_CMP_U_F16
~Inst_VOPC__V_CMP_U_F16()
Definition vopc.cc:748
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:755
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32::~Inst_VOPC__V_CMP_U_F32
~Inst_VOPC__V_CMP_U_F32()
Definition vopc.cc:1536
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32::Inst_VOPC__V_CMP_U_F32
Inst_VOPC__V_CMP_U_F32(InFmt_VOPC *)
Definition vopc.cc:1529
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:1543
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64::Inst_VOPC__V_CMP_U_F64
Inst_VOPC__V_CMP_U_F64(InFmt_VOPC *)
Definition vopc.cc:2723
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64::execute
void execute(GPUDynInstPtr) override
Definition vopc.cc:2737
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64::~Inst_VOPC__V_CMP_U_F64
~Inst_VOPC__V_CMP_U_F64()
Definition vopc.cc:2730
gem5::VegaISA::Inst_VOPC
Definition op_encodings.hh:408
gem5::VegaISA::Inst_VOPC::instData
InFmt_VOPC instData
Definition op_encodings.hh:420
gem5::VegaISA::ScalarOperand::rawData
std::enable_if< Condition, DataType >::type rawData() const
we store scalar data in a std::array, however if we need the full operand data we use this method to ...
Definition operand.hh:392
gem5::VegaISA::ScalarOperand::setBit
std::enable_if< Condition, void >::type setBit(int bit, int bit_val)
bit access to scalar data.
Definition operand.hh:491
gem5::VegaISA::VecOperand::read
void read() override
read from the vrf.
Definition operand.hh:147
gem5::VegaISA::VecOperand::readSrc
void readSrc()
certain vector operands can read from the vrf/srf or constants.
Definition operand.hh:131
gem5::Wavefront::execMask
VectorMask & execMask()
Definition wavefront.cc:1451
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
gem5::ArmISA::b
Bitfield< 7 > b
Definition misc_types.hh:468
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition vec.hh:61
gem5::ArmISA::a
Bitfield< 8 > a
Definition misc_types.hh:66
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition misc.hh:49
std::isinf
constexpr bool isinf(gem5::AMDGPU::fp16_e5m10_info a)
Definition fp16_e5m10.hh:78
std::isnan
constexpr bool isnan(gem5::AMDGPU::fp16_e5m10_info a)
Definition fp16_e5m10.hh:83
std::isnormal
constexpr bool isnormal(gem5::AMDGPU::fp16_e5m10_info a)
Definition fp16_e5m10.hh:88
gem5::VegaISA::InFmt_VOPC
Definition gpu_decoder.hh:1907
gem5::VegaISA::InFmt_VOPC::VSRC1
unsigned int VSRC1
Definition gpu_decoder.hh:1909
gem5::VegaISA::InFmt_VOPC::SRC0
unsigned int SRC0
Definition gpu_decoder.hh:1908
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