gem5
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arch
arm
fastmodel
remote_gdb.cc
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/* * Copyright 2022 Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/arm/fastmodel/remote_gdb.hh
"
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#include "
arch/arm/fastmodel/iris/thread_context.hh
"
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#include "
arch/arm/utility.hh
"
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#include "
base/trace.hh
"
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#include "debug/GDBAcc.hh"
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namespace
gem5
{
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using namespace
ArmISA
;
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namespace
fastmodel
{
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void
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FastmodelRemoteGDB::AArch64GdbRegCache::setRegs
(
ThreadContext
*
context
)
const
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{
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DPRINTF
(GDBAcc,
"setRegs in remotegdb \n"
);
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for
(
int
i
= 0;
i
< 31; ++
i
)
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context
->setReg(
int_reg::x
(
i
),
r
.x[
i
]);
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auto
pc_state =
context
->pcState().as<
PCState
>();
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pc_state.
set
(
r
.pc);
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context
->pcState(pc_state);
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context
->setMiscRegNoEffect(
MISCREG_CPSR
,
r
.cpsr);
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// Update the stack pointer. This should be done after
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// updating CPSR/PSTATE since that might affect how SPX gets
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// mapped.
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context
->setReg(
int_reg::Spx
,
r
.spx);
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// Remove the vector registers update in FastmodelRemoteGDB since it's not
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// implemented in iris::ThreadContext.
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warn
(
"Skip update vector registers in remotegdb\n"
);
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context
->setMiscRegNoEffect(
MISCREG_FPSR
,
r
.fpsr);
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context
->setMiscRegNoEffect(
MISCREG_FPCR
,
r
.fpcr);
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}
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FastmodelRemoteGDB::FastmodelRemoteGDB
(
System
*_system,
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ListenSocketConfig
_listen_config)
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:
gem5
::
ArmISA
::
RemoteGDB
(_system, _listen_config),
regCache64
(this)
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{
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}
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bool
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FastmodelRemoteGDB::readBlob
(
Addr
vaddr
,
size_t
size,
char
*
data
)
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{
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auto
tc
=
dynamic_cast<
Iris::ThreadContext
*
>
(
context
());
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panic_if
(!
tc
,
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"FastmodelRemoteGdb can only work on Iris::ThreadContext"
);
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tc
->readMemWithCurrentMsn(
vaddr
, size,
data
);
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return
true
;
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}
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bool
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FastmodelRemoteGDB::writeBlob
(
Addr
vaddr
,
size_t
size,
const
char
*
data
)
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{
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auto
tc
=
dynamic_cast<
Iris::ThreadContext
*
>
(
context
());
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panic_if
(!
tc
,
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"FastmodelRemoteGdb can only work on Iris::ThreadContext"
);
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tc
->writeMemWithCurrentMsn(
vaddr
, size,
data
);
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return
true
;
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}
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BaseGdbRegCache
*
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FastmodelRemoteGDB::gdbRegs
()
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{
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if
(
inAArch64
(
context
()))
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return
&
regCache64
;
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else
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return
&
regCache32
;
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}
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}
// namespace fastmodel
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}
// namespace gem5
thread_context.hh
remote_gdb.hh
utility.hh
trace.hh
DPRINTF
#define DPRINTF(x,...)
Definition
trace.hh:209
data
const char data[]
Definition
circlebuf.test.cc:48
gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::r
struct gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::GEM5_PACKED r
gem5::ArmISA::RemoteGDB::regCache32
AArch32GdbRegCache regCache32
Definition
remote_gdb.hh:117
gem5::ArmISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, ListenSocketConfig _listen_config)
Definition
remote_gdb.cc:204
gem5::BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition
remote_gdb.hh:86
gem5::BaseRemoteGDB::tc
ThreadContext * tc
Definition
remote_gdb.hh:272
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition
remote_gdb.hh:443
gem5::GenericISA::SimplePCState::set
void set(Addr val) override
Force this PC to reflect a particular value, resetting all its other fields around it.
Definition
pcstate.hh:378
gem5::Iris::ThreadContext
Definition
thread_context.hh:55
gem5::ListenSocketConfig
Definition
socket.hh:115
gem5::PowerISA::PCState
Definition
pcstate.hh:43
gem5::System
Definition
system.hh:75
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
thread_context.hh:89
gem5::fastmodel::FastmodelRemoteGDB::AArch64GdbRegCache::setRegs
void setRegs(ThreadContext *) const override
Set the ThreadContext's registers from the values in the raw buffer.
Definition
remote_gdb.cc:41
gem5::fastmodel::FastmodelRemoteGDB::regCache64
AArch64GdbRegCache regCache64
Definition
remote_gdb.hh:56
gem5::fastmodel::FastmodelRemoteGDB::readBlob
bool readBlob(Addr vaddr, size_t size, char *data) override
Definition
remote_gdb.cc:71
gem5::fastmodel::FastmodelRemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs() override
Definition
remote_gdb.cc:91
gem5::fastmodel::FastmodelRemoteGDB::writeBlob
bool writeBlob(Addr vaddr, size_t size, const char *data) override
Definition
remote_gdb.cc:81
gem5::fastmodel::FastmodelRemoteGDB::FastmodelRemoteGDB
FastmodelRemoteGDB(System *_system, ListenSocketConfig _listen_config)
Definition
remote_gdb.cc:64
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition
logging.hh:246
warn
#define warn(...)
Definition
logging.hh:288
gem5::ArmISA::int_reg::x
static RegId x(unsigned index)
Definition
int.hh:445
gem5::ArmISA::int_reg::Spx
constexpr RegId Spx
Definition
int.hh:238
gem5::ArmISA
Definition
decoder.cc:54
gem5::ArmISA::i
Bitfield< 7 > i
Definition
misc_types.hh:67
gem5::ArmISA::MISCREG_FPSR
@ MISCREG_FPSR
Definition
misc.hh:660
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition
misc.hh:79
gem5::ArmISA::MISCREG_FPCR
@ MISCREG_FPCR
Definition
misc.hh:659
gem5::ArmISA::inAArch64
bool inAArch64(ThreadContext *tc)
Definition
utility.cc:127
gem5::MipsISA::vaddr
vaddr
Definition
pra_constants.hh:278
gem5::fastmodel
Definition
amba_from_tlm_bridge.cc:38
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition
binary32.hh:36
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
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