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gem5 [DEVELOP-FOR-25.0]
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#include "arch/riscv/faults.hh"#include "arch/riscv/insts/static_inst.hh"#include "arch/riscv/isa.hh"#include "arch/riscv/mmu.hh"#include "arch/riscv/pmp.hh"#include "arch/riscv/regs/misc.hh"#include "arch/riscv/utility.hh"#include "cpu/base.hh"#include "cpu/thread_context.hh"#include "debug/Faults.hh"#include "sim/debug.hh"#include "sim/full_system.hh"#include "sim/workload.hh"Go to the source code of this file.
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |
| namespace | gem5::RiscvISA |
Functions | |
| bool | gem5::RiscvISA::getFaultVAddr (Fault fault, Addr &va) |
| Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise. | |