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fs_workload.hh
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1/*
2 * Copyright (c) 2010, 2012-2013, 2015-2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __ARCH_ARM_FS_WORKLOAD_HH__
42#define __ARCH_ARM_FS_WORKLOAD_HH__
43
44#include <memory>
45#include <vector>
46
47#include "arch/arm/aapcs32.hh"
48#include "arch/arm/aapcs64.hh"
50#include "kern/linux/events.hh"
52#include "sim/sim_object.hh"
53
54namespace gem5
55{
56
57struct ArmFsWorkloadParams;
58
59namespace ArmISA
60{
61
62class SkipFunc : public SkipFuncBase
63{
64 public:
66 void returnFromFuncIn(ThreadContext *tc) override;
67};
68
70{
71 protected:
74
79
86
95
96 template <template <class ABI, class Base> class FuncEvent,
97 typename... Args>
98 PCEvent *
99 addSkipFunc(Args... args)
100 {
101 if (getArch() == loader::Arm64) {
103 std::forward<Args>(args)...);
104 } else {
106 std::forward<Args>(args)...);
107 }
108 }
109
110 template <template <class ABI, class Base> class FuncEvent,
111 typename... Args>
112 PCEvent *
113 addSkipFuncOrPanic(Args... args)
114 {
115 if (getArch() == loader::Arm64) {
117 std::forward<Args>(args)...);
118 } else {
120 std::forward<Args>(args)...);
121 }
122 }
123
124 public:
125 PARAMS(ArmFsWorkload);
126
127 Addr
128 getEntry() const override
129 {
130 if (bootldr)
131 return bootldr->entryPoint();
132 else
133 return kernelEntry;
134 }
135
137 getArch() const override
138 {
139 if (bootldr)
140 return bootldr->getArch();
141 else if (kernelObj)
142 return kernelObj->getArch();
143 else
144 return loader::Arm64;
145 }
146
147 ByteOrder byteOrder() const override { return ByteOrder::little; }
148
149 FsWorkload(const Params &p);
150
151 void initState() override;
152
153 void setSystem(System *sys) override;
154
155 Addr
156 fixFuncEventAddr(Addr addr) const override
157 {
158 // Remove the low bit that thumb symbols have set
159 // but that aren't actually odd aligned
160 return addr & ~1;
161 }
162};
163
164} // namespace ArmISA
165} // namespace gem5
166
167#endif // __ARCH_ARM_FS_WORKLOAD_HH__
Addr fixFuncEventAddr(Addr addr) const override
loader::ObjectFile * getBootLoader(loader::ObjectFile *const obj)
Get a boot loader that matches the kernel.
PCEvent * addSkipFuncOrPanic(Args... args)
loader::ObjectFile * bootldr
Pointer to the bootloader object.
Addr getEntry() const override
void setSystem(System *sys) override
loader::Arch getArch() const override
ByteOrder byteOrder() const override
std::vector< std::unique_ptr< loader::ObjectFile > > bootLoaders
Bootloaders.
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Addr kernelEntry
This differs from entry since it takes into account where the kernel is loaded in memory (with loadAd...
FsWorkload(const Params &p)
PCEvent * addSkipFunc(Args... args)
void returnFromFuncIn(ThreadContext *tc) override
SkipFuncBase(PCEventScope *s, const std::string &desc, Addr addr)
loader::ObjectFile * kernelObj
T * addKernelFuncEventOrPanic(const char *lbl, Args... args)
T * addKernelFuncEvent(const char *lbl, Args... args)
Add a function-based event to a kernel symbol.
KernelWorkload(const Params &p)
SimObjectParams Params
SkipFuncBase(PCEventScope *s, const std::string &desc, Addr addr)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
STL vector class.
Definition stl.hh:37
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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