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gem5 [DEVELOP-FOR-25.0]
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Data TLB Invalidate by ASID match. More...
#include <tlbi_op.hh>
Public Member Functions | |
| DTLBIASID (TranslationRegime _target_regime, SecurityState _ss, uint16_t _asid) | |
| void | operator() (ThreadContext *tc) override |
| bool | matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override |
Public Member Functions inherited from gem5::ArmISA::TLBIASID | |
| TLBIASID (TranslationRegime _target_regime, SecurityState _ss, uint16_t _asid, Attr _attr=Attr::None) | |
| void | operator() (ThreadContext *tc) override |
| bool | matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override |
Public Member Functions inherited from gem5::ArmISA::TLBIOp | |
| TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr) | |
| virtual | ~TLBIOp () |
| void | broadcast (ThreadContext *tc) |
| Broadcast the TLB Invalidate operation to all TLBs in the Arm system. | |
| bool | match (TlbEntry *entry, vmid_t curr_vmid) const |
| virtual bool | stage1Flush () const |
| Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. | |
| virtual bool | stage2Flush () const |
| Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. | |
Additional Inherited Members | |
Public Types inherited from gem5::ArmISA::TLBIOp | |
| enum class | Attr { None , ExcludeXS } |
Public Attributes inherited from gem5::ArmISA::TLBIASID | |
| uint16_t | asid |
| bool | el2Enabled |
Public Attributes inherited from gem5::ArmISA::TLBIOp | |
| SecurityState | ss |
| TranslationRegime | targetRegime |
| Attr | attr |
Data TLB Invalidate by ASID match.
Definition at line 246 of file tlbi_op.hh.
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inline |
Definition at line 249 of file tlbi_op.hh.
References gem5::ArmISA::TLBIASID::TLBIASID().
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overridevirtual |
Implements gem5::ArmISA::TLBIOp.
Definition at line 186 of file tlbi_op.cc.
References gem5::ArmISA::TLBIASID::matchEntry(), and gem5::ArmISA::te.
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overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 179 of file tlbi_op.cc.
References gem5::ArmISA::MMU::dflush(), gem5::ArmISA::EL2Enabled(), gem5::ArmISA::TLBIASID::el2Enabled, and gem5::ArmISA::getMMUPtr().