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gem5 [DEVELOP-FOR-25.0]
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#include <tlbi_op.hh>
Public Member Functions | |
| TLBIALL (TranslationRegime _target_regime, SecurityState _ss, Attr _attr=Attr::None) | |
| void | operator() (ThreadContext *tc) override |
| bool | matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override |
| bool | stage2Flush () const override |
| Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class. | |
Public Member Functions inherited from gem5::ArmISA::TLBIOp | |
| TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr) | |
| virtual | ~TLBIOp () |
| void | broadcast (ThreadContext *tc) |
| Broadcast the TLB Invalidate operation to all TLBs in the Arm system. | |
| bool | match (TlbEntry *entry, vmid_t curr_vmid) const |
| virtual bool | stage1Flush () const |
| Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class. | |
Public Attributes | |
| bool | el2Enabled |
| ExceptionLevel | currentEL |
Public Attributes inherited from gem5::ArmISA::TLBIOp | |
| SecurityState | ss |
| TranslationRegime | targetRegime |
| Attr | attr |
Additional Inherited Members | |
Public Types inherited from gem5::ArmISA::TLBIOp | |
| enum class | Attr { None , ExcludeXS } |
TLB Invalidate All.
Definition at line 117 of file tlbi_op.hh.
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inline |
Definition at line 120 of file tlbi_op.hh.
References currentEL, gem5::ArmISA::EL0, el2Enabled, gem5::ArmISA::TLBIOp::None, and gem5::ArmISA::TLBIOp::TLBIOp().
Referenced by gem5::ArmISA::DTLBIALL::DTLBIALL(), and gem5::ArmISA::ITLBIALL::ITLBIALL().
Implements gem5::ArmISA::TLBIOp.
Definition at line 70 of file tlbi_op.cc.
References el2Enabled, gem5::ArmISA::TLBIOp::ss, gem5::ArmISA::TLBIOp::targetRegime, and gem5::ArmISA::te.
Referenced by gem5::ArmISA::DTLBIALL::matchEntry(), and gem5::ArmISA::ITLBIALL::matchEntry().
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overridevirtual |
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 55 of file tlbi_op.cc.
References gem5::ArmISA::currEL(), currentEL, gem5::ArmISA::EL2Enabled(), el2Enabled, gem5::ArmISA::MMU::flush(), gem5::ThreadContext::getCheckerCpuPtr(), and gem5::ArmISA::getMMUPtr().
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inlineoverridevirtual |
Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.
Reimplemented from gem5::ArmISA::TLBIOp.
Definition at line 131 of file tlbi_op.hh.
References currentEL, and gem5::ArmISA::EL2.
| ExceptionLevel gem5::ArmISA::TLBIALL::currentEL |
Definition at line 139 of file tlbi_op.hh.
Referenced by operator()(), stage2Flush(), and TLBIALL().
| bool gem5::ArmISA::TLBIALL::el2Enabled |
Definition at line 138 of file tlbi_op.hh.
Referenced by matchEntry(), gem5::ArmISA::DTLBIALL::operator()(), gem5::ArmISA::ITLBIALL::operator()(), operator()(), and TLBIALL().