gem5::ArmISA::TLBIALLN Class Reference

TLB Invalidate All, Non-Secure. More...

#include <tlbi_op.hh>

Inheritance diagram for gem5::ArmISA::TLBIALLN:

Public Member Functions
	TLBIALLN (TranslationRegime _target_regime)
void	operator() (ThreadContext *tc) override
bool	matchEntry (TlbEntry *entry, vmid_t curr_vmid) const override
bool	stage2Flush () const override
	Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.
Public Member Functions inherited from gem5::ArmISA::TLBIOp
	TLBIOp (TranslationRegime _target_regime, SecurityState _ss, Attr _attr)
virtual	~TLBIOp ()
void	broadcast (ThreadContext *tc)
	Broadcast the TLB Invalidate operation to all TLBs in the Arm system.
bool	match (TlbEntry *entry, vmid_t curr_vmid) const
virtual bool	stage1Flush () const
	Return true if the TLBI op needs to flush stage1 entries, Defaulting to true in the TLBIOp abstract class.

Additional Inherited Members
Public Types inherited from gem5::ArmISA::TLBIOp
enum class	Attr { None , ExcludeXS }
Public Attributes inherited from gem5::ArmISA::TLBIOp
SecurityState	ss
TranslationRegime	targetRegime
Attr	attr

Detailed Description

TLB Invalidate All, Non-Secure.

Definition at line 260 of file tlbi_op.hh.

Constructor & Destructor Documentation

TLBIALLN()

gem5::ArmISA::TLBIALLN::TLBIALLN ( TranslationRegime _target_regime )

inline

Definition at line 263 of file tlbi_op.hh.

References gem5::ArmISA::TLBIOp::None, gem5::ArmISA::NonSecure, and gem5::ArmISA::TLBIOp::TLBIOp().

Member Function Documentation

matchEntry()

bool gem5::ArmISA::TLBIALLN::matchEntry ( TlbEntry * entry, vmid_t curr_vmid ) const

overridevirtual

Implements gem5::ArmISA::TLBIOp.

Definition at line 203 of file tlbi_op.cc.

References gem5::ArmISA::NonSecure, gem5::ArmISA::TLBIOp::targetRegime, and gem5::ArmISA::te.

operator()()

void gem5::ArmISA::TLBIALLN::operator() ( ThreadContext * tc )

overridevirtual

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 192 of file tlbi_op.cc.

References gem5::ArmISA::MMU::flush(), gem5::ThreadContext::getCheckerCpuPtr(), and gem5::ArmISA::getMMUPtr().

stage2Flush()

bool gem5::ArmISA::TLBIALLN::stage2Flush ( ) const

inlineoverridevirtual

Return true if the TLBI op needs to flush stage2 entries, Defaulting to false in the TLBIOp abstract class.

Reimplemented from gem5::ArmISA::TLBIOp.

Definition at line 272 of file tlbi_op.hh.

References gem5::ArmISA::EL2, and gem5::ArmISA::TLBIOp::targetRegime.

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The documentation for this class was generated from the following files:

• arch/arm/tlbi_op.hh
• arch/arm/tlbi_op.cc