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comm.hh
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1/*
2 * Copyright (c) 2011, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * Copyright (c) 2022-2023 The University of Edinburgh
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated
13 * unmodified and in its entirety in all distributions of the software,
14 * modified or unmodified, in source code or in binary form.
15 *
16 * Copyright (c) 2004-2006 The Regents of The University of Michigan
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 */
42
43#ifndef __CPU_O3_COMM_HH__
44#define __CPU_O3_COMM_HH__
45
46#include <vector>
47
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
52#include "cpu/o3/limits.hh"
53#include "sim/faults.hh"
54
55namespace gem5
56{
57
58namespace o3
59{
60
71
79
87
104
106{
107 int size;
108
110};
111
114{
116 {
117 bool block;
119 bool squash;
120 std::unique_ptr<PCStateBase> nextPC;
121 };
122
124
126 {
127 std::unique_ptr<PCStateBase> nextPC;
132 uint64_t branchAddr = 0;
133 unsigned branchCount = 0;
134 bool squash = false;
135 bool controlMispredict = false;
136 bool branchMispredict = false;
137 bool branchTaken = false;
138 };
139
141
142 struct RenameComm {};
143
145
146 struct IewComm
147 {
148 // Also eventually include skid buffer space.
149 unsigned freeIQEntries = 0;
150 unsigned freeLQEntries = 0;
151 unsigned freeSQEntries = 0;
152 unsigned dispatchedToLQ = 0;
153 unsigned dispatchedToSQ = 0;
154
155 unsigned iqCount = 0;
156 unsigned ldstqCount = 0;
157
158 unsigned dispatched = 0;
159 bool usedIQ = false;
160 bool usedLSQ = false;
161 };
162
164
166 {
168 // This code has been re-structured for better packing of variables
169 // instead of by stage which is the more logical way to arrange the
170 // data.
171 // F = Fetch
172 // D = Decode
173 // I = IEW
174 // R = Rename
175 // As such each member is annotated with who consumes it
176 // e.g. bool variable name // *F,R for Fetch and Rename
178
182 std::unique_ptr<PCStateBase> pc; // *F
183
187
190
194
198
202 InstSeqNum doneSeqNum = 0; // *F, I
203
205 unsigned freeROBEntries = 0; // *R
206
207 bool squash = false; // *F, D, R, I
208 bool robSquashing = false; // *F, D, R, I
209
211 bool usedROB = false; // *R
212
214 bool emptyROB = false; // *R
215
217 bool branchTaken = false; // *F
219 bool interruptPending = false; // *F
221 bool clearInterrupt = false; // *F
223 bool trapPending = false; // *F
224
227 bool strictlyOrdered = false; // *I
228
229 };
230
232
239};
240
246template <class CommStruct>
247void
248removeCommThreadInsts(ThreadID tid, CommStruct& comm_struct)
249{
250 auto has_tid = [tid] (const auto &inst) -> bool {
251 return inst && inst->threadNumber == tid;
252 };
253 DynInstPtr *last = std::remove_if(comm_struct.insts,
254 comm_struct.insts + comm_struct.size,
255 has_tid);
256 std::fill(last, comm_struct.insts + comm_struct.size, nullptr);
257 comm_struct.size = last - comm_struct.insts;
258}
259
260} // namespace o3
261} // namespace gem5
262
263#endif //__CPU_O3_COMM_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
static constexpr int MaxThreads
Definition limits.hh:38
void removeCommThreadInsts(ThreadID tid, CommStruct &comm_struct)
Remove instructions belonging to given thread from the given comm struct's instruction array.
Definition comm.hh:248
RefCountingPtr< DynInst > DynInstPtr
static constexpr int MaxWidth
Definition limits.hh:37
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t InstSeqNum
Definition inst_seq.hh:40
Struct that defines the information passed from decode to rename.
Definition comm.hh:74
DynInstPtr insts[MaxWidth]
Definition comm.hh:77
Struct that defines the information passed from fetch to decode.
Definition comm.hh:63
DynInstPtr insts[MaxWidth]
Definition comm.hh:66
InstSeqNum fetchFaultSN
Definition comm.hh:68
Struct that defines the information passed from IEW to commit.
Definition comm.hh:90
bool includeSquashInst[MaxThreads]
Definition comm.hh:102
bool branchTaken[MaxThreads]
Definition comm.hh:101
InstSeqNum squashedSeqNum[MaxThreads]
Definition comm.hh:96
std::unique_ptr< PCStateBase > pc[MaxThreads]
Definition comm.hh:97
bool branchMispredict[MaxThreads]
Definition comm.hh:100
Addr mispredPC[MaxThreads]
Definition comm.hh:95
DynInstPtr mispredictInst[MaxThreads]
Definition comm.hh:94
DynInstPtr insts[MaxWidth]
Definition comm.hh:93
bool squash[MaxThreads]
Definition comm.hh:99
DynInstPtr insts[MaxWidth]
Definition comm.hh:109
Struct that defines the information passed from rename to IEW.
Definition comm.hh:82
DynInstPtr insts[MaxWidth]
Definition comm.hh:85
DynInstPtr strictlyOrderedLoad
Hack for now to send back a strictly ordered access to the IEW stage.
Definition comm.hh:193
bool trapPending
If a trap is pending.
Definition comm.hh:223
bool usedROB
Rename should re-read number of free rob entries.
Definition comm.hh:211
unsigned freeROBEntries
Tell Rename how many free entries it has in the ROB.
Definition comm.hh:205
bool clearInterrupt
If the interrupt ended up being cleared before being handled.
Definition comm.hh:221
std::unique_ptr< PCStateBase > pc
The pc of the next instruction to execute.
Definition comm.hh:182
DynInstPtr mispredictInst
Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.
Definition comm.hh:186
bool emptyROB
Notify Rename that the ROB is empty.
Definition comm.hh:214
bool branchTaken
Was the branch taken or not.
Definition comm.hh:217
InstSeqNum doneSeqNum
Represents the instruction that has either been retired or squashed.
Definition comm.hh:202
DynInstPtr squashInst
Instruction that caused the a non-mispredict squash.
Definition comm.hh:189
bool interruptPending
If an interrupt is pending and fetch should stall.
Definition comm.hh:219
InstSeqNum nonSpecSeqNum
Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instructio...
Definition comm.hh:197
bool strictlyOrdered
Hack for now to send back an strictly ordered access to the IEW stage.
Definition comm.hh:227
std::unique_ptr< PCStateBase > nextPC
Definition comm.hh:127
std::unique_ptr< PCStateBase > nextPC
Definition comm.hh:120
bool squash
Signals to redirect BAC if something goes wrong.
Definition comm.hh:119
Struct that defines all backwards communication.
Definition comm.hh:114
bool iewBlock[MaxThreads]
Definition comm.hh:237
bool iewUnblock[MaxThreads]
Definition comm.hh:238
bool decodeBlock[MaxThreads]
Definition comm.hh:233
DecodeComm decodeInfo[MaxThreads]
Definition comm.hh:140
FetchComm fetchInfo[MaxThreads]
Definition comm.hh:123
RenameComm renameInfo[MaxThreads]
Definition comm.hh:144
bool renameUnblock[MaxThreads]
Definition comm.hh:236
bool decodeUnblock[MaxThreads]
Definition comm.hh:234
IewComm iewInfo[MaxThreads]
Definition comm.hh:163
bool renameBlock[MaxThreads]
Definition comm.hh:235
CommitComm commitInfo[MaxThreads]
Definition comm.hh:231

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