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| class | Checker |
| | Specific non-templated derived class used for SimObject configuration. More...
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| class | Commit |
| | Commit handles single threaded and SMT commit. More...
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| class | CPU |
| | O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More...
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| class | Decode |
| | Decode class handles both single threaded and SMT decode. More...
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| struct | DecodeStruct |
| | Struct that defines the information passed from decode to rename. More...
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| class | DependencyEntry |
| | Node in a linked list. More...
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| class | DependencyGraph |
| | Array of linked list that maintains the dependencies between producing instructions and consuming instructions. More...
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| class | DynInst |
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| class | ElasticTrace |
| | The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU. More...
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| class | Fetch |
| | Fetch class handles both single threaded and SMT fetch. More...
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| struct | FetchStruct |
| | Struct that defines the information passed from fetch to decode. More...
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| class | FUPool |
| | Pool of FU's, specific to the new CPU model. More...
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| class | IEW |
| | IEW handles both single threaded and SMT IEW (issue/execute/writeback). More...
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| struct | IEWStruct |
| | Struct that defines the information passed from IEW to commit. More...
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| class | InstructionQueue |
| | A standard instruction queue class. More...
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| struct | IssueStruct |
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| class | LSQ |
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| class | LSQUnit |
| | Class that implements the actual LQ and SQ for each specific thread. More...
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| struct | ltseqnum |
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| class | MemDepUnit |
| | Memory dependency unit class. More...
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| class | PhysRegFile |
| | Simple physical register file class. More...
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| class | Rename |
| | Rename handles both single threaded and SMT rename. More...
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| struct | RenameStruct |
| | Struct that defines the information passed from rename to IEW. More...
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| class | ROB |
| | ROB class. More...
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| class | Scoreboard |
| | Implements a simple scoreboard to track which registers are ready. More...
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| class | SimpleFreeList |
| | Free list for a single class of registers (e.g., integer or floating point). More...
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| class | SimpleRenameMap |
| | Register rename map for a single class of registers (e.g., integer or floating point). More...
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| class | SimpleTrace |
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| class | StoreSet |
| | Implements a store set predictor for determining if memory instructions are dependent upon each other. More...
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| class | ThreadContext |
| | Derived ThreadContext class for use with the O3CPU. More...
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| class | ThreadState |
| | Class that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc. More...
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| struct | TimeStruct |
| | Struct that defines all backwards communication. More...
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| class | UnifiedFreeList |
| | FreeList class that simply holds the list of free integer and floating point registers. More...
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| class | UnifiedRenameMap |
| | Unified register rename map for all classes of registers. More...
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