gem5 [DEVELOP-FOR-25.1]
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gem5::o3::TimeStruct::CommitComm Struct Reference

#include <comm.hh>

Public Attributes

std::unique_ptr< PCStateBasepc
 The pc of the next instruction to execute.
DynInstPtr mispredictInst
 Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.
DynInstPtr squashInst
 Instruction that caused the a non-mispredict squash.
DynInstPtr strictlyOrderedLoad
 Hack for now to send back a strictly ordered access to the IEW stage.
InstSeqNum nonSpecSeqNum = 0
 Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction.
InstSeqNum doneSeqNum = 0
 Represents the instruction that has either been retired or squashed.
unsigned freeROBEntries = 0
 Tell Rename how many free entries it has in the ROB.
bool squash = false
bool robSquashing = false
bool usedROB = false
 Rename should re-read number of free rob entries.
bool emptyROB = false
 Notify Rename that the ROB is empty.
bool branchTaken = false
 Was the branch taken or not.
bool interruptPending = false
 If an interrupt is pending and fetch should stall.
bool clearInterrupt = false
 If the interrupt ended up being cleared before being handled.
bool trapPending = false
 If a trap is pending.
bool strictlyOrdered = false
 Hack for now to send back an strictly ordered access to the IEW stage.

Detailed Description

Definition at line 165 of file comm.hh.

Member Data Documentation

◆ branchTaken

bool gem5::o3::TimeStruct::CommitComm::branchTaken = false

Was the branch taken or not.

Definition at line 217 of file comm.hh.

◆ clearInterrupt

bool gem5::o3::TimeStruct::CommitComm::clearInterrupt = false

If the interrupt ended up being cleared before being handled.

Definition at line 221 of file comm.hh.

◆ doneSeqNum

InstSeqNum gem5::o3::TimeStruct::CommitComm::doneSeqNum = 0

Represents the instruction that has either been retired or squashed.

Similar to having a single bus that broadcasts the retired or squashed sequence number.

Definition at line 202 of file comm.hh.

◆ emptyROB

bool gem5::o3::TimeStruct::CommitComm::emptyROB = false

Notify Rename that the ROB is empty.

Definition at line 214 of file comm.hh.

◆ freeROBEntries

unsigned gem5::o3::TimeStruct::CommitComm::freeROBEntries = 0

Tell Rename how many free entries it has in the ROB.

Definition at line 205 of file comm.hh.

◆ interruptPending

bool gem5::o3::TimeStruct::CommitComm::interruptPending = false

If an interrupt is pending and fetch should stall.

Definition at line 219 of file comm.hh.

◆ mispredictInst

DynInstPtr gem5::o3::TimeStruct::CommitComm::mispredictInst

Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.

Definition at line 186 of file comm.hh.

◆ nonSpecSeqNum

InstSeqNum gem5::o3::TimeStruct::CommitComm::nonSpecSeqNum = 0

Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction.

Definition at line 197 of file comm.hh.

◆ pc

std::unique_ptr<PCStateBase> gem5::o3::TimeStruct::CommitComm::pc

The pc of the next instruction to execute.

This is the next instruction for a branch mispredict, but the same instruction for order violation and the like

Definition at line 182 of file comm.hh.

◆ robSquashing

bool gem5::o3::TimeStruct::CommitComm::robSquashing = false

Definition at line 208 of file comm.hh.

◆ squash

bool gem5::o3::TimeStruct::CommitComm::squash = false

Definition at line 207 of file comm.hh.

◆ squashInst

DynInstPtr gem5::o3::TimeStruct::CommitComm::squashInst

Instruction that caused the a non-mispredict squash.

Definition at line 189 of file comm.hh.

◆ strictlyOrdered

bool gem5::o3::TimeStruct::CommitComm::strictlyOrdered = false

Hack for now to send back an strictly ordered access to the IEW stage.

Definition at line 227 of file comm.hh.

◆ strictlyOrderedLoad

DynInstPtr gem5::o3::TimeStruct::CommitComm::strictlyOrderedLoad

Hack for now to send back a strictly ordered access to the IEW stage.

Definition at line 193 of file comm.hh.

◆ trapPending

bool gem5::o3::TimeStruct::CommitComm::trapPending = false

If a trap is pending.

Definition at line 223 of file comm.hh.

◆ usedROB

bool gem5::o3::TimeStruct::CommitComm::usedROB = false

Rename should re-read number of free rob entries.

Definition at line 211 of file comm.hh.


The documentation for this struct was generated from the following file:

Generated on Mon Oct 27 2025 04:13:21 for gem5 by doxygen 1.14.0