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gem5 [DEVELOP-FOR-25.0]
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#include <bitset>#include <map>#include "arch/riscv/interrupts.hh"#include "dev/io_device.hh"#include "dev/reg_bank.hh"#include "mem/packet.hh"#include "mem/packet_access.hh"#include "params/Plic.hh"#include "params/PlicBase.hh"#include "sim/system.hh"Go to the source code of this file.
Classes | |
| struct | gem5::PlicOutput |
| NOTE: This implementation of PLIC is based on he riscv-plic-spec repository: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0. More... | |
| class | gem5::PlicBase |
| class | gem5::Plic |
| class | gem5::Plic::PlicRegisters |
| MMIO Registers. More... | |
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |