isa.cc File Reference

#include "arch/riscv/isa.hh"
#include <ctime>
#include <set>
#include <sstream>
#include "arch/riscv/faults.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/interrupts.hh"
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pmp.hh"
#include "arch/riscv/pcstate.hh"
#include "arch/riscv/regs/float.hh"
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/regs/misc.hh"
#include "arch/riscv/regs/vector.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
#include "debug/LLSC.hh"
#include "debug/MatRegs.hh"
#include "debug/RiscvMisc.hh"
#include "debug/VecRegs.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/RiscvISA.hh"
#include "sim/pseudo_inst.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::RiscvISA

Functions
std::ostream &	operator<< (std::ostream &os, gem5::RiscvISA::PrivilegeMode pm)

Variables
const std::array< const char *, NUM_MISCREGS >	gem5::RiscvISA::MiscRegNames

Function Documentation

operator<<()

std::ostream & operator<<	(	std::ostream &	os,
		gem5::RiscvISA::PrivilegeMode	pm )

Definition at line 1086 of file isa.cc.

References gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, and gem5::RiscvISA::PRV_U.

Referenced by sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_signed::operator<<, sc_dt::sc_unsigned::operator<<, sc_dt::sc_unsigned::operator<<, sc_dt::sc_unsigned::operator<<, and sc_dt::sc_unsigned::operator<<.