gem5 [DEVELOP-FOR-25.1]
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rv_ctrl.cc
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1/*
2 * Copyright (c) 2010, 2013, 2015, 2021 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "dev/arm/rv_ctrl.hh"
39
40#include "base/trace.hh"
41#include "debug/RVCTRL.hh"
42#include "mem/packet.hh"
43#include "mem/packet_access.hh"
44#include "params/RealViewCtrl.hh"
45#include "params/RealViewOsc.hh"
46#include "params/RealViewTemperatureSensor.hh"
48#include "sim/system.hh"
49#include "sim/voltage_domain.hh"
50
51namespace gem5
52{
53
55 : BasicPioDevice(p, 0xD4), flags(0), scData(0)
56{
57}
58
59Tick
61{
62 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
63 assert(pkt->getSize() == 4);
64 Addr daddr = pkt->getAddr() - pioAddr;
65
66 switch(daddr) {
67 case ProcId0:
68 pkt->setLE(params().proc_id0);
69 break;
70 case ProcId1:
71 pkt->setLE(params().proc_id1);
72 break;
73 case Clock24:
74 Tick clk;
75 clk = sim_clock::as_float::MHz * curTick() * 24;
76 pkt->setLE((uint32_t)(clk));
77 break;
78 case Clock100:
79 Tick clk100;
80 clk100 = sim_clock::as_float::MHz * curTick() * 100;
81 pkt->setLE((uint32_t)(clk100));
82 break;
83 case Flash:
84 pkt->setLE<uint32_t>(0);
85 break;
86 case Clcd:
87 pkt->setLE<uint32_t>(0x00001F00);
88 break;
89 case Osc0:
90 pkt->setLE<uint32_t>(0x00012C5C);
91 break;
92 case Osc1:
93 pkt->setLE<uint32_t>(0x00002CC0);
94 break;
95 case Osc2:
96 pkt->setLE<uint32_t>(0x00002C75);
97 break;
98 case Osc3:
99 pkt->setLE<uint32_t>(0x00020211);
100 break;
101 case Osc4:
102 pkt->setLE<uint32_t>(0x00002C75);
103 break;
104 case Lock:
105 pkt->setLE<uint32_t>(sysLock);
106 break;
107 case Flags:
108 pkt->setLE<uint32_t>(flags);
109 break;
110 case IdReg:
111 pkt->setLE<uint32_t>(params().idreg);
112 break;
113 case CfgStat:
114 pkt->setLE<uint32_t>(1);
115 break;
116 case CfgData:
117 pkt->setLE<uint32_t>(scData);
118 DPRINTF(RVCTRL, "Read %#x from SCReg\n", scData);
119 break;
120 case CfgCtrl:
121 pkt->setLE<uint32_t>(0); // not busy
122 DPRINTF(RVCTRL, "Read 0 from CfgCtrl\n");
123 break;
124 default:
125 warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
126 daddr);
127 pkt->setLE<uint32_t>(0);
128 break;
129 }
130 pkt->makeAtomicResponse();
131 return pioDelay;
132
133}
134
135Tick
137{
138 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
139
140 Addr daddr = pkt->getAddr() - pioAddr;
141 switch (daddr) {
142 case Flash:
143 case Clcd:
144 case Osc0:
145 case Osc1:
146 case Osc2:
147 case Osc3:
148 case Osc4:
149 break;
150 case Lock:
151 sysLock.lockVal = pkt->getLE<uint16_t>();
152 break;
153 case ResetCtl:
154 // Ignore writes to reset control
155 warn_once("Ignoring write to reset control\n");
156 break;
157 case Flags:
158 flags = pkt->getLE<uint32_t>();
159 break;
160 case FlagsClr:
161 flags = 0;
162 break;
163 case CfgData:
164 scData = pkt->getLE<uint32_t>();
165 break;
166 case CfgCtrl: {
167 // A request is being submitted to read/write the system control
168 // registers. See
169 // http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CACDEFGH.html
170 CfgCtrlReg req = pkt->getLE<uint32_t>();
171 if (!req.start) {
172 DPRINTF(RVCTRL, "SCReg: write %#x to ctrl but not starting\n",
173 req);
174 break;
175 }
176
177 auto it_dev(devices.find(req & CFG_CTRL_ADDR_MASK));
178 if (it_dev == devices.end()) {
179 warn_once("SCReg: Access to unknown device "
180 "dcc%d:site%d:pos%d:fn%d:dev%d\n",
181 req.dcc, req.site, req.pos, req.func, req.dev);
182 break;
183 }
184
185 // Service the request as a read or write depending on the
186 // wr bit in the control register.
187 Device &dev(*it_dev->second);
188 if (req.wr) {
189 DPRINTF(RVCTRL, "SCReg: Writing %#x (ctrlWr %#x)\n",
190 scData, req);
191 dev.write(scData);
192
193 } else {
194 scData = dev.read();
195 DPRINTF(RVCTRL, "SCReg: Reading %#x (ctrlRd %#x)\n",
196 scData, req);
197 }
198 } break;
199 case CfgStat: // Weird to write this
200 default:
201 warn("Tried to write RVIO at offset %#x (data %#x) that doesn't exist\n",
202 daddr, pkt->getLE<uint32_t>());
203 break;
204 }
205 pkt->makeAtomicResponse();
206 return pioDelay;
207}
208
209void
214
215void
220
221void
223 uint8_t dcc, uint16_t dev,
224 Device *handler)
225{
226 CfgCtrlReg addr = 0;
227 addr.func = func;
228 addr.site = site;
229 addr.pos = pos;
230 addr.dcc = dcc;
231 addr.dev = dev;
232
233 if (devices.find(addr) != devices.end()) {
234 fatal("Platform device dcc%d:site%d:pos%d:fn%d:dev%d "
235 "already registered.",
236 addr.dcc, addr.site, addr.pos, addr.func, addr.dev);
237 }
238
239 devices[addr] = handler;
240}
241
242
243RealViewOsc::RealViewOsc(const RealViewOscParams &p)
244 : ClockDomain(p, p.voltage_domain),
245 RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_OSC,
246 p.site, p.position, p.dcc, p.device)
247{
248 if (sim_clock::as_float::s / p.freq > UINT32_MAX) {
249 fatal("Oscillator frequency out of range: %f\n",
250 sim_clock::as_float::s / p.freq / 1E6);
251 }
252
253 _clockPeriod = p.freq;
254}
255
256void
258{
259 // Tell dependent object to set their clock frequency
260 for (auto m : members)
261 m->updateClockPeriod();
262}
263
264void
269
270void
275
276void
278{
279 panic_if(clock_period == 0, "%s has a clock period of zero\n", name());
280
281 // Align all members to the current tick
282 for (auto m : members)
283 m->updateClockPeriod();
284
285 _clockPeriod = clock_period;
286
287 // inform any derived clocks they need to updated their period
288 for (auto m : children)
289 m->updateClockPeriod();
290}
291
292uint32_t
294{
295 const uint32_t freq(sim_clock::as_float::s / _clockPeriod);
296 DPRINTF(RVCTRL, "Reading OSC frequency: %f MHz\n", freq / 1E6);
297 return freq;
298}
299
300void
301RealViewOsc::write(uint32_t freq)
302{
303 DPRINTF(RVCTRL, "Setting new OSC frequency: %f MHz\n", freq / 1E6);
305}
306
308 const RealViewTemperatureSensorParams &p)
309 : SimObject(p),
310 RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_TEMP, p.site,
311 p.position, p.dcc, p.device),
313{}
314
315uint32_t
317{
318 // Temperature reported in uC
319 ThermalModel * tm = system->getThermalModel();
320 if (tm) {
321 double t = tm->getTemperature().toCelsius();
322 if (t < 0)
323 warn("Temperature below zero!\n");
324 return fmax(0, t) * 1000000;
325 }
326
327 // Report a dummy 25 degrees temperature
328 return 25000000;
329}
330
331} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:209
Addr pioAddr
Address that the device listens to.
Definition io_device.hh:151
BasicPioDevice(const Params &p, Addr size)
Definition io_device.cc:75
Tick pioDelay
Delay that the device experinces on an access.
Definition io_device.hh:157
Addr pioSize
Size that the device's address range.
Definition io_device.hh:154
std::vector< DerivedClockDomain * > children
Pointers to potential derived clock domains so we can propagate changes.
ClockDomain(const Params &p, VoltageDomain *voltage_domain)
Tick _clockPeriod
Pre-computed clock period in ticks.
Tick clockPeriod() const
Get the clock period.
std::vector< Clocked * > members
Pointers to members of this clock domain, so that when the clock period changes, we can update each m...
virtual std::string name() const
Definition named.hh:60
Addr getAddr() const
Definition packet.hh:807
void setLE(T v)
Set the value in the data pointer to v as little endian.
unsigned getSize() const
Definition packet.hh:817
void makeAtomicResponse()
Definition packet.hh:1074
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
PioDeviceParams Params
Definition io_device.hh:134
Device(RealViewCtrl &parent, DeviceFunc func, uint8_t site, uint8_t pos, uint8_t dcc, uint16_t dev)
Definition rv_ctrl.hh:77
void registerDevice(DeviceFunc func, uint8_t site, uint8_t pos, uint8_t dcc, uint16_t dev, Device *handler)
Definition rv_ctrl.cc:222
Bitfield< 29, 26 > dcc
Definition rv_ctrl.hh:141
SysLockReg sysLock
Definition rv_ctrl.hh:148
Tick write(PacketPtr pkt) override
All writes are simply ignored.
Definition rv_ctrl.cc:136
Bitfield< 15, 12 > pos
Definition rv_ctrl.hh:138
uint32_t scData
This register contains the result from a system control reg access.
Definition rv_ctrl.hh:159
Tick read(PacketPtr pkt) override
Handle a read to the device.
Definition rv_ctrl.cc:60
uint32_t flags
This register is used for smp booting.
Definition rv_ctrl.hh:155
RealViewCtrl(const Params &p)
The constructor for RealView just registers itself with the MMU.
Definition rv_ctrl.cc:54
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition rv_ctrl.cc:216
Bitfield< 17, 16 > site
Definition rv_ctrl.hh:139
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition rv_ctrl.cc:210
Bitfield< 25, 20 > func
Definition rv_ctrl.hh:140
std::map< uint32_t, Device * > devices
Definition rv_ctrl.hh:193
void startup() override
startup() is the final initialization call before simulation.
Definition rv_ctrl.cc:257
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition rv_ctrl.cc:271
RealViewOsc(const RealViewOscParams &p)
Definition rv_ctrl.cc:243
void write(uint32_t freq) override
Definition rv_ctrl.cc:301
uint32_t read() const override
Definition rv_ctrl.cc:293
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition rv_ctrl.cc:265
RealViewTemperatureSensor(const RealViewTemperatureSensorParams &p)
Definition rv_ctrl.cc:307
uint32_t read() const override
Definition rv_ctrl.cc:316
System * system
The system this RV device belongs to.
Definition rv_ctrl.hh:242
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:232
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:246
const Params & params() const
SimObject(const Params &p)
Definition sim_object.cc:58
#define warn(...)
Definition logging.hh:288
#define warn_once(...)
Definition logging.hh:292
Bitfield< 5 > t
Definition misc_types.hh:71
Bitfield< 0 > m
Bitfield< 0 > p
Bitfield< 32 > tm
Definition misc.hh:112
FloatType fmax(FloatType a, FloatType b)
Definition utility.hh:389
Bitfield< 3 > addr
Definition types.hh:84
double s
These variables equal the number of ticks in the unit of time they're named after in a double.
Definition core.cc:51
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
Packet * PacketPtr
Declaration of the Packet class.
This implements the simple real view registers on a PBXA9.
#define UNSERIALIZE_SCALAR(scalar)
Definition serialize.hh:575
#define SERIALIZE_SCALAR(scalar)
Definition serialize.hh:568

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