smmu_v3.hh

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#ifndef __DEV_ARM_SMMU_V3_HH__
#define __DEV_ARM_SMMU_V3_HH__
 
#include <list>
#include <map>
#include <queue>
#include <string>
#include <vector>
 
#include "base/statistics.hh"
#include "dev/arm/smmu_v3_caches.hh"
#include "dev/arm/smmu_v3_cmdexec.hh"
#include "dev/arm/smmu_v3_defs.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "mem/packet.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"

 
namespace gem5
{
 
class ArmInterruptPin;
class SMMUTranslationProcess;
class System;
 
struct SMMUv3Params;
 
class SMMUv3 : public ClockedObject
{
  protected:
 
    friend class SMMUProcess;
    friend class SMMUTranslationProcess;
    friend class SMMUCommandExecProcess;
    friend class SMMUv3DeviceInterface;
 
    const System &system;
    const RequestorID requestorId;
 
    SMMURequestPort    requestPort;
    SMMUTableWalkPort tableWalkPort;
    SMMUControlPort   controlPort;
 
    // This could be nullptr if wired implementation of the
    // event queue interrupt is not supported
    ArmInterruptPin * const eventqInterrupt;
 
    ARMArchTLB  tlb;
    ConfigCache configCache;
    IPACache    ipaCache;
    WalkCache   walkCache;
 
    const bool tlbEnable;
    const bool configCacheEnable;
    const bool ipaCacheEnable;
    const bool walkCacheEnable;
    bool tableWalkPortEnable;
 
    const bool walkCacheNonfinalEnable;
    const unsigned walkCacheS1Levels;
    const unsigned walkCacheS2Levels;
    const unsigned requestPortWidth; // in bytes
 
    SMMUSemaphore tlbSem;
    SMMUSemaphore ifcSmmuSem;
    SMMUSemaphore smmuIfcSem;
    SMMUSemaphore configSem;
    SMMUSemaphore ipaSem;
    SMMUSemaphore walkSem;
    SMMUSemaphore requestPortSem;
 
    SMMUSemaphore transSem; // max N transactions in SMMU
    SMMUSemaphore ptwSem; // max N concurrent PTWs
    SMMUSemaphore cycleSem; // max 1 table walk per cycle
 
    // Timing parameters
    const Cycles tlbLat;
    const Cycles ifcSmmuLat;
    const Cycles smmuIfcLat;
    const Cycles configLat;
    const Cycles ipaLat;
    const Cycles walkLat;
 
    // Stats
    struct SMMUv3Stats : public statistics::Group
    {
        SMMUv3Stats(statistics::Group *parent);
        statistics::Scalar steL1Fetches;
        statistics::Scalar steFetches;
        statistics::Scalar cdL1Fetches;
        statistics::Scalar cdFetches;
        statistics::Distribution translationTimeDist;
        statistics::Distribution ptwTimeDist;
    } stats;
 
    std::vector<SMMUv3DeviceInterface *> deviceInterfaces;
 
    SMMUCommandExecProcess commandExecutor;
 
    const AddrRange regsMap;
    SMMURegs regs;
 
    bool inSecureBlock(uint32_t offs) const;
 
    std::queue<SMMUAction> packetsToRetry;
    std::queue<SMMUAction> packetsTableWalkToRetry;
 
 
    void scheduleDeviceRetries();
 
    SMMUAction runProcess(SMMUProcess *proc, PacketPtr pkt);
    SMMUAction runProcessAtomic(SMMUProcess *proc, PacketPtr pkt);
    SMMUAction runProcessTiming(SMMUProcess *proc, PacketPtr pkt);
 
    void processCommands();
    MemberEventWrapper<&SMMUv3::processCommands> processCommandsEvent;
 
    void processCommand(const SMMUCommand &cmd);
 
  public:
    SMMUv3(const SMMUv3Params &p);
    virtual ~SMMUv3() {}
 
    virtual void init() override;
 
    Tick recvAtomic(PacketPtr pkt, PortID id);
    bool recvTimingReq(PacketPtr pkt, PortID id);
    bool recvTimingResp(PacketPtr pkt);
    void recvReqRetry();
 
    bool tableWalkRecvTimingResp(PacketPtr pkt);
    void tableWalkRecvReqRetry();
 
    Tick readControl(PacketPtr pkt);
    Tick writeControl(PacketPtr pkt);
 
    DrainState drain() override;
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
    virtual Port &getPort(const std::string &name,
                          PortID id = InvalidPortID) override;
};
 
} // namespace gem5
 
#endif /* __DEV_ARM_SMMU_V3_HH__ */