standard.cc

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/*
 * Copyright (c) 2015 RISC-V Foundation
 * Copyright (c) 2017 The University of Virginia
 * Copyright (c) 2020 Barkhausen Institut
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include "arch/riscv/insts/standard.hh"
 
#include <sstream>
#include <string>
 
#include "arch/riscv/faults.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/regs/misc.hh"
#include "arch/riscv/semihosting.hh"
#include "arch/riscv/utility.hh"
#include "cpu/static_inst.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
std::string
RegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
        registerName(srcRegIdx(0));
    if (_numSrcRegs >= 2)
        ss << ", " << registerName(srcRegIdx(1));
    if (_numSrcRegs >= 3)
        ss << ", " << registerName(srcRegIdx(2));
    return ss.str();
}
 
std::string
CSROp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
    auto data = CSRData.find(csr);
    if (data != CSRData.end())
        ss << data->second.name;
    else
        ss << "?? (" << std::hex << "0x" << csr << std::dec << ")";
    if (_numSrcRegs > 0)
        ss << ", " << registerName(srcRegIdx(0));
    else
        ss << uimm;
    return ss.str();
}
 
std::string
SystemOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
    if (strcmp(mnemonic, "fence_vma") == 0) {
        std::stringstream ss;
        ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " <<
            registerName(srcRegIdx(1));
        return ss.str();
    }
 
    return mnemonic;
}
 
Fault
SystemOp::executeEBreakOrSemihosting(ExecContext *xc) const
{
    // If semihosting is enabled, we may need to execute a semihosting
    // operation instead of raising a breakpoint fault.
    ThreadContext *tc = xc->tcBase();
    if (auto *semihosting = dynamic_cast<RiscvSemihosting *>(
                tc->getSystemPtr()->workload->getSemihosting())) {
        if (semihosting->isSemihostingEBreak(xc) && semihosting->call(tc)) {
            return NoFault;
        }
    }
    // No semihosting, raise a standard breakpoint exception.
    MISA misa = xc->readMiscReg(MISCREG_ISA);
    bool virtualized = misa.rvh ? virtualizationEnabled(xc) : false;
    return std::make_shared<BreakpointFault>(xc->pcState(), virtualized);
}
 
} // namespace RiscvISA
} // namespace gem5