gem5::ArmISA::MMU::CachedState Struct Reference

#include <mmu.hh>

Public Member Functions
	CachedState (MMU *_mmu, bool stage2)
CachedState &	operator= (const CachedState &rhs)
void	updateMiscReg (ThreadContext *tc, ArmTranslationType tran_type)
vmid_t	getVMID (ThreadContext *tc) const
	Returns the current VMID (information stored in the VTTBR_EL2 register)

Public Attributes
MMU *	mmu
bool	isStage2 = false
CPSR	cpsr = 0
bool	aarch64 = false
ExceptionLevel	exceptionLevel = EL0
TranslationRegime	currRegime = TranslationRegime::EL10
SCTLR	sctlr = 0
SCR	scr = 0
bool	isPriv = false
SecurityState	securityState = SecurityState::NonSecure
TTBCR	ttbcr = 0
TCR2	tcr2 = 0
RegVal	pir = 0
RegVal	pire0 = 0
bool	pie = false
uint16_t	asid = 0
vmid_t	vmid = 0
PRRR	prrr = 0
NMRR	nmrr = 0
HCR	hcr = 0
uint32_t	dacr = 0
bool	miscRegValid = false
ArmTranslationType	curTranType = NormalTran
bool	stage2Req = false
bool	stage2DescReq = false
bool	directToStage2 = false
Memoizer< int, ThreadContext *, bool, bool, TCR, ExceptionLevel >	computeAddrTop

Detailed Description

Definition at line 129 of file mmu.hh.

Constructor & Destructor Documentation

CachedState()

gem5::ArmISA::MMU::CachedState::CachedState ( MMU * _mmu, bool stage2 )

inline

Definition at line 131 of file mmu.hh.

References computeAddrTop, isStage2, gem5::ArmISA::MMU::MMU(), and mmu.

Referenced by operator=().

Member Function Documentation

getVMID()

vmid_t gem5::MMU::CachedState::getVMID

(

ThreadContext *

tc

)

const

Returns the current VMID (information stored in the VTTBR_EL2 register)

Definition at line 1351 of file mmu.cc.

References gem5::bits(), gem5::ArmISA::EL2, gem5::ArmISA::ELIs64(), gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_VTCR_EL2, gem5::ArmISA::MISCREG_VTTBR_EL2, panic, gem5::ThreadContext::readMiscReg(), and vmid.

Referenced by updateMiscReg().

operator=()

CachedState & gem5::ArmISA::MMU::CachedState::operator= ( const CachedState & rhs )

inline

Definition at line 137 of file mmu.hh.

References aarch64, asid, CachedState(), computeAddrTop, cpsr, currRegime, curTranType, dacr, directToStage2, exceptionLevel, hcr, isPriv, isStage2, miscRegValid, nmrr, pie, pir, pire0, prrr, scr, sctlr, securityState, stage2DescReq, stage2Req, tcr2, ttbcr, and vmid.

updateMiscReg()

void gem5::MMU::CachedState::updateMiscReg	(	ThreadContext *	tc,
		ArmTranslationType	tran_type )

Definition at line 1420 of file mmu.cc.

References aarch64, asid, gem5::bits(), cpsr, currRegime, curTranType, dacr, directToStage2, gem5::ArmISA::EL0, gem5::ArmISA::EL10, gem5::ArmISA::EL2, gem5::ArmISA::EL20, gem5::ArmISA::EL2Enabled(), gem5::ArmISA::EL3, gem5::ArmISA::ELIs64(), exceptionLevel, getVMID(), gem5::ArmISA::HaveExt(), hcr, gem5::ArmISA::MMU::HypMode, isPriv, gem5::ArmISA::isSecure(), isStage2, gem5::ArmISA::longDescFormatInUse(), gem5::ArmISA::MISCREG_CONTEXTIDR, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_DACR, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_PIR_EL1, gem5::ArmISA::MISCREG_PIR_EL2, gem5::ArmISA::MISCREG_PIR_EL3, gem5::ArmISA::MISCREG_PIRE0_EL1, gem5::ArmISA::MISCREG_PIRE0_EL2, gem5::ArmISA::MISCREG_PRRR, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR, gem5::ArmISA::MISCREG_SCTLR_EL1, gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL3, gem5::ArmISA::MISCREG_TCR2_EL1, gem5::ArmISA::MISCREG_TCR2_EL2, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_TCR_EL3, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::MISCREG_TTBR0, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL2, gem5::ArmISA::MISCREG_TTBR1, gem5::ArmISA::MISCREG_TTBR1_EL1, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_VTTBR, miscRegValid, mmu, gem5::ArmISA::MODE_USER, nmrr, gem5::ArmISA::NonSecure, pie, pir, pire0, prrr, gem5::ThreadContext::readMiscReg(), gem5::ArmISA::MMU::S1CTran, gem5::ArmISA::MMU::S1E1Tran, gem5::ArmISA::MMU::S1S2NsTran, scr, sctlr, gem5::ArmISA::Secure, securityState, gem5::ArmISA::snsBankedIndex(), stage2DescReq, stage2Req, tcr2, gem5::ArmISA::translationEl(), gem5::ArmISA::translationRegime(), gem5::ArmISA::MMU::tranTypeEL(), ttbcr, gem5::ArmISA::vm, and vmid.

Member Data Documentation

aarch64

bool gem5::ArmISA::MMU::CachedState::aarch64 = false

Definition at line 180 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::MMU::getResultTe(), gem5::ArmISA::MMU::getTE(), operator=(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateSe(), and updateMiscReg().

asid

uint16_t gem5::ArmISA::MMU::CachedState::asid = 0

Definition at line 192 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::getTE(), operator=(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateFunctional(), and updateMiscReg().

computeAddrTop

Memoizer<int, ThreadContext*, bool, bool, TCR, ExceptionLevel> gem5::ArmISA::MMU::CachedState::computeAddrTop

Definition at line 215 of file mmu.hh.

Referenced by CachedState(), operator=(), and gem5::ArmISA::MMU::purifyTaggedAddr().

cpsr

CPSR gem5::ArmISA::MMU::CachedState::cpsr = 0

Definition at line 179 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), and updateMiscReg().

currRegime

TranslationRegime gem5::ArmISA::MMU::CachedState::currRegime = TranslationRegime::EL10

Definition at line 182 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::getTE(), operator=(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), gem5::ArmISA::MMU::translateFunctional(), and updateMiscReg().

curTranType

ArmTranslationType gem5::ArmISA::MMU::CachedState::curTranType = NormalTran

Definition at line 199 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::MMU::getResultTe(), operator=(), and updateMiscReg().

dacr

uint32_t gem5::ArmISA::MMU::CachedState::dacr = 0

Definition at line 197 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), operator=(), and updateMiscReg().

directToStage2

bool gem5::ArmISA::MMU::CachedState::directToStage2 = false

Definition at line 212 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::translateFunctional(), and updateMiscReg().

exceptionLevel

ExceptionLevel gem5::ArmISA::MMU::CachedState::exceptionLevel = EL0

Definition at line 181 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::MMU::getTE(), operator=(), gem5::ArmISA::MMU::s2PermBits64(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateSe(), and updateMiscReg().

hcr

HCR gem5::ArmISA::MMU::CachedState::hcr = 0

Definition at line 196 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), operator=(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), and updateMiscReg().

isPriv

bool gem5::ArmISA::MMU::CachedState::isPriv = false

Definition at line 185 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), operator=(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), gem5::ArmISA::MMU::testTranslation(), gem5::ArmISA::MMU::translateFs(), and updateMiscReg().

isStage2

bool gem5::ArmISA::MMU::CachedState::isStage2 = false

Definition at line 178 of file mmu.hh.

Referenced by CachedState(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::MMU::getResultTe(), gem5::ArmISA::MMU::getTE(), operator=(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateMmuOn(), gem5::ArmISA::MMU::translateSe(), and updateMiscReg().

miscRegValid

bool gem5::ArmISA::MMU::CachedState::miscRegValid = false

Definition at line 198 of file mmu.hh.

Referenced by operator=(), and updateMiscReg().

mmu

MMU* gem5::ArmISA::MMU::CachedState::mmu

Definition at line 177 of file mmu.hh.

Referenced by CachedState(), and updateMiscReg().

nmrr

NMRR gem5::ArmISA::MMU::CachedState::nmrr = 0

Definition at line 195 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::translateMmuOff(), and updateMiscReg().

pie

bool gem5::ArmISA::MMU::CachedState::pie = false

Definition at line 191 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::s1PermBits64(), and updateMiscReg().

pir

RegVal gem5::ArmISA::MMU::CachedState::pir = 0

Definition at line 189 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::s1IndirectPermBits64(), and updateMiscReg().

pire0

RegVal gem5::ArmISA::MMU::CachedState::pire0 = 0

Definition at line 190 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::s1IndirectPermBits64(), and updateMiscReg().

prrr

PRRR gem5::ArmISA::MMU::CachedState::prrr = 0

Definition at line 194 of file mmu.hh.

Referenced by operator=(), gem5::ArmISA::MMU::translateMmuOff(), and updateMiscReg().

scr

SCR gem5::ArmISA::MMU::CachedState::scr = 0

Definition at line 184 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), operator=(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), gem5::ArmISA::MMU::s2PermBits64(), gem5::ArmISA::MMU::translateFs(), and updateMiscReg().

sctlr

SCTLR gem5::ArmISA::MMU::CachedState::sctlr = 0

Definition at line 183 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), operator=(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateSe(), and updateMiscReg().

securityState

SecurityState gem5::ArmISA::MMU::CachedState::securityState = SecurityState::NonSecure

Definition at line 186 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::getResultTe(), operator=(), gem5::ArmISA::MMU::s1DirectPermBits64(), gem5::ArmISA::MMU::s1IndirectPermBits64(), gem5::ArmISA::MMU::s2PermBits64(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateMmuOn(), and updateMiscReg().

stage2DescReq

bool gem5::ArmISA::MMU::CachedState::stage2DescReq = false

Definition at line 208 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::getTE(), operator=(), and updateMiscReg().

stage2Req

bool gem5::ArmISA::MMU::CachedState::stage2Req = false

Definition at line 202 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::getResultTe(), operator=(), gem5::ArmISA::MMU::translateComplete(), and updateMiscReg().

tcr2

TCR2 gem5::ArmISA::MMU::CachedState::tcr2 = 0

Definition at line 188 of file mmu.hh.

Referenced by operator=(), and updateMiscReg().

ttbcr

TTBCR gem5::ArmISA::MMU::CachedState::ttbcr = 0

Definition at line 187 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::getTE(), operator=(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateSe(), and updateMiscReg().

vmid

vmid_t gem5::ArmISA::MMU::CachedState::vmid = 0

Definition at line 193 of file mmu.hh.

Referenced by gem5::ArmISA::MMU::getTE(), getVMID(), operator=(), gem5::ArmISA::MMU::translateFunctional(), and updateMiscReg().

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The documentation for this struct was generated from the following files:

• arch/arm/mmu.hh
• arch/arm/mmu.cc