gem5::ArmISA::MMU Class Reference

#include <mmu.hh>

Inheritance diagram for gem5::ArmISA::MMU:

Classes
struct	CachedState
struct	Stats

Public Types
enum	ArmFlags {   AlignmentMask = 0x7 , AlignByte = 0x0 , AlignHalfWord = 0x1 , AlignWord = 0x2 ,   AlignDoubleWord = 0x3 , AlignQuadWord = 0x4 , AlignOctWord = 0x5 , AllowUnaligned = 0x8 ,   UserMode = 0x10 }
enum	ArmTranslationType {   NormalTran = 0 , S1CTran = 0x1 , HypMode = 0x2 , S1S2NsTran = 0x4 ,   S1E0Tran = 0x8 , S1E1Tran = 0x10 , S1E2Tran = 0x20 , S1E3Tran = 0x40 ,   S12E0Tran = 0x80 , S12E1Tran = 0x100 }
Public Types inherited from gem5::BaseMMU
enum	Mode { Read , Write , Execute }
Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Public Member Functions
TranslationGenPtr	translateFunctional (Addr start, Addr size, ThreadContext *tc, Mode mode, Request::Flags flags) override
	Returns a translation generator for a region of virtual addresses, instead of directly translating a specific address.
	MMU (const ArmMMUParams &p)
void	init () override
	Called at init time, this method is traversing the TLB hierarchy and pupulating the instruction/data/unified containers accordingly.
bool	translateFunctional (ThreadContext *tc, Addr vaddr, Addr &paddr)
	Do a functional lookup on the TLB (for debugging) and don't modify any internal state.
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type)
	Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state.
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2)
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode) override
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tran_type, bool stage2)
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode, ArmTranslationType tran_type)
void	translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override
void	translateTiming (const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, bool stage2)
void	translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool stage2)
Fault	translateMmuOff (ThreadContext *tc, const RequestPtr &req, Mode mode, ArmTranslationType tran_type, Addr vaddr, bool long_desc_format, CachedState &state)
Fault	translateMmuOn (ThreadContext *tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, TranMethod tran_method, CachedState &state)
Fault	translateFs (const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tran_type, bool functional, CachedState &state)
Fault	translateSe (const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, CachedState &state)
Addr	getValidAddr (Addr vaddr, ThreadContext *tc, Mode mode) override
Fault	translateComplete (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2)
Fault	translateComplete (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tran_type, bool call_from_s2, CachedState &state)
Fault	finalizePhysical (const RequestPtr &req, ThreadContext *tc, Mode mode) const override
void	drainResume () override
	Resume execution after a successful drain.
void	takeOverFrom (BaseMMU *old_mmu) override
void	invalidateMiscReg ()
void	flush (const TLBIOp &tlbi_op)
void	flushStage1 (const TLBIOp &tlbi_op)
void	flushStage2 (const TLBIOp &tlbi_op)
void	iflush (const TLBIOp &tlbi_op)
void	dflush (const TLBIOp &tlbi_op)
void	flushAll () override
uint64_t	getAttr () const
void	setAttr (uint64_t attr)
	Accessor functions for memory attributes for last accessed TLB entry.
const ArmRelease *	release () const
bool	hasWalkCache () const
TlbEntry *	lookup (Addr vpn, uint16_t asn, vmid_t vmid, SecurityState ss, bool functional, bool ignore_asn, TranslationRegime target_regime, bool stage2, BaseMMU::Mode mode)
	Lookup an entry in the TLB.
Fault	getTE (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, SecurityState ss, PASpace ipaspace, ArmTranslationType tran_type, bool stage2)
Fault	getTE (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, SecurityState ss, PASpace ipaspace, ArmTranslationType tran_type, CachedState &state)
Fault	getResultTe (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe, CachedState &state)
Fault	checkPermissions (TlbEntry *te, const RequestPtr &req, Mode mode, bool stage2)
Fault	checkPermissions (TlbEntry *te, const RequestPtr &req, Mode mode, CachedState &state)
Fault	checkPermissions64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, bool stage2)
Fault	checkPermissions64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state)
void	setTestInterface (SimObject *ti)
Fault	testTranslation (const RequestPtr &req, Mode mode, DomainType domain, CachedState &state) const
Public Member Functions inherited from gem5::BaseMMU
virtual void	reset ()
void	demapPage (Addr vaddr, uint64_t asn)
Public Member Functions inherited from gem5::SimObject
const Params &	params () const
	SimObject (const Params &p)
virtual	~SimObject ()
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint.
virtual void	regProbePoints ()
	Register probe points for this object.
virtual void	regProbeListeners ()
	Register probe listeners for this object.
ProbeManager *	getProbeManager ()
	Get the probe manager for this object.
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index.
virtual void	startup ()
	startup() is the final initialization call before simulation.
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.
void	serialize (CheckpointOut &cp) const override
	Serialize an object.
void	unserialize (CheckpointIn &cp) override
	Unserialize an object.
Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	Event manger manages events in the event queue.
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.
virtual void	notifyFork ()
	Notify a child process of a fork.
Public Member Functions inherited from gem5::statistics::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group.
virtual	~Group ()
virtual void	regStats ()
	Callback to set stat parameters.
virtual void	resetStats ()
	Callback to reset stats.
virtual void	preDumpStats ()
	Callback before stats are dumped.
void	addStat (statistics::Info *info)
	Register a stat with this group.
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block.
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.
void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete
Public Member Functions inherited from gem5::Named
	Named (std::string_view name_)
virtual	~Named ()=default
virtual std::string	name () const

Static Public Member Functions
static ExceptionLevel	tranTypeEL (CPSR cpsr, SCR scr, ArmTranslationType type)
	Determine the EL to use for the purpose of a translation given a specific translation type.
static bool	hasUnprivRegime (TranslationRegime regime)
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.
static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes
TlbTestInterface *	test
CachedState	s1State
CachedState	s2State
Public Attributes inherited from gem5::BaseMMU
BaseTLB *	dtb
BaseTLB *	itb

Protected Types
using	LookupLevel = enums::ArmLookupLevel
Protected Types inherited from gem5::BaseMMU
typedef BaseMMUParams	Params

Protected Member Functions
ArmISA::TLB *	getDTBPtr () const
ArmISA::TLB *	getITBPtr () const
TLB *	getTlb (BaseMMU::Mode mode, bool stage2) const
TableWalker *	getTableWalker (BaseMMU::Mode mode, bool stage2) const
Addr	purifyTaggedAddr (Addr vaddr_tainted, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool is_inst, CachedState &state)
std::pair< bool, bool >	s1PermBits64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
std::tuple< bool, bool, bool >	s1IndirectPermBits64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
std::tuple< bool, bool, bool >	s1DirectPermBits64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
std::pair< bool, bool >	s2PermBits64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc, CachedState &state, bool r, bool w, bool x)
bool	checkWalkCache () const
bool	isCompleteTranslation (TlbEntry *te) const
CachedState &	updateMiscReg (ThreadContext *tc, ArmTranslationType tran_type, bool stage2)
Fault	testAndFinalize (const RequestPtr &req, ThreadContext *tc, Mode mode, TlbEntry *te, CachedState &state) const
Protected Member Functions inherited from gem5::BaseMMU
	BaseMMU (const Params &p)
BaseTLB *	getTlb (Mode mode) const
Protected Member Functions inherited from gem5::Drainable
	Drainable ()
virtual	~Drainable ()
void	signalDrainDone () const
	Signal that an object is drained.

Protected Attributes
TLB *	itbStage2
TLB *	dtbStage2
TableWalker *	itbWalker
TableWalker *	dtbWalker
TableWalker *	itbStage2Walker
TableWalker *	dtbStage2Walker
ContextID	miscRegContext
uint64_t	_attr
const ArmRelease *	_release
bool	haveLargeAsid64
uint8_t	physAddrRange
AddrRange	m5opRange
bool	_hasWalkCache
gem5::ArmISA::MMU::Stats	stats
Protected Attributes inherited from gem5::BaseMMU
std::set< BaseTLB * >	instruction
	It is possible from the MMU to traverse the entire hierarchy of TLBs, starting from the DTB and ITB (generally speaking from the first level) up to the last level via the nextLevel pointer.
std::set< BaseTLB * >	data
std::set< BaseTLB * >	unified
Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.
Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Detailed Description

Definition at line 64 of file mmu.hh.

Member Typedef Documentation

LookupLevel

using gem5::ArmISA::MMU::LookupLevel = enums::ArmLookupLevel

protected

Definition at line 67 of file mmu.hh.

Member Enumeration Documentation

ArmFlags

enum gem5::ArmISA::MMU::ArmFlags

Enumerator
AlignmentMask
AlignByte
AlignHalfWord
AlignWord
AlignDoubleWord
AlignQuadWord
AlignOctWord
AllowUnaligned
UserMode

Definition at line 93 of file mmu.hh.

ArmTranslationType

enum gem5::ArmISA::MMU::ArmTranslationType

Enumerator
NormalTran
S1CTran
HypMode
S1S2NsTran
S1E0Tran
S1E1Tran
S1E2Tran
S1E3Tran
S12E0Tran
S12E1Tran

Definition at line 109 of file mmu.hh.

Constructor & Destructor Documentation

MMU()

gem5::MMU::MMU

(

const ArmMMUParams &

p

)

Definition at line 60 of file mmu.cc.

References _attr, _hasWalkCache, _release, gem5::BaseMMU::BaseMMU(), dtbStage2, dtbStage2Walker, dtbWalker, gem5::FullSystem, haveLargeAsid64, gem5::ArmSystem::haveLargeAsid64(), itbStage2, itbStage2Walker, itbWalker, m5opRange, miscRegContext, gem5::MipsISA::p, physAddrRange, gem5::ArmSystem::physAddrRange(), gem5::ArmSystem::releaseFS(), s1State, s2State, stats, and test.

Referenced by gem5::ArmISA::MMU::CachedState::CachedState(), checkPermissions(), checkPermissions64(), getResultTe(), getTE(), s1DirectPermBits64(), s1IndirectPermBits64(), s2PermBits64(), takeOverFrom(), translateComplete(), translateFs(), translateMmuOff(), translateMmuOn(), and updateMiscReg().

Member Function Documentation

checkPermissions() [1/2]

Fault gem5::MMU::checkPermissions	(	TlbEntry *	te,
		const RequestPtr &	req,
		Mode	mode,
		bool	stage2 )

Definition at line 391 of file mmu.cc.

References checkPermissions(), gem5::ArmISA::mode, s1State, s2State, and gem5::ArmISA::te.

Referenced by checkPermissions(), and getResultTe().

checkPermissions() [2/2]

Fault gem5::MMU::checkPermissions	(	TlbEntry *	te,
		const RequestPtr &	req,
		Mode	mode,
		CachedState &	state )

Definition at line 398 of file mmu.cc.

References gem5::ArmISA::ArmFault::AlignmentFault, AlignmentMask, gem5::ArmISA::MMU::CachedState::dacr, gem5::ArmISA::ArmFault::DomainLL, DPRINTF, gem5::BaseMMU::Execute, gem5::ArmISA::MMU::CachedState::hcr, gem5::ArmISA::MMU::CachedState::isPriv, gem5::ArmISA::MMU::CachedState::isStage2, gem5::ArmISA::LpaeTran, gem5::ArmISA::mask, MMU(), gem5::ArmISA::mode, gem5::ArmISA::NoAccess, gem5::NoFault, gem5::ArmISA::TlbEntry::Normal, panic, gem5::ArmISA::ArmFault::PermissionLL, gem5::ArmISA::ArmFault::PrefetchUncacheable, gem5::ArmISA::MMU::CachedState::scr, gem5::ArmISA::MMU::CachedState::sctlr, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, stats, gem5::ArmISA::te, UserMode, gem5::MipsISA::vaddr, gem5::ArmISA::VmsaTran, and gem5::BaseMMU::Write.

checkPermissions64() [1/2]

Fault gem5::MMU::checkPermissions64	(	TlbEntry *	te,
		const RequestPtr &	req,
		Mode	mode,
		ThreadContext *	tc,
		bool	stage2 )

Definition at line 578 of file mmu.cc.

References checkPermissions64(), gem5::ArmISA::mode, s1State, s2State, and gem5::ArmISA::te.

Referenced by checkPermissions64(), and getResultTe().

checkPermissions64() [2/2]

Fault gem5::MMU::checkPermissions64	(	TlbEntry *	te,
		const RequestPtr &	req,
		Mode	mode,
		ThreadContext *	tc,
		CachedState &	state )

Definition at line 585 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::aarch64, gem5::ArmISA::ArmFault::AlignmentFault, AlignmentMask, gem5::ArmISA::MMU::CachedState::curTranType, DPRINTF, gem5::ArmISA::EL0, gem5::ArmISA::MMU::CachedState::exceptionLevel, gem5::BaseMMU::Execute, gem5::ArmISA::MMU::CachedState::hcr, gem5::ArmISA::MMU::CachedState::isStage2, gem5::ArmISA::LpaeTran, gem5::ArmISA::mask, MMU(), gem5::ArmISA::mode, gem5::ArmISA::NoAccess, gem5::NoFault, gem5::ArmISA::TlbEntry::Normal, gem5::ArmISA::ArmFault::PermissionLL, gem5::ArmISA::ArmFault::PrefetchUncacheable, s1PermBits64(), s2PermBits64(), gem5::ArmISA::MMU::CachedState::scr, gem5::ArmISA::MMU::CachedState::sctlr, stats, gem5::ArmISA::te, updateMiscReg(), and gem5::BaseMMU::Write.

checkWalkCache()

bool gem5::MMU::checkWalkCache ( ) const

protected

Definition at line 112 of file mmu.cc.

References gem5::BaseMMU::data, gem5::BaseMMU::instruction, gem5::ArmISA::tlb, and gem5::BaseMMU::unified.

Referenced by init().

dflush()

void gem5::MMU::dflush

(

const TLBIOp &

tlbi_op

)

Definition at line 260 of file mmu.cc.

References gem5::BaseMMU::data, flush(), gem5::ArmISA::tlb, and gem5::BaseMMU::unified.

Referenced by gem5::ArmISA::DTLBIALL::operator()(), gem5::ArmISA::DTLBIASID::operator()(), and gem5::ArmISA::DTLBIMVA::operator()().

drainResume()

void gem5::MMU::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from gem5::Drainable.

Definition at line 131 of file mmu.cc.

References s1State, and s2State.

finalizePhysical()

Fault gem5::MMU::finalizePhysical ( const RequestPtr & req, ThreadContext * tc, Mode mode ) const

overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 302 of file mmu.cc.

References gem5::pseudo_inst::decodeAddrOffset(), gem5::ArmISA::inAArch64(), m5opRange, gem5::ArmISA::mode, gem5::NoFault, gem5::pseudo_inst::pseudoInst(), gem5::BaseMMU::Read, and gem5::Packet::setLE().

Referenced by testAndFinalize(), and translateSe().

flush()

void gem5::MMU::flush

(

const TLBIOp &

tlbi_op

)

Definition at line 216 of file mmu.cc.

References flushStage1(), flushStage2(), gem5::ArmISA::TLBIOp::stage1Flush(), and gem5::ArmISA::TLBIOp::stage2Flush().

Referenced by dflush(), flushStage1(), iflush(), gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::TLBIALLEL::operator()(), gem5::ArmISA::TLBIALLN::operator()(), and gem5::ArmISA::TLBIVMALL::operator()().

flushAll()

void gem5::MMU::flushAll ( )

overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 271 of file mmu.cc.

References dtbStage2, gem5::BaseMMU::flushAll(), and itbStage2.

flushStage1()

void gem5::MMU::flushStage1

(

const TLBIOp &

tlbi_op

)

Definition at line 228 of file mmu.cc.

References gem5::BaseMMU::data, flush(), gem5::BaseMMU::instruction, gem5::ArmISA::tlb, and gem5::BaseMMU::unified.

Referenced by flush(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::TLBIMVA::operator()(), and gem5::ArmISA::TLBIMVAA::operator()().

flushStage2()

void gem5::MMU::flushStage2

(

const TLBIOp &

tlbi_op

)

Definition at line 242 of file mmu.cc.

References dtbStage2, and itbStage2.

Referenced by flush(), and gem5::ArmISA::TLBIIPA::operator()().

getAttr()

uint64_t gem5::ArmISA::MMU::getAttr ( ) const

inline

Definition at line 314 of file mmu.hh.

References _attr.

Referenced by gem5::AtOp64::addressTranslation64().

getDTBPtr()

ArmISA::TLB * gem5::MMU::getDTBPtr ( ) const

protected

Definition at line 138 of file mmu.cc.

References gem5::BaseMMU::dtb.

Referenced by getTlb(), and init().

getITBPtr()

ArmISA::TLB * gem5::MMU::getITBPtr ( ) const

protected

Definition at line 144 of file mmu.cc.

References gem5::BaseMMU::itb.

Referenced by getTlb(), and init().

getResultTe()

Fault gem5::MMU::getResultTe	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		TlbEntry *	mergeTe,
		CachedState &	state )

Definition at line 1704 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::aarch64, gem5::ArmISA::ArmFault::annotate(), checkPermissions(), checkPermissions64(), gem5::ArmISA::MMU::CachedState::curTranType, DPRINTF, getTE(), gem5::ArmISA::Stage2LookUp::getTe(), gem5::ArmISA::Stage2LookUp::isComplete(), isCompleteTranslation(), gem5::ArmISA::MMU::CachedState::isStage2, MMU(), gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::NonSecure, gem5::ArmISA::ArmFault::OVA, gem5::ArmISA::ArmFault::S1PTW, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, gem5::ArmISA::Stage2LookUp::setSelfDelete(), gem5::ArmISA::MMU::CachedState::stage2Req, and gem5::ArmISA::te.

Referenced by translateMmuOn().

getTableWalker()

TableWalker * gem5::MMU::getTableWalker ( BaseMMU::Mode mode, bool stage2 ) const

protected

Definition at line 166 of file mmu.cc.

References dtbStage2Walker, dtbWalker, gem5::BaseMMU::Execute, itbStage2Walker, itbWalker, and gem5::ArmISA::mode.

Referenced by getTE().

getTE() [1/2]

Fault gem5::MMU::getTE	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		SecurityState	ss,
		PASpace	ipaspace,
		ArmTranslationType	tran_type,
		bool	stage2 )

Definition at line 1613 of file mmu.cc.

References getTE(), gem5::ArmISA::mode, s1State, s2State, gem5::ArmISA::ss, and gem5::ArmISA::te.

Referenced by getResultTe(), and getTE().

getTE() [2/2]

Fault gem5::MMU::getTE	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		SecurityState	ss,
		PASpace	ipaspace,
		ArmTranslationType	tran_type,
		CachedState &	state )

Definition at line 1644 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::aarch64, gem5::ArmISA::MMU::CachedState::asid, gem5::ArmISA::MMU::CachedState::currRegime, DPRINTF, gem5::ArmISA::MMU::CachedState::exceptionLevel, gem5::BaseMMU::Execute, getTableWalker(), isCompleteTranslation(), gem5::ArmISA::MMU::CachedState::isStage2, lookup(), MMU(), gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::ArmFault::PrefetchTLBMiss, purifyTaggedAddr(), gem5::ArmISA::ss, gem5::ArmISA::MMU::CachedState::stage2DescReq, stats, gem5::ArmISA::te, gem5::ArmISA::MMU::CachedState::ttbcr, updateMiscReg(), gem5::MipsISA::vaddr, gem5::ArmISA::MMU::CachedState::vmid, and gem5::ArmISA::TableWalker::walk().

getTlb()

TLB * gem5::MMU::getTlb ( BaseMMU::Mode mode, bool stage2 ) const

protected

Definition at line 150 of file mmu.cc.

References dtbStage2, gem5::BaseMMU::Execute, getDTBPtr(), getITBPtr(), itbStage2, and gem5::ArmISA::mode.

Referenced by lookup(), and translateFunctional().

getValidAddr()

Addr gem5::MMU::getValidAddr ( Addr vaddr, ThreadContext * tc, Mode mode )

overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 377 of file mmu.cc.

References gem5::BaseMMU::Execute, gem5::ArmISA::mode, NormalTran, purifyTaggedAddr(), updateMiscReg(), and gem5::MipsISA::vaddr.

hasUnprivRegime()

bool gem5::MMU::hasUnprivRegime ( TranslationRegime regime )

static

Definition at line 989 of file mmu.cc.

References gem5::ArmISA::EL10, and gem5::ArmISA::EL20.

Referenced by gem5::ArmISA::TableWalker::LongDescriptor::global(), s1DirectPermBits64(), s1IndirectPermBits64(), gem5::TlbiOp64::tlbiRva(), and gem5::TlbiOp64::tlbiVa().

hasWalkCache()

bool gem5::ArmISA::MMU::hasWalkCache ( ) const

inline

Definition at line 329 of file mmu.hh.

References _hasWalkCache.

iflush()

void gem5::MMU::iflush

(

const TLBIOp &

tlbi_op

)

Definition at line 249 of file mmu.cc.

References flush(), gem5::BaseMMU::instruction, gem5::ArmISA::tlb, and gem5::BaseMMU::unified.

Referenced by gem5::ArmISA::ITLBIALL::operator()(), gem5::ArmISA::ITLBIASID::operator()(), and gem5::ArmISA::ITLBIMVA::operator()().

init()

void gem5::MMU::init ( )

overridevirtual

Called at init time, this method is traversing the TLB hierarchy and pupulating the instruction/data/unified containers accordingly.

Reimplemented from gem5::BaseMMU.

Definition at line 93 of file mmu.cc.

References _hasWalkCache, checkWalkCache(), dtbStage2, dtbStage2Walker, dtbWalker, getDTBPtr(), getITBPtr(), gem5::BaseMMU::init(), itbStage2, itbStage2Walker, itbWalker, and gem5::ArmISA::TLB::setTableWalker().

invalidateMiscReg()

void gem5::MMU::invalidateMiscReg

(

)

Definition at line 208 of file mmu.cc.

References s1State, and s2State.

Referenced by gem5::ArmISA::ISA::clear(), gem5::ArmISA::ISA::copyRegsFrom(), and gem5::ArmISA::ISA::setMiscReg().

isCompleteTranslation()

bool gem5::MMU::isCompleteTranslation ( TlbEntry * te ) const

protected

Definition at line 1783 of file mmu.cc.

References gem5::ArmISA::TlbEntry::partial.

Referenced by getResultTe(), getTE(), and translateMmuOn().

lookup()

TlbEntry * gem5::MMU::lookup	(	Addr	vpn,
		uint16_t	asn,
		vmid_t	vmid,
		SecurityState	ss,
		bool	functional,
		bool	ignore_asn,
		TranslationRegime	target_regime,
		bool	stage2,
		BaseMMU::Mode	mode )

Lookup an entry in the TLB.

Parameters

vpn	virtual address
asn	context id/address space id to use
vmid	The virtual machine ID used for stage 2 translation
ss	security state of the PE
functional	if the lookup should modify state
ignore_asn	if on lookup asn should be ignored
target_regime	selecting the translation regime
mode	to differentiate between read/writes/fetches.

Returns

pointer to TLB entry if it exists

Definition at line 1623 of file mmu.cc.

References gem5::ArmISA::asid, gem5::ArmISA::TLBTypes::KeyType::asn, gem5::ArmISA::TLBTypes::KeyType::functional, getTlb(), gem5::ArmISA::TLBTypes::KeyType::ignoreAsn, gem5::ArmISA::mode, gem5::ArmISA::TLBTypes::KeyType::mode, gem5::ArmISA::ss, gem5::ArmISA::TLBTypes::KeyType::ss, gem5::ArmISA::TLBTypes::KeyType::targetRegime, gem5::ArmISA::tlb, gem5::ArmISA::TLBTypes::KeyType::va, gem5::ArmISA::va, and gem5::ArmISA::TLBTypes::KeyType::vmid.

Referenced by getTE().

purifyTaggedAddr()

Addr gem5::MMU::purifyTaggedAddr ( Addr vaddr_tainted, ThreadContext * tc, ExceptionLevel el, TCR tcr, bool is_inst, CachedState & state )

protected

Definition at line 1001 of file mmu.cc.

References gem5::bits(), gem5::ArmISA::MMU::CachedState::computeAddrTop, gem5::ArmISA::el, and gem5::ArmISA::maskTaggedAddr().

Referenced by getTE(), getValidAddr(), translateFs(), and translateSe().

release()

const ArmRelease * gem5::ArmISA::MMU::release ( ) const

inline

Definition at line 327 of file mmu.hh.

References _release.

s1DirectPermBits64()

std::tuple< bool, bool, bool > gem5::MMU::s1DirectPermBits64 ( TlbEntry * te, const RequestPtr & req, Mode mode, ThreadContext * tc, CachedState & state, bool r, bool w, bool x )

protected

Definition at line 873 of file mmu.cc.

References _release, gem5::bits(), gem5::Request::CACHE_BLOCK_ZERO, gem5::ArmISA::MMU::CachedState::cpsr, gem5::ArmISA::MMU::CachedState::currRegime, DPRINTF, gem5::ArmISA::EL10, gem5::ArmISA::EL3, hasUnprivRegime(), gem5::ArmSystem::haveEL(), gem5::ArmISA::MMU::CachedState::isPriv, MMU(), gem5::ArmISA::mode, gem5::ArmISA::pan, gem5::PowerISA::pr, gem5::MipsISA::px, gem5::MipsISA::r, gem5::ArmISA::MMU::CachedState::scr, gem5::ArmISA::MMU::CachedState::sctlr, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, gem5::ArmISA::te, UserMode, gem5::ArmISA::uw, gem5::MipsISA::ux, gem5::MipsISA::w, gem5::ArmISA::wxn, and gem5::RiscvISA::x.

Referenced by s1PermBits64().

s1IndirectPermBits64()

std::tuple< bool, bool, bool > gem5::MMU::s1IndirectPermBits64 ( TlbEntry * te, const RequestPtr & req, Mode mode, ThreadContext * tc, CachedState & state, bool r, bool w, bool x )

protected

Definition at line 732 of file mmu.cc.

References _release, gem5::bits(), gem5::Request::CACHE_BLOCK_ZERO, gem5::ArmISA::MMU::CachedState::cpsr, gem5::ArmISA::MMU::CachedState::currRegime, DPRINTF, gem5::ArmISA::EL10, gem5::ArmISA::EL3, hasUnprivRegime(), gem5::ArmSystem::haveEL(), gem5::ArmISA::MMU::CachedState::isPriv, MMU(), gem5::ArmISA::mode, gem5::ArmISA::MMU::CachedState::pir, gem5::ArmISA::MMU::CachedState::pire0, gem5::PowerISA::pr, gem5::MipsISA::px, gem5::MipsISA::r, gem5::ArmISA::MMU::CachedState::scr, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, gem5::ArmISA::te, UserMode, gem5::ArmISA::uw, gem5::MipsISA::ux, gem5::MipsISA::w, gem5::ArmISA::wxn, and gem5::RiscvISA::x.

Referenced by s1PermBits64().

s1PermBits64()

std::pair< bool, bool > gem5::MMU::s1PermBits64 ( TlbEntry * te, const RequestPtr & req, Mode mode, ThreadContext * tc, CachedState & state, bool r, bool w, bool x )

protected

Definition at line 959 of file mmu.cc.

References gem5::ArmISA::mode, gem5::ArmISA::MMU::CachedState::pie, gem5::MipsISA::r, s1DirectPermBits64(), s1IndirectPermBits64(), gem5::ArmISA::te, gem5::MipsISA::w, and gem5::RiscvISA::x.

Referenced by checkPermissions64().

s2PermBits64()

std::pair< bool, bool > gem5::MMU::s2PermBits64 ( TlbEntry * te, const RequestPtr & req, Mode mode, ThreadContext * tc, CachedState & state, bool r, bool w, bool x )

protected

Definition at line 691 of file mmu.cc.

References DPRINTF, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::MMU::CachedState::exceptionLevel, gem5::ArmSystem::haveEL(), MMU(), gem5::ArmISA::mode, panic, gem5::MipsISA::r, gem5::ArmISA::MMU::CachedState::scr, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, gem5::ArmISA::te, gem5::MipsISA::w, and gem5::RiscvISA::x.

Referenced by checkPermissions64().

setAttr()

void gem5::ArmISA::MMU::setAttr ( uint64_t attr )

inline

Accessor functions for memory attributes for last accessed TLB entry.

Definition at line 322 of file mmu.hh.

References _attr, and gem5::ArmISA::attr.

Referenced by translateMmuOff(), and translateMmuOn().

setTestInterface()

void gem5::MMU::setTestInterface

(

SimObject *

ti

)

Definition at line 1803 of file mmu.cc.

References dtbStage2Walker, dtbWalker, fatal_if, itbStage2Walker, itbWalker, gem5::Named::name(), gem5::SimObject::SimObject(), test, and gem5::MipsISA::ti.

takeOverFrom()

void gem5::MMU::takeOverFrom ( BaseMMU * old_mmu )

overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 1789 of file mmu.cc.

References _attr, gem5::BaseMMU::BaseMMU(), MMU(), s1State, s2State, and gem5::BaseMMU::takeOverFrom().

testAndFinalize()

Fault gem5::MMU::testAndFinalize ( const RequestPtr & req, ThreadContext * tc, Mode mode, TlbEntry * te, CachedState & state ) const

protected

Definition at line 280 of file mmu.cc.

References gem5::ArmISA::domain, gem5::BaseMMU::Execute, finalizePhysical(), gem5::ArmISA::mode, gem5::ArmISA::NoAccess, gem5::NoFault, gem5::ArmISA::mpam::tagRequest(), gem5::ArmISA::te, and testTranslation().

Referenced by translateMmuOff(), and translateMmuOn().

testTranslation()

Fault gem5::MMU::testTranslation	(	const RequestPtr &	req,
		Mode	mode,
		DomainType	domain,
		CachedState &	state ) const

Definition at line 1819 of file mmu.cc.

References gem5::ArmISA::domain, gem5::ArmISA::MMU::CachedState::isPriv, gem5::ArmISA::mode, gem5::NoFault, and test.

Referenced by testAndFinalize().

translateAtomic() [1/3]

Fault gem5::MMU::translateAtomic	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		ArmTranslationType	tran_type,
		bool	stage2 )

Definition at line 1250 of file mmu.cc.

References gem5::FullSystem, gem5::ArmISA::mode, translateFs(), translateSe(), and updateMiscReg().

translateAtomic() [2/3]

Fault gem5::ArmISA::MMU::translateAtomic ( const RequestPtr & req, ThreadContext * tc, Mode mode )

inlineoverridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 248 of file mmu.hh.

References gem5::ArmISA::mode, NormalTran, and translateAtomic().

Referenced by translateAtomic(), and translateAtomic().

translateAtomic() [3/3]

Fault gem5::MMU::translateAtomic	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		ArmTranslationType	tran_type )

Definition at line 1243 of file mmu.cc.

References gem5::ArmISA::mode, and translateAtomic().

translateComplete() [1/2]

Fault gem5::MMU::translateComplete	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		ArmTranslationType	tran_type,
		bool	call_from_s2 )

Definition at line 1310 of file mmu.cc.

References gem5::ArmISA::mode, s1State, and translateComplete().

Referenced by translateComplete(), and translateTiming().

translateComplete() [2/2]

Fault gem5::MMU::translateComplete	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		ArmTranslationType	tran_type,
		bool	call_from_s2,
		CachedState &	state )

Definition at line 1319 of file mmu.cc.

References DPRINTF, gem5::BaseMMU::Translation::finish(), gem5::FullSystem, gem5::BaseMMU::Translation::markDelayed(), MMU(), gem5::ArmISA::mode, gem5::NoFault, gem5::ArmISA::MMU::CachedState::stage2Req, translateFs(), and translateSe().

translateFs()

Fault gem5::MMU::translateFs	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing,
		ArmTranslationType	tran_type,
		bool	functional,
		CachedState &	state )

Definition at line 1156 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::aarch64, gem5::ArmISA::ArmFault::AlignmentFault, AlignmentMask, AllowUnaligned, gem5::ArmISA::MMU::CachedState::asid, DPRINTF, gem5::ArmISA::MMU::CachedState::exceptionLevel, gem5::BaseMMU::Execute, gem5::ArmISA::ISA::getSelfDebug(), gem5::ArmISA::HaveExt(), gem5::ArmISA::MMU::CachedState::hcr, gem5::ArmISA::MMU::CachedState::isPriv, gem5::ArmISA::MMU::CachedState::isStage2, gem5::ArmISA::longDescFormatInUse(), gem5::ArmISA::LpaeTran, gem5::ArmISA::mask, MMU(), gem5::ArmISA::mode, gem5::ArmISA::NoAccess, gem5::NoFault, purifyTaggedAddr(), S1S2NsTran, gem5::ArmISA::MMU::CachedState::scr, gem5::ArmISA::MMU::CachedState::sctlr, gem5::ArmISA::sd, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, stats, gem5::Request::STRICT_ORDER, translateMmuOff(), translateMmuOn(), gem5::ArmISA::MMU::CachedState::ttbcr, gem5::Request::UNCACHEABLE, UserMode, gem5::MipsISA::vaddr, gem5::ArmISA::vm, gem5::ArmISA::VmsaTran, and gem5::BaseMMU::Write.

Referenced by translateAtomic(), translateComplete(), and translateFunctional().

translateFunctional() [1/5]

TranslationGenPtr gem5::ArmISA::MMU::translateFunctional ( Addr start, Addr size, ThreadContext * tc, Mode mode, Request::Flags flags )

inlineoverridevirtual

Returns a translation generator for a region of virtual addresses, instead of directly translating a specific address.

Implements gem5::BaseMMU.

Definition at line 86 of file mmu.hh.

References gem5::ArmISA::mode, and gem5::ArmISA::PageBytes.

Referenced by gem5::ArmISA::ISA::addressTranslation(), gem5::AtOp64::addressTranslation64(), gem5::trace::TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(), translateFunctional(), and translateFunctional().

translateFunctional() [2/5]

Fault gem5::MMU::translateFunctional ( const RequestPtr & req, ThreadContext * tc, BaseMMU::Mode mode )

overridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 1267 of file mmu.cc.

References gem5::ArmISA::mode, NormalTran, and translateFunctional().

translateFunctional() [3/5]

Fault gem5::MMU::translateFunctional	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		ArmTranslationType	tran_type )

Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state.

Definition at line 1273 of file mmu.cc.

References gem5::ArmISA::mode, and translateFunctional().

translateFunctional() [4/5]

Fault gem5::MMU::translateFunctional	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Mode	mode,
		ArmTranslationType	tran_type,
		bool	stage2 )

Definition at line 1280 of file mmu.cc.

References gem5::FullSystem, gem5::ArmISA::mode, translateFs(), translateSe(), and updateMiscReg().

translateFunctional() [5/5]

bool gem5::MMU::translateFunctional	(	ThreadContext *	tc,
		Addr	vaddr,
		Addr &	paddr )

Do a functional lookup on the TLB (for debugging) and don't modify any internal state.

Parameters

tc	thread context to get the context id from
vaddr	virtual address to translate
pa	returned physical address

Returns

if the translation was successful

Definition at line 182 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::asid, gem5::ArmISA::TLBTypes::KeyType::asn, gem5::ArmISA::MMU::CachedState::currRegime, gem5::ArmISA::MMU::CachedState::directToStage2, gem5::ArmISA::e, gem5::ArmISA::TLBTypes::KeyType::functional, getTlb(), gem5::ArmISA::TLBTypes::KeyType::ignoreAsn, gem5::ArmISA::TLBTypes::KeyType::mode, NormalTran, gem5::ArmISA::pa, gem5::BaseMMU::Read, gem5::ArmISA::MMU::CachedState::securityState, gem5::ArmISA::TLBTypes::KeyType::ss, gem5::ArmISA::TLBTypes::KeyType::targetRegime, gem5::ArmISA::tlb, updateMiscReg(), gem5::ArmISA::TLBTypes::KeyType::va, gem5::ArmISA::va, gem5::ArmISA::MMU::CachedState::vmid, and gem5::ArmISA::TLBTypes::KeyType::vmid.

translateMmuOff()

Fault gem5::MMU::translateMmuOff	(	ThreadContext *	tc,
		const RequestPtr &	req,
		Mode	mode,
		ArmTranslationType	tran_type,
		Addr	vaddr,
		bool	long_desc_format,
		CachedState &	state )

Definition at line 1014 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::aarch64, gem5::ArmISA::ArmFault::AddressSizeLL, gem5::ArmISA::TlbEntry::attributes, gem5::bits(), gem5::ArmISA::computeAddrTop(), gem5::ArmISA::currEL(), gem5::ArmISA::dc, DPRINTF, gem5::ArmISA::EL2, gem5::ArmISA::MMU::CachedState::exceptionLevel, gem5::BaseMMU::Execute, gem5::ArmISA::f, gem5::ArmISA::HaveExt(), gem5::ArmISA::MMU::CachedState::hcr, gem5::ArmISA::TlbEntry::innerAttrs, gem5::ArmISA::MMU::CachedState::isStage2, gem5::ArmISA::LpaeTran, gem5::ArmISA::MISCREG_TCR_EL1, MMU(), gem5::ArmISA::mode, gem5::ArmISA::TlbEntry::mtype, gem5::ArmISA::MMU::CachedState::nmrr, gem5::ArmISA::NoAccess, gem5::ArmISA::TlbEntry::Normal, gem5::ArmISA::TlbEntry::ns, gem5::ArmISA::TlbEntry::outerAttrs, gem5::ArmISA::TlbEntry::outerShareable, physAddrRange, gem5::ArmISA::MMU::CachedState::prrr, gem5::ThreadContext::readMiscReg(), gem5::ArmISA::MMU::CachedState::sctlr, gem5::Request::SECURE, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, setAttr(), gem5::ArmISA::TlbEntry::setAttributes(), gem5::ArmISA::TlbEntry::shareable, gem5::Request::STRICT_ORDER, gem5::ArmISA::TlbEntry::StronglyOrdered, testAndFinalize(), gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, and gem5::BaseMMU::Write.

Referenced by translateFs().

translateMmuOn()

Fault gem5::MMU::translateMmuOn	(	ThreadContext *	tc,
		const RequestPtr &	req,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing,
		bool	functional,
		Addr	vaddr,
		TranMethod	tran_method,
		CachedState &	state )

Definition at line 1089 of file mmu.cc.

References gem5::ArmISA::ArmFault::AlignmentFault, AlignmentMask, DPRINTF, gem5::BaseMMU::Execute, getResultTe(), isCompleteTranslation(), gem5::ArmISA::MMU::CachedState::isStage2, gem5::ArmISA::mask, MMU(), gem5::ArmISA::mode, gem5::ArmISA::NoAccess, gem5::NoFault, gem5::ArmISA::TlbEntry::Normal, gem5::ArmISA::pa, gem5::Request::SECURE, gem5::ArmISA::Secure, gem5::ArmISA::MMU::CachedState::securityState, setAttr(), stats, gem5::Request::STRICT_ORDER, gem5::ArmISA::te, testAndFinalize(), gem5::Request::UNCACHEABLE, gem5::MipsISA::vaddr, and gem5::BaseMMU::Write.

Referenced by translateFs().

translateSe()

Fault gem5::MMU::translateSe	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing,
		CachedState &	state )

Definition at line 332 of file mmu.cc.

References gem5::ArmISA::MMU::CachedState::aarch64, gem5::ArmISA::ArmFault::AlignmentFault, AlignmentMask, AllowUnaligned, gem5::ArmISA::MMU::CachedState::exceptionLevel, gem5::BaseMMU::Execute, finalizePhysical(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::MMU::CachedState::isStage2, gem5::ArmISA::mask, gem5::ArmISA::mode, gem5::ArmISA::NoAccess, NormalTran, gem5::MipsISA::p, purifyTaggedAddr(), gem5::ArmISA::MMU::CachedState::sctlr, gem5::ArmISA::MMU::CachedState::ttbcr, gem5::Request::UNCACHEABLE, gem5::EmulationPageTable::Uncacheable, updateMiscReg(), gem5::MipsISA::vaddr, gem5::ArmISA::VmsaTran, and gem5::BaseMMU::Write.

Referenced by translateAtomic(), translateComplete(), and translateFunctional().

translateTiming() [1/3]

void gem5::ArmISA::MMU::translateTiming	(	const RequestPtr &	req,
		ThreadContext *	tc,
		BaseMMU::Translation *	translation,
		BaseMMU::Mode	mode,
		bool	stage2 )

References gem5::BaseMMU::BaseMMU(), gem5::ArmISA::mode, and gem5::MipsISA::vaddr.

translateTiming() [2/3]

void gem5::ArmISA::MMU::translateTiming ( const RequestPtr & req, ThreadContext * tc, Translation * translation, Mode mode )

inlineoverridevirtual

Reimplemented from gem5::BaseMMU.

Definition at line 259 of file mmu.hh.

References gem5::ArmISA::mode, NormalTran, and translateTiming().

Referenced by translateTiming().

translateTiming() [3/3]

void gem5::MMU::translateTiming	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		ArmTranslationType	tran_type,
		bool	stage2 )

Definition at line 1297 of file mmu.cc.

References gem5::ArmISA::mode, translateComplete(), and updateMiscReg().

tranTypeEL()

ExceptionLevel gem5::MMU::tranTypeEL ( CPSR cpsr, SCR scr, ArmTranslationType type )

static

Determine the EL to use for the purpose of a translation given a specific translation type.

If the translation type doesn't specify an EL, we use the current EL.

Definition at line 1581 of file mmu.cc.

References gem5::ArmISA::currEL(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, HypMode, NormalTran, panic, S12E0Tran, S12E1Tran, S1CTran, S1E0Tran, S1E1Tran, S1E2Tran, S1E3Tran, and S1S2NsTran.

Referenced by gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

updateMiscReg()

MMU::CachedState & gem5::MMU::updateMiscReg ( ThreadContext * tc, ArmTranslationType tran_type, bool stage2 )

protected

Definition at line 1380 of file mmu.cc.

References gem5::ThreadContext::contextId(), gem5::BaseMMU::data, DPRINTF, dtbStage2, gem5::BaseMMU::instruction, itbStage2, miscRegContext, MMU(), s1State, s2State, gem5::ArmISA::tlb, and gem5::BaseMMU::unified.

Referenced by checkPermissions64(), getTE(), getValidAddr(), translateAtomic(), translateFunctional(), translateFunctional(), translateSe(), and translateTiming().

Member Data Documentation

_attr

uint64_t gem5::ArmISA::MMU::_attr

protected

Definition at line 433 of file mmu.hh.

Referenced by getAttr(), MMU(), setAttr(), and takeOverFrom().

_hasWalkCache

bool gem5::ArmISA::MMU::_hasWalkCache

protected

Definition at line 442 of file mmu.hh.

Referenced by hasWalkCache(), init(), and MMU().

_release

const ArmRelease* gem5::ArmISA::MMU::_release

protected

Definition at line 436 of file mmu.hh.

Referenced by MMU(), release(), s1DirectPermBits64(), and s1IndirectPermBits64().

dtbStage2

TLB* gem5::ArmISA::MMU::dtbStage2

protected

Definition at line 77 of file mmu.hh.

Referenced by flushAll(), flushStage2(), getTlb(), init(), MMU(), and updateMiscReg().

dtbStage2Walker

TableWalker* gem5::ArmISA::MMU::dtbStage2Walker

protected

Definition at line 82 of file mmu.hh.

Referenced by getTableWalker(), init(), MMU(), and setTestInterface().

dtbWalker

TableWalker* gem5::ArmISA::MMU::dtbWalker

protected

Definition at line 80 of file mmu.hh.

Referenced by getTableWalker(), init(), MMU(), and setTestInterface().

haveLargeAsid64

bool gem5::ArmISA::MMU::haveLargeAsid64

protected

Definition at line 437 of file mmu.hh.

Referenced by MMU().

itbStage2

TLB* gem5::ArmISA::MMU::itbStage2

protected

Definition at line 76 of file mmu.hh.

Referenced by flushAll(), flushStage2(), getTlb(), init(), MMU(), and updateMiscReg().

itbStage2Walker

TableWalker* gem5::ArmISA::MMU::itbStage2Walker

protected

Definition at line 81 of file mmu.hh.

Referenced by getTableWalker(), init(), MMU(), and setTestInterface().

itbWalker

TableWalker* gem5::ArmISA::MMU::itbWalker

protected

Definition at line 79 of file mmu.hh.

Referenced by getTableWalker(), init(), MMU(), and setTestInterface().

m5opRange

AddrRange gem5::ArmISA::MMU::m5opRange

protected

Definition at line 440 of file mmu.hh.

Referenced by finalizePhysical(), and MMU().

miscRegContext

ContextID gem5::ArmISA::MMU::miscRegContext

protected

Definition at line 427 of file mmu.hh.

Referenced by MMU(), and updateMiscReg().

physAddrRange

uint8_t gem5::ArmISA::MMU::physAddrRange

protected

Definition at line 438 of file mmu.hh.

Referenced by MMU(), and translateMmuOff().

s1State

CachedState gem5::ArmISA::MMU::s1State

Definition at line 430 of file mmu.hh.

Referenced by checkPermissions(), checkPermissions64(), drainResume(), getTE(), invalidateMiscReg(), MMU(), takeOverFrom(), translateComplete(), and updateMiscReg().

s2State

CachedState gem5::ArmISA::MMU::s2State

Definition at line 430 of file mmu.hh.

Referenced by checkPermissions(), checkPermissions64(), drainResume(), getTE(), invalidateMiscReg(), MMU(), takeOverFrom(), and updateMiscReg().

stats

gem5::ArmISA::MMU::Stats gem5::ArmISA::MMU::stats

protected

Referenced by checkPermissions(), checkPermissions64(), getTE(), MMU(), translateFs(), and translateMmuOn().

test

TlbTestInterface* gem5::ArmISA::MMU::test

Definition at line 406 of file mmu.hh.

Referenced by MMU(), setTestInterface(), and testTranslation().

---

The documentation for this class was generated from the following files:

• arch/arm/mmu.hh
• arch/arm/mmu.cc