pmu.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2011-2014, 2017-2018, 2022-2023, 2025 Arm Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ARCH_ARM_PMU_HH__
#define __ARCH_ARM_PMU_HH__
 
#include <map>
#include <memory>
#include <vector>
 
#include "arch/arm/isa_device.hh"
#include "arch/arm/system.hh"
#include "base/cprintf.hh"
#include "cpu/base.hh"
#include "debug/PMUVerbose.hh"
#include "enums/EventTypeId.hh"
#include "mem/cache/cache_probe_arg.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
struct ArmPMUParams;
class Platform;
class ThreadContext;
class ArmInterruptPin;
 
namespace ArmISA {
 

class PMU : public SimObject, public ArmISA::BaseISADevice
{
  public:
    using EventTypeId = std::underlying_type_t<enums::EventTypeId>;
    PMU(const ArmPMUParams &p);
    ~PMU();
 
    void addEventProbe(EventTypeId id, SimObject *obj, const char *name);
    void addSoftwareIncrementEvent(EventTypeId id);
 
    void registerEvent(EventTypeId id);
 
  public: // SimObject and related interfaces
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
    void drainResume() override;
 
    void regProbeListeners() override;
 
  public: // ISA Device interface
    void setThreadContext(ThreadContext *tc) override;

    void setMiscReg(int misc_reg, RegVal val) override;
    RegVal readMiscReg(int misc_reg) override;
 
  protected: // PMU register types and constants
    BitUnion32(PMCR_t)
        // PMU Enable
        Bitfield<0> e;
        // Event counter reset
        Bitfield<1> p;
        // Cycle counter reset
        Bitfield<2> c;
        // Cycle counter divider enable
        Bitfield<3> d;
        // Export enable
        Bitfield<4> x;
        // Disable PMCCNTR when event counting is prohibited
        Bitfield<5> dp;
        // Long Cycle counter enable
        Bitfield<6> lc;
        // Number of event counters implemented
        Bitfield<15, 11> n;
        // Implementation ID
        Bitfield<23, 16> idcode;
        // Implementer code
        Bitfield<31, 24> imp;
    EndBitUnion(PMCR_t)
 
    BitUnion32(PMSELR_t)
        // Performance counter selector
        Bitfield<4, 0> sel;
    EndBitUnion(PMSELR_t)
 
    BitUnion32(PMEVTYPER_t)
        Bitfield<15, 0> evtCount;
 
        // Secure EL3 filtering
        Bitfield<26> m;
        // Non-secure EL2 mode filtering
        Bitfield<27> nsh;
        // Non-secure EL0 mode filtering
        Bitfield<28> nsu;
        // Non-secure EL1 mode filtering
        Bitfield<29> nsk;
        // EL0 filtering
        Bitfield<30> u;
        // EL1 filtering
        Bitfield<31> p;
    EndBitUnion(PMEVTYPER_t)

    typedef unsigned int CounterId;

    static const CounterId PMCCNTR = 31;
 
  protected: /* High-level register and interrupt handling */
    RegVal readMiscRegInt(int misc_reg);

    void setControlReg(PMCR_t val);

    void resetEventCounts();

    void raiseInterrupt();

    void clearInterrupt();

    uint64_t getCounterValue(CounterId id) const {
        return isValidCounter(id) ? getCounter(id).getValue() : 0;
    }

    void setCounterValue(CounterId id, uint64_t val);

    PMEVTYPER_t getCounterTypeRegister(CounterId id) const;

    void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);

    void setOverflowStatus(RegVal new_val);
 
  protected: /* Probe handling and counter state */
    struct CounterState;
    struct Stats;

    struct PMUEvent
    {
        PMUEvent(EventTypeId _id, Stats *pmu_stats)
          : id(_id), pmuStats(pmu_stats)
        {}
 
        virtual ~PMUEvent()
        {}

        void attachEvent(PMU::CounterState *user);

        void detachEvent(PMU::CounterState *user);

        virtual void increment(const uint64_t val);

        virtual void enable() = 0;

        virtual void disable() = 0;

        virtual void updateAttachedCounters() {}
 
      protected:
        const EventTypeId id;

        Stats * const pmuStats;

        std::set<PMU::CounterState*> userCounters;
    };
 
    struct RegularEvent : public PMUEvent
    {
        typedef std::pair<SimObject*, std::string> EventTypeEntry;
 
        void addMicroarchitectureProbe(SimObject* object,
            std::string name) {
 
            panic_if(!object,"malformed probe-point"
                " definition with name %s\n", name);
 
            microArchitectureEventSet.emplace(object, name);
        }
 
      protected:
        struct RegularProbe : public ProbeListenerArgBase<uint64_t>
        {
            RegularProbe(RegularEvent *parent, std::string name)
                : ProbeListenerArgBase(std::move(name)), parentEvent(parent)
            {}
 
            RegularProbe() = delete;
 
            void notify(const uint64_t &val) override;
 
          protected:
            RegularEvent *parentEvent;
        };
 
        struct CacheProbe : public ProbeListenerArgBase<CacheAccessProbeArg>
        {
            CacheProbe(RegularEvent *parent, std::string name)
                : ProbeListenerArgBase(std::move(name)), parentEvent(parent)
            {}
 
            CacheProbe() = delete;
 
            void notify(const CacheAccessProbeArg &val) override
            {
                parentEvent->increment(1);
            };
 
          protected:
            RegularEvent *parentEvent;
        };

        std::set<EventTypeEntry> microArchitectureEventSet;

        std::vector<ProbeListenerPtr<>> attachedProbePointList;
 
        using PMUEvent::PMUEvent;
 
        void enable() override;
 
        void disable() override;
    };
 
    class SWIncrementEvent : public PMUEvent
    {
        void enable() override {}
        void disable() override {}
 
      public:
        using PMUEvent::PMUEvent;

        void write(uint64_t val);
    };

    std::shared_ptr<PMUEvent> getEvent(EventTypeId eventId);

    struct CounterState : public Serializable
    {
        CounterState(PMU &pmuReference, uint64_t counter_id,
                     const bool is_64_bit)
            : eventId(0), filter(0), enabled(false),
              overflow64(is_64_bit), sourceEvent(nullptr),
              counterId(counter_id), value(0), resetValue(false),
              pmu(pmuReference) {}
 
        void serialize(CheckpointOut &cp) const override;
        void unserialize(CheckpointIn &cp)  override;

        uint64_t add(uint64_t delta);
 
        bool isFiltered() const;

        void detach();

        void attach(const std::shared_ptr<PMUEvent> &event);

        uint64_t getCounterId() const{
            return counterId;
        }

        uint64_t getValue() const;

        void setValue(uint64_t val);
 
      public: /* Serializable state */
        EventTypeId eventId;

        PMEVTYPER_t filter;

        bool enabled;

        bool overflow64;
 
      protected: /* Configuration */
        std::shared_ptr<PMUEvent> sourceEvent;

        uint64_t counterId;

        uint64_t value;

        bool resetValue;
 
        PMU &pmu;
 
        template <typename ...Args>
        void debugCounter(const char* mainString, Args &...args) const {
 
            std::string userString = csprintf(mainString, args...);
 
            warn("[counterId = %d, eventId = %d, sourceEvent = 0x%x] %s",
                counterId, eventId, sourceEvent, userString.c_str());
 
        }
    };

    bool isValidCounter(CounterId id) const {
        return id < counters.size() || id == PMCCNTR;
    }

    CounterState &getCounter(CounterId id) {
        assert(isValidCounter(id));
        return id == PMCCNTR ? cycleCounter : counters[id];
    }

    const CounterState &getCounter(CounterId id) const {
        assert(isValidCounter(id));
        return id == PMCCNTR ? cycleCounter : counters[id];
    }

    void updateCounter(CounterState &ctr);

    bool isFiltered(const CounterState &ctr) const;

    void updateAllCounters();
 
  protected: /* State that needs to be serialized */
    bool use64bitCounters;

    std::set<EventTypeId> statCounters;

    RegVal reg_pmcnten;

    PMCR_t reg_pmcr;

    PMSELR_t reg_pmselr;

    RegVal reg_pminten;

    RegVal reg_pmovsr;

    uint64_t reg_pmceid0;
    uint64_t reg_pmceid1;

    unsigned clock_remainder;

    uint64_t maximumCounterCount;

    std::vector<CounterState> counters;

    CounterState cycleCounter;

    const EventTypeId cycleCounterEventId;

    std::shared_ptr<SWIncrementEvent> swIncrementEvent;
 
  protected: /* Configuration and constants */
    PMCR_t reg_pmcr_conf;

    static const RegVal reg_pmcr_wr_mask;

    ArmInterruptPin *interrupt;

    std::map<EventTypeId, std::shared_ptr<PMUEvent>> eventMap;

    const bool exitOnPMUControl;

    bool exitOnPMUInterrupt;
 
    struct Stats : public statistics::Group
    {
      public:
        Stats(PMU *parent);

        void add(EventTypeId id, uint64_t value);
 
      private:
        void registerEvent(EventTypeId id, const char *stat_name);
 
      private:
        PMU *pmu;
        std::unordered_map<EventTypeId, statistics::Scalar> map;
    } stats;
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif