gem5 v25.0.0.1
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misc.hh
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1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * Copyright (c) 2019 Yifei Liu
5 * Copyright (c) 2020 Barkhausen Institut
6 * Copyright (c) 2021 StreamComputing Corp
7 * Copyright (c) 2025 University of Athens
8 * All rights reserved
9 *
10 * The license below extends only to copyright in the software and shall
11 * not be construed as granting a license to any other intellectual
12 * property including but not limited to intellectual property relating
13 * to a hardware implementation of the functionality of the software
14 * licensed hereunder. You may use the software subject to the license
15 * terms below provided that you ensure that this notice is replicated
16 * unmodified and in its entirety in all distributions of the software,
17 * modified or unmodified, in source code or in binary form.
18 *
19 * Copyright (c) 2016 RISC-V Foundation
20 * Copyright (c) 2016 The University of Virginia
21 * Copyright (c) 2024 University of Rostock
22 * All rights reserved.
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions are
26 * met: redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer;
28 * redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in the
30 * documentation and/or other materials provided with the distribution;
31 * neither the name of the copyright holders nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 */
47
48#ifndef __ARCH_RISCV_REGS_MISC_HH__
49#define __ARCH_RISCV_REGS_MISC_HH__
50
51#include <string>
52#include <unordered_map>
53
54#include "arch/generic/vec_pred_reg.hh"
55#include "arch/generic/vec_reg.hh"
56#include "arch/riscv/fault_codes.hh"
57#include "arch/riscv/types.hh"
58#include "base/bitunion.hh"
59#include "base/types.hh"
60#include "cpu/reg_class.hh"
61#include "debug/MiscRegs.hh"
62#include "enums/RiscvType.hh"
63
64namespace gem5
65{
66
67namespace RiscvISA
68{
69
70enum MiscRegIndex
71{
72 MISCREG_PRV = 0,
73 MISCREG_ISA,
74 MISCREG_VENDORID,
75 MISCREG_ARCHID,
76 MISCREG_IMPID,
77 MISCREG_HARTID,
78 MISCREG_STATUS,
79 MISCREG_IP,
80 MISCREG_IE,
81 MISCREG_CYCLE,
82 MISCREG_TIME,
83 MISCREG_INSTRET,
84 MISCREG_HPMCOUNTER03,
85 MISCREG_HPMCOUNTER04,
86 MISCREG_HPMCOUNTER05,
87 MISCREG_HPMCOUNTER06,
88 MISCREG_HPMCOUNTER07,
89 MISCREG_HPMCOUNTER08,
90 MISCREG_HPMCOUNTER09,
91 MISCREG_HPMCOUNTER10,
92 MISCREG_HPMCOUNTER11,
93 MISCREG_HPMCOUNTER12,
94 MISCREG_HPMCOUNTER13,
95 MISCREG_HPMCOUNTER14,
96 MISCREG_HPMCOUNTER15,
97 MISCREG_HPMCOUNTER16,
98 MISCREG_HPMCOUNTER17,
99 MISCREG_HPMCOUNTER18,
100 MISCREG_HPMCOUNTER19,
101 MISCREG_HPMCOUNTER20,
102 MISCREG_HPMCOUNTER21,
103 MISCREG_HPMCOUNTER22,
104 MISCREG_HPMCOUNTER23,
105 MISCREG_HPMCOUNTER24,
106 MISCREG_HPMCOUNTER25,
107 MISCREG_HPMCOUNTER26,
108 MISCREG_HPMCOUNTER27,
109 MISCREG_HPMCOUNTER28,
110 MISCREG_HPMCOUNTER29,
111 MISCREG_HPMCOUNTER30,
112 MISCREG_HPMCOUNTER31,
113 MISCREG_HPMEVENT03,
114 MISCREG_HPMEVENT04,
115 MISCREG_HPMEVENT05,
116 MISCREG_HPMEVENT06,
117 MISCREG_HPMEVENT07,
118 MISCREG_HPMEVENT08,
119 MISCREG_HPMEVENT09,
120 MISCREG_HPMEVENT10,
121 MISCREG_HPMEVENT11,
122 MISCREG_HPMEVENT12,
123 MISCREG_HPMEVENT13,
124 MISCREG_HPMEVENT14,
125 MISCREG_HPMEVENT15,
126 MISCREG_HPMEVENT16,
127 MISCREG_HPMEVENT17,
128 MISCREG_HPMEVENT18,
129 MISCREG_HPMEVENT19,
130 MISCREG_HPMEVENT20,
131 MISCREG_HPMEVENT21,
132 MISCREG_HPMEVENT22,
133 MISCREG_HPMEVENT23,
134 MISCREG_HPMEVENT24,
135 MISCREG_HPMEVENT25,
136 MISCREG_HPMEVENT26,
137 MISCREG_HPMEVENT27,
138 MISCREG_HPMEVENT28,
139 MISCREG_HPMEVENT29,
140 MISCREG_HPMEVENT30,
141 MISCREG_HPMEVENT31,
142 MISCREG_TSELECT,
143 MISCREG_TDATA1,
144 MISCREG_TDATA2,
145 MISCREG_TDATA3,
146 MISCREG_DCSR,
147 MISCREG_DPC,
148 MISCREG_DSCRATCH,
149
150 MISCREG_MEDELEG,
151 MISCREG_MIDELEG,
152 MISCREG_MTVEC,
153 MISCREG_MCOUNTEREN,
154 MISCREG_MSCRATCH,
155 MISCREG_MEPC,
156 MISCREG_MCAUSE,
157 MISCREG_MTVAL,
158 MISCREG_PMPCFG0,
159 MISCREG_PMPCFG1, // pmpcfg1 is rv32 only
160 MISCREG_PMPCFG2,
161 MISCREG_PMPCFG3, // pmpcfg3 is rv32 only
162 MISCREG_PMPADDR00,
163 MISCREG_PMPADDR01,
164 MISCREG_PMPADDR02,
165 MISCREG_PMPADDR03,
166 MISCREG_PMPADDR04,
167 MISCREG_PMPADDR05,
168 MISCREG_PMPADDR06,
169 MISCREG_PMPADDR07,
170 MISCREG_PMPADDR08,
171 MISCREG_PMPADDR09,
172 MISCREG_PMPADDR10,
173 MISCREG_PMPADDR11,
174 MISCREG_PMPADDR12,
175 MISCREG_PMPADDR13,
176 MISCREG_PMPADDR14,
177 MISCREG_PMPADDR15,
178
179 MISCREG_RESERVED01, // MISCREG_SEDELEG,
180 MISCREG_RESERVED02, // MISCREG_SIDELEG,
181 MISCREG_STVEC,
182 MISCREG_SCOUNTEREN,
183 MISCREG_SSCRATCH,
184 MISCREG_SEPC,
185 MISCREG_SCAUSE,
186 MISCREG_STVAL,
187 MISCREG_SATP,
188 MISCREG_SENVCFG,
189
190 MISCREG_RESERVED03, // MISCREG_UTVEC,
191 MISCREG_RESERVED04, // MISCREG_USCRATCH,
192 MISCREG_RESERVED05, // MISCREG_UEPC,
193 MISCREG_RESERVED06, // MISCREG_UCAUSE,
194 MISCREG_RESERVED07, // MISCREG_UTVAL,
195 MISCREG_FFLAGS,
196 MISCREG_FRM,
197
198 MISCREG_VSTART,
199 MISCREG_VXSAT,
200 MISCREG_VXRM,
201 MISCREG_VCSR,
202 MISCREG_VL,
203 MISCREG_VTYPE,
204 MISCREG_VLENB,
205
206 // H-extension registers (RV64)
207
208 MISCREG_HVIP, // vssi bit is alias for mip.vssi
209
210 MISCREG_MTINST,
211 MISCREG_MTVAL2,
212
213 MISCREG_HSTATUS,
214 MISCREG_HEDELEG,
215 MISCREG_HIDELEG,
216 MISCREG_HCOUNTEREN,
217 MISCREG_HGEIE,
218 MISCREG_HTVAL,
219 MISCREG_HTINST,
220 MISCREG_HGEIP,
221
222 MISCREG_HENVCFG,
223 MISCREG_HGATP,
224 MISCREG_HCONTEXT,
225 MISCREG_HTIMEDELTA,
226
227 MISCREG_VSSTATUS,
228 MISCREG_VSTVEC,
229 MISCREG_VSSCRATCH,
230 MISCREG_VSEPC,
231 MISCREG_VSCAUSE,
232 MISCREG_VSTVAL,
233 MISCREG_VSATP,
234
235 // This register stores the V-bit.
236 // It is not mandated by the specification,
237 // however it is useful for the implementation.
238 MISCREG_VIRT,
239
240 // H-extension registers end here
241
242 // These registers are not in the standard, hence does not exist in the
243 // CSRData map. These are mainly used to provide a minimal implementation
244 // for non-maskable-interrupt in our simple cpu.
245 // non-maskable-interrupt-vector-base-address: NMI version of xTVEC
246 MISCREG_NMIVEC,
247 // non-maskable-interrupt-enable: NMI version of xIE
248 MISCREG_NMIE,
249 // non-maskable-interrupt-pending: NMI version of xIP
250 MISCREG_NMIP,
251
252 // Resumable Non-Maskable Interrupts
253 MISCREG_MNSCRATCH,
254 MISCREG_MNEPC,
255 MISCREG_MNCAUSE,
256 MISCREG_MNSTATUS,
257
258 // the following MicsRegIndex are RV32 only
259 MISCREG_MSTATUSH,
260
261 MISCREG_CYCLEH,
262 MISCREG_TIMEH,
263 MISCREG_INSTRETH,
264 MISCREG_HPMCOUNTER03H,
265 MISCREG_HPMCOUNTER04H,
266 MISCREG_HPMCOUNTER05H,
267 MISCREG_HPMCOUNTER06H,
268 MISCREG_HPMCOUNTER07H,
269 MISCREG_HPMCOUNTER08H,
270 MISCREG_HPMCOUNTER09H,
271 MISCREG_HPMCOUNTER10H,
272 MISCREG_HPMCOUNTER11H,
273 MISCREG_HPMCOUNTER12H,
274 MISCREG_HPMCOUNTER13H,
275 MISCREG_HPMCOUNTER14H,
276 MISCREG_HPMCOUNTER15H,
277 MISCREG_HPMCOUNTER16H,
278 MISCREG_HPMCOUNTER17H,
279 MISCREG_HPMCOUNTER18H,
280 MISCREG_HPMCOUNTER19H,
281 MISCREG_HPMCOUNTER20H,
282 MISCREG_HPMCOUNTER21H,
283 MISCREG_HPMCOUNTER22H,
284 MISCREG_HPMCOUNTER23H,
285 MISCREG_HPMCOUNTER24H,
286 MISCREG_HPMCOUNTER25H,
287 MISCREG_HPMCOUNTER26H,
288 MISCREG_HPMCOUNTER27H,
289 MISCREG_HPMCOUNTER28H,
290 MISCREG_HPMCOUNTER29H,
291 MISCREG_HPMCOUNTER30H,
292 MISCREG_HPMCOUNTER31H,
293 MISCREG_JVT,
294
295 NUM_PHYS_MISCREGS,
296 MISCREG_FFLAGS_EXE = NUM_PHYS_MISCREGS,
297
298 NUM_MISCREGS
299};
300
301inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName,
302 NUM_MISCREGS, debug::MiscRegs);
303
304enum CSRIndex
305{
306 CSR_FFLAGS = 0x001,
307 CSR_FRM = 0x002,
308 CSR_FCSR = 0x003,
309 CSR_CYCLE = 0xC00,
310 CSR_TIME = 0xC01,
311 CSR_INSTRET = 0xC02,
312 CSR_HPMCOUNTER03 = 0xC03,
313 CSR_HPMCOUNTER04 = 0xC04,
314 CSR_HPMCOUNTER05 = 0xC05,
315 CSR_HPMCOUNTER06 = 0xC06,
316 CSR_HPMCOUNTER07 = 0xC07,
317 CSR_HPMCOUNTER08 = 0xC08,
318 CSR_HPMCOUNTER09 = 0xC09,
319 CSR_HPMCOUNTER10 = 0xC0A,
320 CSR_HPMCOUNTER11 = 0xC0B,
321 CSR_HPMCOUNTER12 = 0xC0C,
322 CSR_HPMCOUNTER13 = 0xC0D,
323 CSR_HPMCOUNTER14 = 0xC0E,
324 CSR_HPMCOUNTER15 = 0xC0F,
325 CSR_HPMCOUNTER16 = 0xC10,
326 CSR_HPMCOUNTER17 = 0xC11,
327 CSR_HPMCOUNTER18 = 0xC12,
328 CSR_HPMCOUNTER19 = 0xC13,
329 CSR_HPMCOUNTER20 = 0xC14,
330 CSR_HPMCOUNTER21 = 0xC15,
331 CSR_HPMCOUNTER22 = 0xC16,
332 CSR_HPMCOUNTER23 = 0xC17,
333 CSR_HPMCOUNTER24 = 0xC18,
334 CSR_HPMCOUNTER25 = 0xC19,
335 CSR_HPMCOUNTER26 = 0xC1A,
336 CSR_HPMCOUNTER27 = 0xC1B,
337 CSR_HPMCOUNTER28 = 0xC1C,
338 CSR_HPMCOUNTER29 = 0xC1D,
339 CSR_HPMCOUNTER30 = 0xC1E,
340 CSR_HPMCOUNTER31 = 0xC1F,
341
342 // rv32 only csr register begin
343 CSR_CYCLEH = 0xC80,
344 CSR_TIMEH = 0xC81,
345 CSR_INSTRETH = 0xC82,
346 CSR_HPMCOUNTER03H = 0xC83,
347 CSR_HPMCOUNTER04H = 0xC84,
348 CSR_HPMCOUNTER05H = 0xC85,
349 CSR_HPMCOUNTER06H = 0xC86,
350 CSR_HPMCOUNTER07H = 0xC87,
351 CSR_HPMCOUNTER08H = 0xC88,
352 CSR_HPMCOUNTER09H = 0xC89,
353 CSR_HPMCOUNTER10H = 0xC8A,
354 CSR_HPMCOUNTER11H = 0xC8B,
355 CSR_HPMCOUNTER12H = 0xC8C,
356 CSR_HPMCOUNTER13H = 0xC8D,
357 CSR_HPMCOUNTER14H = 0xC8E,
358 CSR_HPMCOUNTER15H = 0xC8F,
359 CSR_HPMCOUNTER16H = 0xC90,
360 CSR_HPMCOUNTER17H = 0xC91,
361 CSR_HPMCOUNTER18H = 0xC92,
362 CSR_HPMCOUNTER19H = 0xC93,
363 CSR_HPMCOUNTER20H = 0xC94,
364 CSR_HPMCOUNTER21H = 0xC95,
365 CSR_HPMCOUNTER22H = 0xC96,
366 CSR_HPMCOUNTER23H = 0xC97,
367 CSR_HPMCOUNTER24H = 0xC98,
368 CSR_HPMCOUNTER25H = 0xC99,
369 CSR_HPMCOUNTER26H = 0xC9A,
370 CSR_HPMCOUNTER27H = 0xC9B,
371 CSR_HPMCOUNTER28H = 0xC9C,
372 CSR_HPMCOUNTER29H = 0xC9D,
373 CSR_HPMCOUNTER30H = 0xC9E,
374 CSR_HPMCOUNTER31H = 0xC9F,
375 // rv32 only csr register end
376
377 CSR_SSTATUS = 0x100,
378 CSR_SIE = 0x104,
379 CSR_STVEC = 0x105,
380 CSR_SCOUNTEREN = 0x106,
381 CSR_SSCRATCH = 0x140,
382 CSR_SEPC = 0x141,
383 CSR_SCAUSE = 0x142,
384 CSR_STVAL = 0x143,
385 CSR_SIP = 0x144,
386 CSR_SATP = 0x180,
387 CSR_SENVCFG = 0x10A, // 20240411 RISCV spec, volume 2
388
389 CSR_MVENDORID = 0xF11,
390 CSR_MARCHID = 0xF12,
391 CSR_MIMPID = 0xF13,
392 CSR_MHARTID = 0xF14,
393 CSR_MSTATUS = 0x300,
394 CSR_MISA = 0x301,
395 CSR_MEDELEG = 0x302,
396 CSR_MIDELEG = 0x303,
397 CSR_MIE = 0x304,
398 CSR_MTVEC = 0x305,
399 CSR_MCOUNTEREN = 0x306,
400 CSR_MSTATUSH = 0x310, // rv32 only
401 CSR_MSCRATCH = 0x340,
402 CSR_MEPC = 0x341,
403 CSR_MCAUSE = 0x342,
404 CSR_MTVAL = 0x343,
405 CSR_MIP = 0x344,
406 CSR_PMPCFG0 = 0x3A0,
407 CSR_PMPCFG1 = 0x3A1, // pmpcfg1 rv32 only
408 CSR_PMPCFG2 = 0x3A2,
409 CSR_PMPCFG3 = 0x3A3,// pmpcfg3 rv32 only
410 CSR_PMPADDR00 = 0x3B0,
411 CSR_PMPADDR01 = 0x3B1,
412 CSR_PMPADDR02 = 0x3B2,
413 CSR_PMPADDR03 = 0x3B3,
414 CSR_PMPADDR04 = 0x3B4,
415 CSR_PMPADDR05 = 0x3B5,
416 CSR_PMPADDR06 = 0x3B6,
417 CSR_PMPADDR07 = 0x3B7,
418 CSR_PMPADDR08 = 0x3B8,
419 CSR_PMPADDR09 = 0x3B9,
420 CSR_PMPADDR10 = 0x3BA,
421 CSR_PMPADDR11 = 0x3BB,
422 CSR_PMPADDR12 = 0x3BC,
423 CSR_PMPADDR13 = 0x3BD,
424 CSR_PMPADDR14 = 0x3BE,
425 CSR_PMPADDR15 = 0x3BF,
426 CSR_MCYCLE = 0xB00,
427 CSR_MINSTRET = 0xB02,
428 CSR_MHPMCOUNTER03 = 0xB03,
429 CSR_MHPMCOUNTER04 = 0xB04,
430 CSR_MHPMCOUNTER05 = 0xB05,
431 CSR_MHPMCOUNTER06 = 0xB06,
432 CSR_MHPMCOUNTER07 = 0xB07,
433 CSR_MHPMCOUNTER08 = 0xB08,
434 CSR_MHPMCOUNTER09 = 0xB09,
435 CSR_MHPMCOUNTER10 = 0xB0A,
436 CSR_MHPMCOUNTER11 = 0xB0B,
437 CSR_MHPMCOUNTER12 = 0xB0C,
438 CSR_MHPMCOUNTER13 = 0xB0D,
439 CSR_MHPMCOUNTER14 = 0xB0E,
440 CSR_MHPMCOUNTER15 = 0xB0F,
441 CSR_MHPMCOUNTER16 = 0xB10,
442 CSR_MHPMCOUNTER17 = 0xB11,
443 CSR_MHPMCOUNTER18 = 0xB12,
444 CSR_MHPMCOUNTER19 = 0xB13,
445 CSR_MHPMCOUNTER20 = 0xB14,
446 CSR_MHPMCOUNTER21 = 0xB15,
447 CSR_MHPMCOUNTER22 = 0xB16,
448 CSR_MHPMCOUNTER23 = 0xB17,
449 CSR_MHPMCOUNTER24 = 0xB18,
450 CSR_MHPMCOUNTER25 = 0xB19,
451 CSR_MHPMCOUNTER26 = 0xB1A,
452 CSR_MHPMCOUNTER27 = 0xB1B,
453 CSR_MHPMCOUNTER28 = 0xB1C,
454 CSR_MHPMCOUNTER29 = 0xB1D,
455 CSR_MHPMCOUNTER30 = 0xB1E,
456 CSR_MHPMCOUNTER31 = 0xB1F,
457
458 // rv32 only csr register begin
459 CSR_MCYCLEH = 0xB80,
460 CSR_MINSTRETH = 0xB82,
461 CSR_MHPMCOUNTER03H = 0xB83,
462 CSR_MHPMCOUNTER04H = 0xB84,
463 CSR_MHPMCOUNTER05H = 0xB85,
464 CSR_MHPMCOUNTER06H = 0xB86,
465 CSR_MHPMCOUNTER07H = 0xB87,
466 CSR_MHPMCOUNTER08H = 0xB88,
467 CSR_MHPMCOUNTER09H = 0xB89,
468 CSR_MHPMCOUNTER10H = 0xB8A,
469 CSR_MHPMCOUNTER11H = 0xB8B,
470 CSR_MHPMCOUNTER12H = 0xB8C,
471 CSR_MHPMCOUNTER13H = 0xB8D,
472 CSR_MHPMCOUNTER14H = 0xB8E,
473 CSR_MHPMCOUNTER15H = 0xB8F,
474 CSR_MHPMCOUNTER16H = 0xB90,
475 CSR_MHPMCOUNTER17H = 0xB91,
476 CSR_MHPMCOUNTER18H = 0xB92,
477 CSR_MHPMCOUNTER19H = 0xB93,
478 CSR_MHPMCOUNTER20H = 0xB94,
479 CSR_MHPMCOUNTER21H = 0xB95,
480 CSR_MHPMCOUNTER22H = 0xB96,
481 CSR_MHPMCOUNTER23H = 0xB97,
482 CSR_MHPMCOUNTER24H = 0xB98,
483 CSR_MHPMCOUNTER25H = 0xB99,
484 CSR_MHPMCOUNTER26H = 0xB9A,
485 CSR_MHPMCOUNTER27H = 0xB9B,
486 CSR_MHPMCOUNTER28H = 0xB9C,
487 CSR_MHPMCOUNTER29H = 0xB9D,
488 CSR_MHPMCOUNTER30H = 0xB9E,
489 CSR_MHPMCOUNTER31H = 0xB9F,
490 // rv32 only csr register end
491
492 CSR_MHPMEVENT03 = 0x323,
493 CSR_MHPMEVENT04 = 0x324,
494 CSR_MHPMEVENT05 = 0x325,
495 CSR_MHPMEVENT06 = 0x326,
496 CSR_MHPMEVENT07 = 0x327,
497 CSR_MHPMEVENT08 = 0x328,
498 CSR_MHPMEVENT09 = 0x329,
499 CSR_MHPMEVENT10 = 0x32A,
500 CSR_MHPMEVENT11 = 0x32B,
501 CSR_MHPMEVENT12 = 0x32C,
502 CSR_MHPMEVENT13 = 0x32D,
503 CSR_MHPMEVENT14 = 0x32E,
504 CSR_MHPMEVENT15 = 0x32F,
505 CSR_MHPMEVENT16 = 0x330,
506 CSR_MHPMEVENT17 = 0x331,
507 CSR_MHPMEVENT18 = 0x332,
508 CSR_MHPMEVENT19 = 0x333,
509 CSR_MHPMEVENT20 = 0x334,
510 CSR_MHPMEVENT21 = 0x335,
511 CSR_MHPMEVENT22 = 0x336,
512 CSR_MHPMEVENT23 = 0x337,
513 CSR_MHPMEVENT24 = 0x338,
514 CSR_MHPMEVENT25 = 0x339,
515 CSR_MHPMEVENT26 = 0x33A,
516 CSR_MHPMEVENT27 = 0x33B,
517 CSR_MHPMEVENT28 = 0x33C,
518 CSR_MHPMEVENT29 = 0x33D,
519 CSR_MHPMEVENT30 = 0x33E,
520 CSR_MHPMEVENT31 = 0x33F,
521
522 CSR_TSELECT = 0x7A0,
523 CSR_TDATA1 = 0x7A1,
524 CSR_TDATA2 = 0x7A2,
525 CSR_TDATA3 = 0x7A3,
526 CSR_DCSR = 0x7B0,
527 CSR_DPC = 0x7B1,
528 CSR_DSCRATCH = 0x7B2,
529
530 CSR_VSTART = 0x008,
531 CSR_VXSAT = 0x009,
532 CSR_VXRM = 0x00A,
533 CSR_VCSR = 0x00F,
534 CSR_VL = 0xC20,
535 CSR_VTYPE = 0xC21,
536 CSR_VLENB = 0xC22,
537
538 CSR_MNSCRATCH = 0x740,
539 CSR_MNEPC = 0x741,
540 CSR_MNCAUSE = 0x742,
541 CSR_MNSTATUS = 0x744,
542
543 CSR_JVT = 0x017,
544
545 // H-extension (RV64) CSRs
546
547 CSR_MTINST = 0x34A,
548 CSR_MTVAL2 = 0x34B,
549
550 CSR_HSTATUS = 0x600,
551 CSR_HEDELEG = 0x602,
552 CSR_HIDELEG = 0x603,
553 CSR_HIE = 0x604,
554 CSR_HTIMEDELTA = 0x605,
555 CSR_HCOUNTEREN = 0x606,
556 CSR_HGEIE = 0x607,
557
558 CSR_HTVAL = 0x643,
559 CSR_HIP = 0x644,
560 CSR_HVIP = 0x645,
561 CSR_HTINST = 0x64A,
562 CSR_HGEIP = 0xE12,
563
564 CSR_HENVCFG = 0x60A,
565 CSR_HGATP = 0x680,
566 CSR_HCONTEXT = 0x6A8,
567
568 CSR_VSSTATUS = 0x200,
569 CSR_VSIE = 0x204,
570 CSR_VSTVEC = 0x205,
571 CSR_VSSCRATCH = 0x240,
572 CSR_VSEPC = 0x241,
573 CSR_VSCAUSE = 0x242,
574 CSR_VSTVAL = 0x243,
575 CSR_VSIP = 0x244,
576 CSR_VSATP = 0x280
577
578 // H-extension (RV64) CSRs end here
579};
580
581struct CSRMetadata
582{
583 const std::string name;
584 const int physIndex;
585 const uint64_t rvTypes;
586 const uint64_t isaExts;
587 const bool requireSmrnmi = false;
588};
589
590template <typename... T>
591constexpr uint64_t rvTypeFlags(T... args) {
592 return ((1 << args) | ...);
593}
594
595template <typename... T>
596constexpr uint64_t isaExtsFlags(T... isa_exts) {
597 return ((1ULL << (isa_exts - 'a')) | ...);
598}
599
600constexpr uint64_t isaExtsFlags() {
601 return 0ULL;
602}
603
604const std::unordered_map<int, CSRMetadata> CSRData = {
605 {CSR_FFLAGS,
606 {"fflags", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32),
607 isaExtsFlags('f')}},
608 {CSR_FRM,
609 {"frm", MISCREG_FRM, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
610 {CSR_FCSR,
611 {"fcsr", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
612 {CSR_CYCLE,
613 {"cycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
614 {CSR_TIME,
615 {"time", MISCREG_TIME, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
616 {CSR_INSTRET,
617 {"instret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
618 {CSR_HPMCOUNTER03,
619 {"hpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32),
620 isaExtsFlags()}},
621 {CSR_HPMCOUNTER04,
622 {"hpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32),
623 isaExtsFlags()}},
624 {CSR_HPMCOUNTER05,
625 {"hpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32),
626 isaExtsFlags()}},
627 {CSR_HPMCOUNTER06,
628 {"hpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32),
629 isaExtsFlags()}},
630 {CSR_HPMCOUNTER07,
631 {"hpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32),
632 isaExtsFlags()}},
633 {CSR_HPMCOUNTER08,
634 {"hpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32),
635 isaExtsFlags()}},
636 {CSR_HPMCOUNTER09,
637 {"hpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32),
638 isaExtsFlags()}},
639 {CSR_HPMCOUNTER10,
640 {"hpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32),
641 isaExtsFlags()}},
642 {CSR_HPMCOUNTER11,
643 {"hpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32),
644 isaExtsFlags()}},
645 {CSR_HPMCOUNTER12,
646 {"hpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32),
647 isaExtsFlags()}},
648 {CSR_HPMCOUNTER13,
649 {"hpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32),
650 isaExtsFlags()}},
651 {CSR_HPMCOUNTER14,
652 {"hpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32),
653 isaExtsFlags()}},
654 {CSR_HPMCOUNTER15,
655 {"hpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32),
656 isaExtsFlags()}},
657 {CSR_HPMCOUNTER16,
658 {"hpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32),
659 isaExtsFlags()}},
660 {CSR_HPMCOUNTER17,
661 {"hpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32),
662 isaExtsFlags()}},
663 {CSR_HPMCOUNTER18,
664 {"hpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32),
665 isaExtsFlags()}},
666 {CSR_HPMCOUNTER19,
667 {"hpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32),
668 isaExtsFlags()}},
669 {CSR_HPMCOUNTER20,
670 {"hpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32),
671 isaExtsFlags()}},
672 {CSR_HPMCOUNTER21,
673 {"hpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32),
674 isaExtsFlags()}},
675 {CSR_HPMCOUNTER22,
676 {"hpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32),
677 isaExtsFlags()}},
678 {CSR_HPMCOUNTER23,
679 {"hpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32),
680 isaExtsFlags()}},
681 {CSR_HPMCOUNTER24,
682 {"hpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32),
683 isaExtsFlags()}},
684 {CSR_HPMCOUNTER25,
685 {"hpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32),
686 isaExtsFlags()}},
687 {CSR_HPMCOUNTER26,
688 {"hpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32),
689 isaExtsFlags()}},
690 {CSR_HPMCOUNTER27,
691 {"hpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32),
692 isaExtsFlags()}},
693 {CSR_HPMCOUNTER28,
694 {"hpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32),
695 isaExtsFlags()}},
696 {CSR_HPMCOUNTER29,
697 {"hpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32),
698 isaExtsFlags()}},
699 {CSR_HPMCOUNTER30,
700 {"hpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32),
701 isaExtsFlags()}},
702 {CSR_HPMCOUNTER31,
703 {"hpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32),
704 isaExtsFlags()}},
705 {CSR_CYCLEH,
706 {"cycleh", MISCREG_CYCLEH, rvTypeFlags(RV32), isaExtsFlags()}},
707 {CSR_TIMEH,
708 {"timeh", MISCREG_TIMEH, rvTypeFlags(RV32), isaExtsFlags()}},
709 {CSR_INSTRETH,
710 {"instreth", MISCREG_INSTRETH, rvTypeFlags(RV32), isaExtsFlags()}},
711 {CSR_HPMCOUNTER03H,
712 {"hpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32),
713 isaExtsFlags()}},
714 {CSR_HPMCOUNTER04H,
715 {"hpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32),
716 isaExtsFlags()}},
717 {CSR_HPMCOUNTER05H,
718 {"hpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32),
719 isaExtsFlags()}},
720 {CSR_HPMCOUNTER06H,
721 {"hpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32),
722 isaExtsFlags()}},
723 {CSR_HPMCOUNTER07H,
724 {"hpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32),
725 isaExtsFlags()}},
726 {CSR_HPMCOUNTER08H,
727 {"hpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32),
728 isaExtsFlags()}},
729 {CSR_HPMCOUNTER09H,
730 {"hpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32),
731 isaExtsFlags()}},
732 {CSR_HPMCOUNTER10H,
733 {"hpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32),
734 isaExtsFlags()}},
735 {CSR_HPMCOUNTER11H,
736 {"hpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32),
737 isaExtsFlags()}},
738 {CSR_HPMCOUNTER12H,
739 {"hpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32),
740 isaExtsFlags()}},
741 {CSR_HPMCOUNTER13H,
742 {"hpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32),
743 isaExtsFlags()}},
744 {CSR_HPMCOUNTER14H,
745 {"hpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32),
746 isaExtsFlags()}},
747 {CSR_HPMCOUNTER15H,
748 {"hpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32),
749 isaExtsFlags()}},
750 {CSR_HPMCOUNTER16H,
751 {"hpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32),
752 isaExtsFlags()}},
753 {CSR_HPMCOUNTER17H,
754 {"hpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32),
755 isaExtsFlags()}},
756 {CSR_HPMCOUNTER18H,
757 {"hpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32),
758 isaExtsFlags()}},
759 {CSR_HPMCOUNTER19H,
760 {"hpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32),
761 isaExtsFlags()}},
762 {CSR_HPMCOUNTER20H,
763 {"hpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32),
764 isaExtsFlags()}},
765 {CSR_HPMCOUNTER21H,
766 {"hpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32),
767 isaExtsFlags()}},
768 {CSR_HPMCOUNTER22H,
769 {"hpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32),
770 isaExtsFlags()}},
771 {CSR_HPMCOUNTER23H,
772 {"hpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32),
773 isaExtsFlags()}},
774 {CSR_HPMCOUNTER24H,
775 {"hpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32),
776 isaExtsFlags()}},
777 {CSR_HPMCOUNTER25H,
778 {"hpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32),
779 isaExtsFlags()}},
780 {CSR_HPMCOUNTER26H,
781 {"hpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32),
782 isaExtsFlags()}},
783 {CSR_HPMCOUNTER27H,
784 {"hpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32),
785 isaExtsFlags()}},
786 {CSR_HPMCOUNTER28H,
787 {"hpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32),
788 isaExtsFlags()}},
789 {CSR_HPMCOUNTER29H,
790 {"hpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32),
791 isaExtsFlags()}},
792 {CSR_HPMCOUNTER30H,
793 {"hpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32),
794 isaExtsFlags()}},
795 {CSR_HPMCOUNTER31H,
796 {"hpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32),
797 isaExtsFlags()}},
798
799 {CSR_SSTATUS,
800 {"sstatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32),
801 isaExtsFlags('s')}},
802 {CSR_SIE,
803 {"sie", MISCREG_IE, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
804 {CSR_STVEC,
805 {"stvec", MISCREG_STVEC, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
806 {CSR_SCOUNTEREN,
807 {"scounteren", MISCREG_SCOUNTEREN, rvTypeFlags(RV64, RV32),
808 isaExtsFlags('s')}},
809 {CSR_SSCRATCH,
810 {"sscratch", MISCREG_SSCRATCH, rvTypeFlags(RV64, RV32),
811 isaExtsFlags('s')}},
812 {CSR_SEPC,
813 {"sepc", MISCREG_SEPC, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
814 {CSR_SCAUSE,
815 {"scause", MISCREG_SCAUSE, rvTypeFlags(RV64, RV32),
816 isaExtsFlags('s')}},
817 {CSR_STVAL,
818 {"stval", MISCREG_STVAL, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
819 {CSR_SIP,
820 {"sip", MISCREG_IP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
821 {CSR_SATP,
822 {"satp", MISCREG_SATP, rvTypeFlags(RV64, RV32), isaExtsFlags('s')}},
823 {CSR_SENVCFG,
824 {"senvcfg", MISCREG_SENVCFG, rvTypeFlags(RV64, RV32),
825 isaExtsFlags('s')}},
826
827 {CSR_MVENDORID,
828 {"mvendorid", MISCREG_VENDORID, rvTypeFlags(RV64, RV32),
829 isaExtsFlags()}},
830 {CSR_MARCHID,
831 {"marchid", MISCREG_ARCHID, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
832 {CSR_MIMPID,
833 {"mimpid", MISCREG_IMPID, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
834 {CSR_MHARTID,
835 {"mhartid", MISCREG_HARTID, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
836 {CSR_MSTATUS,
837 {"mstatus", MISCREG_STATUS, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
838 {CSR_MISA,
839 {"misa", MISCREG_ISA, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
840 {CSR_MEDELEG,
841 {"medeleg", MISCREG_MEDELEG, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
842 {CSR_MIDELEG,
843 {"mideleg", MISCREG_MIDELEG, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
844 {CSR_MIE,
845 {"mie", MISCREG_IE, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
846 {CSR_MTVEC,
847 {"mtvec", MISCREG_MTVEC, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
848 {CSR_MCOUNTEREN,
849 {"mcounteren", MISCREG_MCOUNTEREN, rvTypeFlags(RV64, RV32),
850 isaExtsFlags()}},
851 {CSR_MSTATUSH,
852 {"mstatush", MISCREG_MSTATUSH, rvTypeFlags(RV32), isaExtsFlags()}},
853 {CSR_MSCRATCH,
854 {"mscratch", MISCREG_MSCRATCH, rvTypeFlags(RV64, RV32),
855 isaExtsFlags()}},
856 {CSR_MEPC,
857 {"mepc", MISCREG_MEPC, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
858 {CSR_MCAUSE,
859 {"mcause", MISCREG_MCAUSE, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
860 {CSR_MTVAL,
861 {"mtval", MISCREG_MTVAL, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
862 {CSR_MIP,
863 {"mip", MISCREG_IP, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
864 {CSR_PMPCFG0,
865 {"pmpcfg0", MISCREG_PMPCFG0, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
866 // pmpcfg1 rv32 only
867 {CSR_PMPCFG1,
868 {"pmpcfg1", MISCREG_PMPCFG1, rvTypeFlags(RV32), isaExtsFlags()}},
869 {CSR_PMPCFG2,
870 {"pmpcfg2", MISCREG_PMPCFG2, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
871 // pmpcfg3 rv32 only
872 {CSR_PMPCFG3,
873 {"pmpcfg3", MISCREG_PMPCFG3, rvTypeFlags(RV32), isaExtsFlags()}},
874 {CSR_PMPADDR00,
875 {"pmpaddr0", MISCREG_PMPADDR00, rvTypeFlags(RV64, RV32),
876 isaExtsFlags()}},
877 {CSR_PMPADDR01,
878 {"pmpaddr1", MISCREG_PMPADDR01, rvTypeFlags(RV64, RV32),
879 isaExtsFlags()}},
880 {CSR_PMPADDR02,
881 {"pmpaddr2", MISCREG_PMPADDR02, rvTypeFlags(RV64, RV32),
882 isaExtsFlags()}},
883 {CSR_PMPADDR03,
884 {"pmpaddr3", MISCREG_PMPADDR03, rvTypeFlags(RV64, RV32),
885 isaExtsFlags()}},
886 {CSR_PMPADDR04,
887 {"pmpaddr4", MISCREG_PMPADDR04, rvTypeFlags(RV64, RV32),
888 isaExtsFlags()}},
889 {CSR_PMPADDR05,
890 {"pmpaddr5", MISCREG_PMPADDR05, rvTypeFlags(RV64, RV32),
891 isaExtsFlags()}},
892 {CSR_PMPADDR06,
893 {"pmpaddr6", MISCREG_PMPADDR06, rvTypeFlags(RV64, RV32),
894 isaExtsFlags()}},
895 {CSR_PMPADDR07,
896 {"pmpaddr7", MISCREG_PMPADDR07, rvTypeFlags(RV64, RV32),
897 isaExtsFlags()}},
898 {CSR_PMPADDR08,
899 {"pmpaddr8", MISCREG_PMPADDR08, rvTypeFlags(RV64, RV32),
900 isaExtsFlags()}},
901 {CSR_PMPADDR09,
902 {"pmpaddr9", MISCREG_PMPADDR09, rvTypeFlags(RV64, RV32),
903 isaExtsFlags()}},
904 {CSR_PMPADDR10,
905 {"pmpaddr10", MISCREG_PMPADDR10, rvTypeFlags(RV64, RV32),
906 isaExtsFlags()}},
907 {CSR_PMPADDR11,
908 {"pmpaddr11", MISCREG_PMPADDR11, rvTypeFlags(RV64, RV32),
909 isaExtsFlags()}},
910 {CSR_PMPADDR12,
911 {"pmpaddr12", MISCREG_PMPADDR12, rvTypeFlags(RV64, RV32),
912 isaExtsFlags()}},
913 {CSR_PMPADDR13,
914 {"pmpaddr13", MISCREG_PMPADDR13, rvTypeFlags(RV64, RV32),
915 isaExtsFlags()}},
916 {CSR_PMPADDR14,
917 {"pmpaddr14", MISCREG_PMPADDR14, rvTypeFlags(RV64, RV32),
918 isaExtsFlags()}},
919 {CSR_PMPADDR15,
920 {"pmpaddr15", MISCREG_PMPADDR15, rvTypeFlags(RV64, RV32),
921 isaExtsFlags()}},
922 {CSR_MCYCLE,
923 {"mcycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
924 {CSR_MINSTRET,
925 {"minstret", MISCREG_INSTRET, rvTypeFlags(RV64, RV32),
926 isaExtsFlags()}},
927 {CSR_MHPMCOUNTER03,
928 {"mhpmcounter03", MISCREG_HPMCOUNTER03, rvTypeFlags(RV64, RV32),
929 isaExtsFlags()}},
930 {CSR_MHPMCOUNTER04,
931 {"mhpmcounter04", MISCREG_HPMCOUNTER04, rvTypeFlags(RV64, RV32),
932 isaExtsFlags()}},
933 {CSR_MHPMCOUNTER05,
934 {"mhpmcounter05", MISCREG_HPMCOUNTER05, rvTypeFlags(RV64, RV32),
935 isaExtsFlags()}},
936 {CSR_MHPMCOUNTER06,
937 {"mhpmcounter06", MISCREG_HPMCOUNTER06, rvTypeFlags(RV64, RV32),
938 isaExtsFlags()}},
939 {CSR_MHPMCOUNTER07,
940 {"mhpmcounter07", MISCREG_HPMCOUNTER07, rvTypeFlags(RV64, RV32),
941 isaExtsFlags()}},
942 {CSR_MHPMCOUNTER08,
943 {"mhpmcounter08", MISCREG_HPMCOUNTER08, rvTypeFlags(RV64, RV32),
944 isaExtsFlags()}},
945 {CSR_MHPMCOUNTER09,
946 {"mhpmcounter09", MISCREG_HPMCOUNTER09, rvTypeFlags(RV64, RV32),
947 isaExtsFlags()}},
948 {CSR_MHPMCOUNTER10,
949 {"mhpmcounter10", MISCREG_HPMCOUNTER10, rvTypeFlags(RV64, RV32),
950 isaExtsFlags()}},
951 {CSR_MHPMCOUNTER11,
952 {"mhpmcounter11", MISCREG_HPMCOUNTER11, rvTypeFlags(RV64, RV32),
953 isaExtsFlags()}},
954 {CSR_MHPMCOUNTER12,
955 {"mhpmcounter12", MISCREG_HPMCOUNTER12, rvTypeFlags(RV64, RV32),
956 isaExtsFlags()}},
957 {CSR_MHPMCOUNTER13,
958 {"mhpmcounter13", MISCREG_HPMCOUNTER13, rvTypeFlags(RV64, RV32),
959 isaExtsFlags()}},
960 {CSR_MHPMCOUNTER14,
961 {"mhpmcounter14", MISCREG_HPMCOUNTER14, rvTypeFlags(RV64, RV32),
962 isaExtsFlags()}},
963 {CSR_MHPMCOUNTER15,
964 {"mhpmcounter15", MISCREG_HPMCOUNTER15, rvTypeFlags(RV64, RV32),
965 isaExtsFlags()}},
966 {CSR_MHPMCOUNTER16,
967 {"mhpmcounter16", MISCREG_HPMCOUNTER16, rvTypeFlags(RV64, RV32),
968 isaExtsFlags()}},
969 {CSR_MHPMCOUNTER17,
970 {"mhpmcounter17", MISCREG_HPMCOUNTER17, rvTypeFlags(RV64, RV32),
971 isaExtsFlags()}},
972 {CSR_MHPMCOUNTER18,
973 {"mhpmcounter18", MISCREG_HPMCOUNTER18, rvTypeFlags(RV64, RV32),
974 isaExtsFlags()}},
975 {CSR_MHPMCOUNTER19,
976 {"mhpmcounter19", MISCREG_HPMCOUNTER19, rvTypeFlags(RV64, RV32),
977 isaExtsFlags()}},
978 {CSR_MHPMCOUNTER20,
979 {"mhpmcounter20", MISCREG_HPMCOUNTER20, rvTypeFlags(RV64, RV32),
980 isaExtsFlags()}},
981 {CSR_MHPMCOUNTER21,
982 {"mhpmcounter21", MISCREG_HPMCOUNTER21, rvTypeFlags(RV64, RV32),
983 isaExtsFlags()}},
984 {CSR_MHPMCOUNTER22,
985 {"mhpmcounter22", MISCREG_HPMCOUNTER22, rvTypeFlags(RV64, RV32),
986 isaExtsFlags()}},
987 {CSR_MHPMCOUNTER23,
988 {"mhpmcounter23", MISCREG_HPMCOUNTER23, rvTypeFlags(RV64, RV32),
989 isaExtsFlags()}},
990 {CSR_MHPMCOUNTER24,
991 {"mhpmcounter24", MISCREG_HPMCOUNTER24, rvTypeFlags(RV64, RV32),
992 isaExtsFlags()}},
993 {CSR_MHPMCOUNTER25,
994 {"mhpmcounter25", MISCREG_HPMCOUNTER25, rvTypeFlags(RV64, RV32),
995 isaExtsFlags()}},
996 {CSR_MHPMCOUNTER26,
997 {"mhpmcounter26", MISCREG_HPMCOUNTER26, rvTypeFlags(RV64, RV32),
998 isaExtsFlags()}},
999 {CSR_MHPMCOUNTER27,
1000 {"mhpmcounter27", MISCREG_HPMCOUNTER27, rvTypeFlags(RV64, RV32),
1001 isaExtsFlags()}},
1002 {CSR_MHPMCOUNTER28,
1003 {"mhpmcounter28", MISCREG_HPMCOUNTER28, rvTypeFlags(RV64, RV32),
1004 isaExtsFlags()}},
1005 {CSR_MHPMCOUNTER29,
1006 {"mhpmcounter29", MISCREG_HPMCOUNTER29, rvTypeFlags(RV64, RV32),
1007 isaExtsFlags()}},
1008 {CSR_MHPMCOUNTER30,
1009 {"mhpmcounter30", MISCREG_HPMCOUNTER30, rvTypeFlags(RV64, RV32),
1010 isaExtsFlags()}},
1011 {CSR_MHPMCOUNTER31,
1012 {"mhpmcounter31", MISCREG_HPMCOUNTER31, rvTypeFlags(RV64, RV32),
1013 isaExtsFlags()}},
1014
1015 {CSR_MCYCLEH,
1016 {"mcycleh", MISCREG_CYCLEH, rvTypeFlags(RV32), isaExtsFlags()}},
1017 {CSR_MINSTRETH,
1018 {"minstreth", MISCREG_INSTRETH, rvTypeFlags(RV32), isaExtsFlags()}},
1019 {CSR_MHPMCOUNTER03H,
1020 {"mhpmcounter03h", MISCREG_HPMCOUNTER03H, rvTypeFlags(RV32),
1021 isaExtsFlags()}},
1022 {CSR_MHPMCOUNTER04H,
1023 {"mhpmcounter04h", MISCREG_HPMCOUNTER04H, rvTypeFlags(RV32),
1024 isaExtsFlags()}},
1025 {CSR_MHPMCOUNTER05H,
1026 {"mhpmcounter05h", MISCREG_HPMCOUNTER05H, rvTypeFlags(RV32),
1027 isaExtsFlags()}},
1028 {CSR_MHPMCOUNTER06H,
1029 {"mhpmcounter06h", MISCREG_HPMCOUNTER06H, rvTypeFlags(RV32),
1030 isaExtsFlags()}},
1031 {CSR_MHPMCOUNTER07H,
1032 {"mhpmcounter07h", MISCREG_HPMCOUNTER07H, rvTypeFlags(RV32),
1033 isaExtsFlags()}},
1034 {CSR_MHPMCOUNTER08H,
1035 {"mhpmcounter08h", MISCREG_HPMCOUNTER08H, rvTypeFlags(RV32),
1036 isaExtsFlags()}},
1037 {CSR_MHPMCOUNTER09H,
1038 {"mhpmcounter09h", MISCREG_HPMCOUNTER09H, rvTypeFlags(RV32),
1039 isaExtsFlags()}},
1040 {CSR_MHPMCOUNTER10H,
1041 {"mhpmcounter10h", MISCREG_HPMCOUNTER10H, rvTypeFlags(RV32),
1042 isaExtsFlags()}},
1043 {CSR_MHPMCOUNTER11H,
1044 {"mhpmcounter11h", MISCREG_HPMCOUNTER11H, rvTypeFlags(RV32),
1045 isaExtsFlags()}},
1046 {CSR_MHPMCOUNTER12H,
1047 {"mhpmcounter12h", MISCREG_HPMCOUNTER12H, rvTypeFlags(RV32),
1048 isaExtsFlags()}},
1049 {CSR_MHPMCOUNTER13H,
1050 {"mhpmcounter13h", MISCREG_HPMCOUNTER13H, rvTypeFlags(RV32),
1051 isaExtsFlags()}},
1052 {CSR_MHPMCOUNTER14H,
1053 {"mhpmcounter14h", MISCREG_HPMCOUNTER14H, rvTypeFlags(RV32),
1054 isaExtsFlags()}},
1055 {CSR_MHPMCOUNTER15H,
1056 {"mhpmcounter15h", MISCREG_HPMCOUNTER15H, rvTypeFlags(RV32),
1057 isaExtsFlags()}},
1058 {CSR_MHPMCOUNTER16H,
1059 {"mhpmcounter16h", MISCREG_HPMCOUNTER16H, rvTypeFlags(RV32),
1060 isaExtsFlags()}},
1061 {CSR_MHPMCOUNTER17H,
1062 {"mhpmcounter17h", MISCREG_HPMCOUNTER17H, rvTypeFlags(RV32),
1063 isaExtsFlags()}},
1064 {CSR_MHPMCOUNTER18H,
1065 {"mhpmcounter18h", MISCREG_HPMCOUNTER18H, rvTypeFlags(RV32),
1066 isaExtsFlags()}},
1067 {CSR_MHPMCOUNTER19H,
1068 {"mhpmcounter19h", MISCREG_HPMCOUNTER19H, rvTypeFlags(RV32),
1069 isaExtsFlags()}},
1070 {CSR_MHPMCOUNTER20H,
1071 {"mhpmcounter20h", MISCREG_HPMCOUNTER20H, rvTypeFlags(RV32),
1072 isaExtsFlags()}},
1073 {CSR_MHPMCOUNTER21H,
1074 {"mhpmcounter21h", MISCREG_HPMCOUNTER21H, rvTypeFlags(RV32),
1075 isaExtsFlags()}},
1076 {CSR_MHPMCOUNTER22H,
1077 {"mhpmcounter22h", MISCREG_HPMCOUNTER22H, rvTypeFlags(RV32),
1078 isaExtsFlags()}},
1079 {CSR_MHPMCOUNTER23H,
1080 {"mhpmcounter23h", MISCREG_HPMCOUNTER23H, rvTypeFlags(RV32),
1081 isaExtsFlags()}},
1082 {CSR_MHPMCOUNTER24H,
1083 {"mhpmcounter24h", MISCREG_HPMCOUNTER24H, rvTypeFlags(RV32),
1084 isaExtsFlags()}},
1085 {CSR_MHPMCOUNTER25H,
1086 {"mhpmcounter25h", MISCREG_HPMCOUNTER25H, rvTypeFlags(RV32),
1087 isaExtsFlags()}},
1088 {CSR_MHPMCOUNTER26H,
1089 {"mhpmcounter26h", MISCREG_HPMCOUNTER26H, rvTypeFlags(RV32),
1090 isaExtsFlags()}},
1091 {CSR_MHPMCOUNTER27H,
1092 {"mhpmcounter27h", MISCREG_HPMCOUNTER27H, rvTypeFlags(RV32),
1093 isaExtsFlags()}},
1094 {CSR_MHPMCOUNTER28H,
1095 {"mhpmcounter28h", MISCREG_HPMCOUNTER28H, rvTypeFlags(RV32),
1096 isaExtsFlags()}},
1097 {CSR_MHPMCOUNTER29H,
1098 {"mhpmcounter29h", MISCREG_HPMCOUNTER29H, rvTypeFlags(RV32),
1099 isaExtsFlags()}},
1100 {CSR_MHPMCOUNTER30H,
1101 {"mhpmcounter30h", MISCREG_HPMCOUNTER30H, rvTypeFlags(RV32),
1102 isaExtsFlags()}},
1103 {CSR_MHPMCOUNTER31H,
1104 {"mhpmcounter31h", MISCREG_HPMCOUNTER31H, rvTypeFlags(RV32),
1105 isaExtsFlags()}},
1106
1107 {CSR_MHPMEVENT03,
1108 {"mhpmevent03", MISCREG_HPMEVENT03, rvTypeFlags(RV64, RV32),
1109 isaExtsFlags()}},
1110 {CSR_MHPMEVENT04,
1111 {"mhpmevent04", MISCREG_HPMEVENT04, rvTypeFlags(RV64, RV32),
1112 isaExtsFlags()}},
1113 {CSR_MHPMEVENT05,
1114 {"mhpmevent05", MISCREG_HPMEVENT05, rvTypeFlags(RV64, RV32),
1115 isaExtsFlags()}},
1116 {CSR_MHPMEVENT06,
1117 {"mhpmevent06", MISCREG_HPMEVENT06, rvTypeFlags(RV64, RV32),
1118 isaExtsFlags()}},
1119 {CSR_MHPMEVENT07,
1120 {"mhpmevent07", MISCREG_HPMEVENT07, rvTypeFlags(RV64, RV32),
1121 isaExtsFlags()}},
1122 {CSR_MHPMEVENT08,
1123 {"mhpmevent08", MISCREG_HPMEVENT08, rvTypeFlags(RV64, RV32),
1124 isaExtsFlags()}},
1125 {CSR_MHPMEVENT09,
1126 {"mhpmevent09", MISCREG_HPMEVENT09, rvTypeFlags(RV64, RV32),
1127 isaExtsFlags()}},
1128 {CSR_MHPMEVENT10,
1129 {"mhpmevent10", MISCREG_HPMEVENT10, rvTypeFlags(RV64, RV32),
1130 isaExtsFlags()}},
1131 {CSR_MHPMEVENT11,
1132 {"mhpmevent11", MISCREG_HPMEVENT11, rvTypeFlags(RV64, RV32),
1133 isaExtsFlags()}},
1134 {CSR_MHPMEVENT12,
1135 {"mhpmevent12", MISCREG_HPMEVENT12, rvTypeFlags(RV64, RV32),
1136 isaExtsFlags()}},
1137 {CSR_MHPMEVENT13,
1138 {"mhpmevent13", MISCREG_HPMEVENT13, rvTypeFlags(RV64, RV32),
1139 isaExtsFlags()}},
1140 {CSR_MHPMEVENT14,
1141 {"mhpmevent14", MISCREG_HPMEVENT14, rvTypeFlags(RV64, RV32),
1142 isaExtsFlags()}},
1143 {CSR_MHPMEVENT15,
1144 {"mhpmevent15", MISCREG_HPMEVENT15, rvTypeFlags(RV64, RV32),
1145 isaExtsFlags()}},
1146 {CSR_MHPMEVENT16,
1147 {"mhpmevent16", MISCREG_HPMEVENT16, rvTypeFlags(RV64, RV32),
1148 isaExtsFlags()}},
1149 {CSR_MHPMEVENT17,
1150 {"mhpmevent17", MISCREG_HPMEVENT17, rvTypeFlags(RV64, RV32),
1151 isaExtsFlags()}},
1152 {CSR_MHPMEVENT18,
1153 {"mhpmevent18", MISCREG_HPMEVENT18, rvTypeFlags(RV64, RV32),
1154 isaExtsFlags()}},
1155 {CSR_MHPMEVENT19,
1156 {"mhpmevent19", MISCREG_HPMEVENT19, rvTypeFlags(RV64, RV32),
1157 isaExtsFlags()}},
1158 {CSR_MHPMEVENT20,
1159 {"mhpmevent20", MISCREG_HPMEVENT20, rvTypeFlags(RV64, RV32),
1160 isaExtsFlags()}},
1161 {CSR_MHPMEVENT21,
1162 {"mhpmevent21", MISCREG_HPMEVENT21, rvTypeFlags(RV64, RV32),
1163 isaExtsFlags()}},
1164 {CSR_MHPMEVENT22,
1165 {"mhpmevent22", MISCREG_HPMEVENT22, rvTypeFlags(RV64, RV32),
1166 isaExtsFlags()}},
1167 {CSR_MHPMEVENT23,
1168 {"mhpmevent23", MISCREG_HPMEVENT23, rvTypeFlags(RV64, RV32),
1169 isaExtsFlags()}},
1170 {CSR_MHPMEVENT24,
1171 {"mhpmevent24", MISCREG_HPMEVENT24, rvTypeFlags(RV64, RV32),
1172 isaExtsFlags()}},
1173 {CSR_MHPMEVENT25,
1174 {"mhpmevent25", MISCREG_HPMEVENT25, rvTypeFlags(RV64, RV32),
1175 isaExtsFlags()}},
1176 {CSR_MHPMEVENT26,
1177 {"mhpmevent26", MISCREG_HPMEVENT26, rvTypeFlags(RV64, RV32),
1178 isaExtsFlags()}},
1179 {CSR_MHPMEVENT27,
1180 {"mhpmevent27", MISCREG_HPMEVENT27, rvTypeFlags(RV64, RV32),
1181 isaExtsFlags()}},
1182 {CSR_MHPMEVENT28,
1183 {"mhpmevent28", MISCREG_HPMEVENT28, rvTypeFlags(RV64, RV32),
1184 isaExtsFlags()}},
1185 {CSR_MHPMEVENT29,
1186 {"mhpmevent29", MISCREG_HPMEVENT29, rvTypeFlags(RV64, RV32),
1187 isaExtsFlags()}},
1188 {CSR_MHPMEVENT30,
1189 {"mhpmevent30", MISCREG_HPMEVENT30, rvTypeFlags(RV64, RV32),
1190 isaExtsFlags()}},
1191 {CSR_MHPMEVENT31,
1192 {"mhpmevent31", MISCREG_HPMEVENT31, rvTypeFlags(RV64, RV32),
1193 isaExtsFlags()}},
1194
1195 {CSR_TSELECT,
1196 {"tselect", MISCREG_TSELECT, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1197 {CSR_TDATA1,
1198 {"tdata1", MISCREG_TDATA1, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1199 {CSR_TDATA2,
1200 {"tdata2", MISCREG_TDATA2, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1201 {CSR_TDATA3,
1202 {"tdata3", MISCREG_TDATA3, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1203 {CSR_DCSR,
1204 {"dcsr", MISCREG_DCSR, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1205 {CSR_DPC,
1206 {"dpc", MISCREG_DPC, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1207 {CSR_DSCRATCH,
1208 {"dscratch", MISCREG_DSCRATCH, rvTypeFlags(RV64, RV32),
1209 isaExtsFlags()}},
1210
1211 {CSR_VSTART,
1212 {"vstart", MISCREG_VSTART, rvTypeFlags(RV64, RV32),
1213 isaExtsFlags('v')}},
1214 {CSR_VXSAT,
1215 {"vxsat", MISCREG_VXSAT, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1216 {CSR_VXRM,
1217 {"vxrm", MISCREG_VXRM, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1218 {CSR_VCSR,
1219 {"vcsr", MISCREG_VCSR, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1220 {CSR_VL,
1221 {"vl", MISCREG_VL, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1222 {CSR_VTYPE,
1223 {"vtype", MISCREG_VTYPE, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1224 {CSR_VLENB,
1225 {"VLENB", MISCREG_VLENB, rvTypeFlags(RV64, RV32), isaExtsFlags('v')}},
1226
1227 {CSR_MNSCRATCH,
1228 {"mnscratch", MISCREG_MNSCRATCH, rvTypeFlags(RV64, RV32),
1229 isaExtsFlags(), true}},
1230 {CSR_MNEPC,
1231 {"mnepc", MISCREG_MNEPC, rvTypeFlags(RV64, RV32), isaExtsFlags(),
1232 true}},
1233 {CSR_MNCAUSE,
1234 {"mncause", MISCREG_MNCAUSE, rvTypeFlags(RV64, RV32), isaExtsFlags(),
1235 true}},
1236 {CSR_MNSTATUS,
1237 {"mnstatus", MISCREG_MNSTATUS, rvTypeFlags(RV64, RV32),
1238 isaExtsFlags(), true}},
1239
1240 {CSR_JVT,
1241 {"jvt", MISCREG_JVT, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
1242
1243 // H-extension CSR -> MISCREG mappings
1244 {CSR_MTINST,
1245 {"mtinst", MISCREG_MTINST, rvTypeFlags(RV64),
1246 isaExtsFlags('h')}},
1247 {CSR_MTVAL2,
1248 {"mtval2", MISCREG_MTVAL2, rvTypeFlags(RV64),
1249 isaExtsFlags('h')}},
1250
1251 {CSR_HSTATUS,
1252 {"hstatus", MISCREG_HSTATUS, rvTypeFlags(RV64),
1253 isaExtsFlags('h')}},
1254 {CSR_HEDELEG,
1255 {"hedeleg", MISCREG_HEDELEG, rvTypeFlags(RV64),
1256 isaExtsFlags('h')}},
1257 {CSR_HIDELEG,
1258 {"hideleg", MISCREG_HIDELEG, rvTypeFlags(RV64),
1259 isaExtsFlags('h')}},
1260 {CSR_HIE,
1261 {"hie", MISCREG_IE, rvTypeFlags(RV64),
1262 isaExtsFlags('h')}},
1263 {CSR_HCOUNTEREN,
1264 {"hcounteren", MISCREG_HCOUNTEREN, rvTypeFlags(RV64),
1265 isaExtsFlags('h')}},
1266 {CSR_HGEIE,
1267 {"hgeie", MISCREG_HGEIE, rvTypeFlags(RV64),
1268 isaExtsFlags('h')}},
1269 {CSR_HTVAL,
1270 {"htval", MISCREG_HTVAL, rvTypeFlags(RV64),
1271 isaExtsFlags('h')}},
1272 {CSR_HIP,
1273 {"hip", MISCREG_IP, rvTypeFlags(RV64),
1274 isaExtsFlags('h')}},
1275 {CSR_HVIP,
1276 {"hvip", MISCREG_HVIP, rvTypeFlags(RV64),
1277 isaExtsFlags('h')}},
1278 {CSR_HTINST,
1279 {"htinst", MISCREG_HTINST, rvTypeFlags(RV64),
1280 isaExtsFlags('h')}},
1281 {CSR_HGEIP,
1282 {"hgeip", MISCREG_HGEIP, rvTypeFlags(RV64),
1283 isaExtsFlags('h')}},
1284 {CSR_HENVCFG,
1285 {"henvcfg", MISCREG_HENVCFG, rvTypeFlags(RV64),
1286 isaExtsFlags('h')}},
1287 {CSR_HGATP,
1288 {"hgatp", MISCREG_HGATP, rvTypeFlags(RV64),
1289 isaExtsFlags('h')}},
1290 {CSR_HCONTEXT,
1291 {"hcontext", MISCREG_HCONTEXT, rvTypeFlags(RV64),
1292 isaExtsFlags('h')}},
1293 {CSR_HTIMEDELTA,
1294 {"htimedelta", MISCREG_HTIMEDELTA, rvTypeFlags(RV64),
1295 isaExtsFlags('h')}},
1296
1297 {CSR_VSSTATUS,
1298 {"vsstatus", MISCREG_VSSTATUS, rvTypeFlags(RV64),
1299 isaExtsFlags('h')}},
1300 {CSR_VSIE,
1301 {"vsie", MISCREG_IE, rvTypeFlags(RV64),
1302 isaExtsFlags('h')}},
1303 {CSR_VSTVEC,
1304 {"vstvec", MISCREG_VSTVEC, rvTypeFlags(RV64),
1305 isaExtsFlags('h')}},
1306 {CSR_VSSCRATCH,
1307 {"vsscratch", MISCREG_VSSCRATCH, rvTypeFlags(RV64),
1308 isaExtsFlags('h')}},
1309 {CSR_VSEPC,
1310 {"vsepc", MISCREG_VSEPC, rvTypeFlags(RV64),
1311 isaExtsFlags('h')}},
1312 {CSR_VSCAUSE,
1313 {"vscause", MISCREG_VSCAUSE, rvTypeFlags(RV64),
1314 isaExtsFlags('h')}},
1315 {CSR_VSTVAL,
1316 {"vstval", MISCREG_VSTVAL, rvTypeFlags(RV64),
1317 isaExtsFlags('h')}},
1318 {CSR_VSIP,
1319 {"vsip", MISCREG_IP, rvTypeFlags(RV64),
1320 isaExtsFlags('h')}},
1321 {CSR_VSATP,
1322 {"vsatp", MISCREG_VSATP, rvTypeFlags(RV64),
1323 isaExtsFlags('h')}},
1324};
1325
1333BitUnion64(STATUS)
1334 Bitfield<63> rv64_sd;
1335 Bitfield<39> mpv; // H-extension
1336 Bitfield<38> gva; // H-extension
1337 Bitfield<37> mbe;
1338 Bitfield<36> sbe;
1339 Bitfield<35, 34> sxl;
1340 Bitfield<33, 32> uxl;
1341 Bitfield<31> rv32_sd;
1342 Bitfield<22> tsr;
1343 Bitfield<21> tw;
1344 Bitfield<20> tvm;
1345 Bitfield<19> mxr;
1346 Bitfield<18> sum;
1347 Bitfield<17> mprv;
1348 Bitfield<16, 15> xs;
1349 Bitfield<14, 13> fs;
1350 Bitfield<12, 11> mpp;
1351 Bitfield<10, 9> vs;
1352 Bitfield<8> spp;
1353 Bitfield<7> mpie;
1354 Bitfield<6> ube;
1355 Bitfield<5> spie;
1356 Bitfield<3> mie;
1357 Bitfield<1> sie;
1358EndBitUnion(STATUS)
1359
1360
1361// H-extension
1362BitUnion64(HSTATUS)
1363 Bitfield<33, 32> vsxl;
1364 Bitfield<22> vtsr;
1365 Bitfield<21> vtw;
1366 Bitfield<20> vtvm;
1367 Bitfield<17, 12> vgein;
1368 Bitfield<9> hu;
1369 Bitfield<8> spvp;
1370 Bitfield<7> spv;
1371 Bitfield<6> gva;
1372 Bitfield<5> vsbe;
1373EndBitUnion(HSTATUS)
1374
1375
1381BitUnion64(NSTATUS)
1382 Bitfield<12, 11> mnpp;
1383 Bitfield<7> mnv;
1384 Bitfield<3> nmie;
1385EndBitUnion(NSTATUS)
1386
1392BitUnion64(MISA)
1393 Bitfield<63, 62> rv64_mxl;
1394 Bitfield<31, 30> rv32_mxl;
1395 Bitfield<23> rvx;
1396 Bitfield<21> rvv;
1397 Bitfield<20> rvu;
1398 Bitfield<19> rvt;
1399 Bitfield<18> rvs;
1400 Bitfield<16> rvq;
1401 Bitfield<15> rvp;
1402 Bitfield<13> rvn;
1403 Bitfield<12> rvm;
1404 Bitfield<11> rvl;
1405 Bitfield<10> rvk;
1406 Bitfield<9> rvj;
1407 Bitfield<8> rvi;
1408 Bitfield<7> rvh;
1409 Bitfield<6> rvg;
1410 Bitfield<5> rvf;
1411 Bitfield<4> rve;
1412 Bitfield<3> rvd;
1413 Bitfield<2> rvc;
1414 Bitfield<1> rvb;
1415 Bitfield<0> rva;
1416EndBitUnion(MISA)
1417
1424BitUnion64(INTERRUPT)
1425 Bitfield<63,16> local;
1426 Bitfield<12> sgei; // H-extension
1427 Bitfield<11> mei;
1428 Bitfield<10> vsei; // H-extension
1429 Bitfield<9> sei;
1430 Bitfield<7> mti;
1431 Bitfield<6> vsti; // H-extension
1432 Bitfield<5> sti;
1433 Bitfield<3> msi;
1434 Bitfield<2> vssi; // H-extension
1435 Bitfield<1> ssi;
1436EndBitUnion(INTERRUPT)
1437
1438
1439// From the RISCV specification version 20240411, volume 2,
1440// section 10.1.10, page 98
1441BitUnion64(SENVCFG)
1442 Bitfield<63,34> wpri_1;
1443 Bitfield<33,32> pmm;
1444 Bitfield<31,8> wpri_2;
1445 Bitfield<7> cbze;
1446 Bitfield<6> cbcfe;
1447 Bitfield<5,4> cbie;
1448 Bitfield<3,1> wpri_3;
1449 Bitfield<0> fiom;
1450EndBitUnion(SENVCFG)
1451
1452BitUnion64(JVT)
1453 Bitfield<63,6> base;
1454 Bitfield<5,0> mode;
1455EndBitUnion(JVT)
1456
1457const off_t MXL_OFFSETS[enums::Num_RiscvType] = {
1458 [RV32] = (sizeof(uint32_t) * 8 - 2),
1459 [RV64] = (sizeof(uint64_t) * 8 - 2),
1460};
1461const off_t MBE_OFFSET[enums::Num_RiscvType] = {
1462 [RV32] = 5,
1463 [RV64] = 37,
1464};
1465const off_t SBE_OFFSET[enums::Num_RiscvType] = {
1466 [RV32] = 4,
1467 [RV64] = 36,
1468};
1469const off_t SXL_OFFSET = 34;
1470const off_t VSXL_OFFSET = 32; // H-extension
1471const off_t UXL_OFFSET = 32;
1472const off_t FS_OFFSET = 13;
1473const off_t VS_OFFSET = 9;
1474const off_t FRM_OFFSET = 5;
1475
1476const RegVal ISA_MXL_MASKS[enums::Num_RiscvType] = {
1477 [RV32] = 3ULL << MXL_OFFSETS[RV32],
1478 [RV64] = 3ULL << MXL_OFFSETS[RV64],
1479};
1480const RegVal ISA_EXT_MASK = mask(26);
1481const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
1482const RegVal MISA_MASKS[enums::Num_RiscvType] = {
1483 [RV32] = ISA_MXL_MASKS[RV32] | ISA_EXT_MASK,
1484 [RV64] = ISA_MXL_MASKS[RV64] | ISA_EXT_MASK,
1485};
1486
1487
1488const RegVal STATUS_SD_MASKS[enums::Num_RiscvType] = {
1489 [RV32] = 1ULL << ((sizeof(uint32_t) * 8) - 1),
1490 [RV64] = 1ULL << ((sizeof(uint64_t) * 8) - 1),
1491};
1492const RegVal STATUS_MBE_MASK[enums::Num_RiscvType] = {
1493 [RV32] = 1ULL << MBE_OFFSET[RV32],
1494 [RV64] = 1ULL << MBE_OFFSET[RV64],
1495};
1496const RegVal STATUS_SBE_MASK[enums::Num_RiscvType] = {
1497 [RV32] = 1ULL << SBE_OFFSET[RV32],
1498 [RV64] = 1ULL << SBE_OFFSET[RV64],
1499};
1500// These first two offsets only work for RV64
1501const RegVal STATUS_MPV_MASK = 1LL << 39; // H-extension
1502const RegVal STATUS_GVA_MASK = 1LL << 38; // H-extension
1503const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
1504const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
1505const RegVal STATUS_TSR_MASK = 1ULL << 22;
1506const RegVal STATUS_TW_MASK = 1ULL << 21;
1507const RegVal STATUS_TVM_MASK = 1ULL << 20;
1508const RegVal STATUS_MXR_MASK = 1ULL << 19;
1509const RegVal STATUS_SUM_MASK = 1ULL << 18;
1510const RegVal STATUS_MPRV_MASK = 1ULL << 17;
1511const RegVal STATUS_XS_MASK = 3ULL << 15;
1512const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
1513const RegVal STATUS_MPP_MASK = 3ULL << 11;
1514const RegVal STATUS_VS_MASK = 3ULL << VS_OFFSET;
1515const RegVal STATUS_SPP_MASK = 1ULL << 8;
1516const RegVal STATUS_MPIE_MASK = 1ULL << 7;
1517const RegVal STATUS_UBE_MASK = 1ULL << 6;
1518const RegVal STATUS_SPIE_MASK = 1ULL << 5;
1519const RegVal STATUS_MIE_MASK = 1ULL << 3;
1520const RegVal STATUS_SIE_MASK = 1ULL << 1;
1521
1522// H-extension
1523const RegVal HSTATUS_VSXL_MASK = 3ULL << VSXL_OFFSET;
1524const RegVal HSTATUS_VTSR_MASK = 1ULL << 22;
1525const RegVal HSTATUS_VTW_MASK = 1ULL << 21;
1526const RegVal HSTATUS_VTVM_MASK = 1ULL << 20;
1527const RegVal HSTATUS_VGEIN_MASK = 63ULL << 12;
1528const RegVal HSTATUS_HU_MASK = 1ULL << 9;
1529const RegVal HSTATUS_SPVP_MASK = 1ULL << 8;
1530const RegVal HSTATUS_SPV_MASK = 1ULL << 7;
1531const RegVal HSTATUS_GVA_MASK = 1LL << 6;
1532const RegVal HSTATUS_VSBE_MASK = 1ULL << 5;
1533
1534const RegVal
1535MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1536 [RV32] = {
1537 [enums::M] = STATUS_SD_MASKS[RV32] |
1538 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1539 STATUS_MPIE_MASK | STATUS_MIE_MASK,
1540 [enums::MU] = STATUS_SD_MASKS[RV32] | STATUS_TW_MASK |
1541 STATUS_MPRV_MASK |
1542 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1543 STATUS_MPP_MASK | STATUS_MPIE_MASK | STATUS_MIE_MASK,
1544 [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK |
1545 STATUS_TW_MASK | STATUS_TVM_MASK | STATUS_MXR_MASK |
1546 STATUS_SUM_MASK | STATUS_MPRV_MASK |
1547 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1548 STATUS_MPP_MASK | STATUS_SPP_MASK |
1549 STATUS_MPIE_MASK | STATUS_SPIE_MASK |
1550 STATUS_MIE_MASK | STATUS_SIE_MASK,
1551 },
1552 [RV64] = {
1553 [enums::M] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] |
1554 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1555 STATUS_MPIE_MASK | STATUS_MIE_MASK,
1556 [enums::MU] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] |
1557 STATUS_UXL_MASK | STATUS_TW_MASK | STATUS_MPRV_MASK |
1558 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1559 STATUS_MPP_MASK | STATUS_MPIE_MASK | STATUS_MIE_MASK,
1560 [enums::MSU] = STATUS_SD_MASKS[RV64] |
1561 STATUS_MBE_MASK[RV64] | STATUS_SBE_MASK[RV64] |
1562 STATUS_SXL_MASK | STATUS_UXL_MASK |
1563 STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK |
1564 STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK |
1565 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1566 STATUS_MPP_MASK | STATUS_SPP_MASK |
1567 STATUS_MPIE_MASK | STATUS_SPIE_MASK |
1568 STATUS_MIE_MASK | STATUS_SIE_MASK,
1569 [enums::MHSU] = STATUS_SD_MASKS[RV64] |
1570 STATUS_MPV_MASK | STATUS_GVA_MASK | // H-extension
1571 STATUS_MBE_MASK[RV64] | STATUS_SBE_MASK[RV64] |
1572 STATUS_SXL_MASK | STATUS_UXL_MASK |
1573 STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK |
1574 STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK |
1575 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1576 STATUS_MPP_MASK | STATUS_SPP_MASK |
1577 STATUS_MPIE_MASK | STATUS_SPIE_MASK |
1578 STATUS_MIE_MASK | STATUS_SIE_MASK,
1579 },
1580};
1581// rv32 only
1582const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet] = {
1583 [enums::M] = STATUS_MBE_MASK[RV32],
1584 [enums::MU] = STATUS_MBE_MASK[RV32],
1585 [enums::MSU] = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32],
1586};
1587
1588const RegVal
1589HSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1590 [RV32] = {
1591 [enums::M] = 0ULL,
1592 [enums::MU] = 0ULL,
1593 [enums::MSU] = 0ULL,
1594 [enums::MHSU] = 0ULL,
1595 },
1596 [RV64] = {
1597 [enums::M] = 0ULL,
1598 [enums::MU] = 0ULL,
1599 [enums::MSU] = 0ULL,
1600 [enums::MHSU] = HSTATUS_VSXL_MASK | HSTATUS_VTSR_MASK |
1601 HSTATUS_VTW_MASK | HSTATUS_VTVM_MASK |
1602 HSTATUS_VGEIN_MASK | HSTATUS_HU_MASK |
1603 HSTATUS_SPVP_MASK | HSTATUS_SPV_MASK |
1604 HSTATUS_GVA_MASK | HSTATUS_VSBE_MASK,
1605 },
1606};
1607const RegVal
1608SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1609 [RV32] = {
1610 [enums::M] = 0ULL,
1611 [enums::MU] = 0ULL,
1612 [enums::MSU] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK |
1613 STATUS_SUM_MASK |
1614 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1615 STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK,
1616 },
1617 [RV64] = {
1618 [enums::M] = 0ULL,
1619 [enums::MU] = 0ULL,
1620 [enums::MSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK |
1621 STATUS_MXR_MASK | STATUS_SUM_MASK |
1622 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1623 STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK,
1624 [enums::MHSU] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK |
1625 STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_UBE_MASK |
1626 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1627 STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_SIE_MASK,
1628 },
1629};
1630
1631const RegVal LOCAL_MASK = mask(63,16);
1632const RegVal SGEI_MASK = 1ULL << 12; // H-extension
1633const RegVal MEI_MASK = 1ULL << 11;
1634const RegVal VSEI_MASK = 1ULL << 10; // H-extension
1635const RegVal SEI_MASK = 1ULL << 9;
1636const RegVal MTI_MASK = 1ULL << 7;
1637const RegVal VSTI_MASK = 1ULL << 6; // H-extension
1638const RegVal STI_MASK = 1ULL << 5;
1639const RegVal MSI_MASK = 1ULL << 3;
1640const RegVal VSSI_MASK = 1ULL << 2; // H-extension
1641const RegVal SSI_MASK = 1ULL << 1;
1642
1643const RegVal MI_MASK[enums::Num_PrivilegeModeSet] = {
1644 [enums::M] = LOCAL_MASK |
1645 MEI_MASK| MTI_MASK | MSI_MASK,
1646 [enums::MU] = LOCAL_MASK |
1647 MEI_MASK| MTI_MASK | MSI_MASK,
1648 [enums::MSU] = LOCAL_MASK |
1649 MEI_MASK | SEI_MASK |
1650 MTI_MASK | STI_MASK |
1651 MSI_MASK | SSI_MASK,
1652 [enums::MHSU] = LOCAL_MASK |
1653 MEI_MASK | VSEI_MASK | SEI_MASK |
1654 MTI_MASK | VSTI_MASK | STI_MASK |
1655 MSI_MASK | VSSI_MASK | SSI_MASK | SGEI_MASK,
1656};
1657
1658const RegVal SI_MASK[enums::Num_PrivilegeModeSet] = {
1659 [enums::M] = LOCAL_MASK,
1660 [enums::MU] = LOCAL_MASK,
1661 [enums::MSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
1662 [enums::MHSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
1663};
1664const RegVal MIDELEG_MASK[enums::Num_PrivilegeModeSet] = {
1665 [enums::M] = LOCAL_MASK,
1666 [enums::MU] = LOCAL_MASK,
1667 [enums::MSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
1668 [enums::MHSU] = LOCAL_MASK | SEI_MASK | STI_MASK | SSI_MASK,
1669};
1670
1671const RegVal VSI_MASK[enums::Num_PrivilegeModeSet] = {
1672 [enums::M] = LOCAL_MASK,
1673 [enums::MU] = LOCAL_MASK,
1674 [enums::MSU] = LOCAL_MASK,
1675 [enums::MHSU] = LOCAL_MASK | VSEI_MASK | VSTI_MASK | VSSI_MASK,
1676};
1677
1678const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
1679const RegVal FRM_MASK = 0x7;
1680
1681const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType] = {
1682 [RV32] = (1ULL << 31),
1683 [RV64] = (1ULL << 63),
1684};
1685
1686
1687// H-extension
1688const RegVal DELEGABLE_INTS_MASK = SSI_MASK | STI_MASK | SEI_MASK |
1689 VSSI_MASK | VSTI_MASK | VSEI_MASK;
1690// H-extension
1691const RegVal HS_INTERRUPTS = SGEI_MASK | VSSI_MASK | VSTI_MASK | VSEI_MASK;
1692
1693const std::unordered_map<int, RegVal>
1694CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1695 [RV32] = {
1696 [enums::M] = {
1697 {CSR_FFLAGS, FFLAGS_MASK},
1698 {CSR_FRM, FRM_MASK},
1699 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1700 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::M]},
1701 {CSR_SIE, SI_MASK[enums::M]},
1702 {CSR_SIP, SI_MASK[enums::M]},
1703 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::M]},
1704 {CSR_MISA, MISA_MASKS[RV32]},
1705 {CSR_MIE, MI_MASK[enums::M]},
1706 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::M]},
1707 {CSR_MIP, MI_MASK[enums::M]},
1708 },
1709 [enums::MU] = {
1710 {CSR_FFLAGS, FFLAGS_MASK},
1711 {CSR_FRM, FRM_MASK},
1712 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1713 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MU]},
1714 {CSR_SIE, SI_MASK[enums::MU]},
1715 {CSR_SIP, SI_MASK[enums::MU]},
1716 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MU]},
1717 {CSR_MISA, MISA_MASKS[RV32]},
1718 {CSR_MIE, MI_MASK[enums::MU]},
1719 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MU]},
1720 {CSR_MIP, MI_MASK[enums::MU]},
1721 },
1722 [enums::MSU] = {
1723 {CSR_FFLAGS, FFLAGS_MASK},
1724 {CSR_FRM, FRM_MASK},
1725 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1726 {CSR_SSTATUS, SSTATUS_MASKS[RV32][enums::MSU]},
1727 {CSR_SIE, SI_MASK[enums::MSU]},
1728 {CSR_SIP, SI_MASK[enums::MSU]},
1729 {CSR_MSTATUS, MSTATUS_MASKS[RV32][enums::MSU]},
1730 {CSR_MISA, MISA_MASKS[RV32]},
1731 {CSR_MIE, MI_MASK[enums::MSU]},
1732 {CSR_MSTATUSH, MSTATUSH_MASKS[enums::MSU]},
1733 {CSR_MIP, MI_MASK[enums::MSU]},
1734 },
1735 },
1736 [RV64] = {
1737 [enums::M] = {
1738 {CSR_FFLAGS, FFLAGS_MASK},
1739 {CSR_FRM, FRM_MASK},
1740 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1741 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::M]},
1742 {CSR_SIE, SI_MASK[enums::M]},
1743 {CSR_SIP, SI_MASK[enums::M]},
1744 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::M]},
1745 {CSR_MISA, MISA_MASKS[RV64]},
1746 {CSR_MIE, MI_MASK[enums::M]},
1747 {CSR_MIP, MI_MASK[enums::M]},
1748 },
1749 [enums::MU] = {
1750 {CSR_FFLAGS, FFLAGS_MASK},
1751 {CSR_FRM, FRM_MASK},
1752 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1753 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MU]},
1754 {CSR_SIE, SI_MASK[enums::MU]},
1755 {CSR_SIP, SI_MASK[enums::MU]},
1756 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MU]},
1757 {CSR_MISA, MISA_MASKS[RV64]},
1758 {CSR_MIE, MI_MASK[enums::MU]},
1759 {CSR_MIP, MI_MASK[enums::MU]},
1760 },
1761 [enums::MSU] = {
1762 {CSR_FFLAGS, FFLAGS_MASK},
1763 {CSR_FRM, FRM_MASK},
1764 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1765 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MSU]},
1766 {CSR_SIE, SI_MASK[enums::MSU]},
1767 {CSR_SIP, SI_MASK[enums::MSU]},
1768 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MSU]},
1769 {CSR_MISA, MISA_MASKS[RV64]},
1770 {CSR_MIE, MI_MASK[enums::MSU]},
1771 {CSR_MIP, MI_MASK[enums::MSU]},
1772 },
1773 [enums::MHSU] = {
1774 {CSR_FFLAGS, FFLAGS_MASK},
1775 {CSR_FRM, FRM_MASK},
1776 {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
1777 {CSR_SSTATUS, SSTATUS_MASKS[RV64][enums::MHSU]},
1778 {CSR_SIE, SI_MASK[enums::MHSU]},
1779 {CSR_SIP, SI_MASK[enums::MHSU]},
1780 {CSR_VSSTATUS, SSTATUS_MASKS[RV64][enums::MHSU]},
1781 {CSR_VSIE, VSI_MASK[enums::MHSU]},
1782 {CSR_VSIP, VSI_MASK[enums::MHSU]},
1783 {CSR_HSTATUS, HSTATUS_MASKS[RV64][enums::MHSU]},
1784 {CSR_HIE, HS_INTERRUPTS},
1785 {CSR_HIP, HS_INTERRUPTS},
1786 {CSR_HVIP, HS_INTERRUPTS & ~SGEI_MASK},
1787 {CSR_MSTATUS, MSTATUS_MASKS[RV64][enums::MHSU]},
1788 {CSR_MISA, MISA_MASKS[RV64]},
1789 {CSR_MIE, MI_MASK[enums::MHSU]},
1790 {CSR_MIP, MI_MASK[enums::MHSU]},
1791 },
1792 },
1793};
1794
1795
1796// Write masks are needed since some visible (readable)
1797// register bits can be read-only.
1798// Without using a write mask, writes are permitted to
1799// bits that should be read-only.
1800
1801// Normal software (e.g. a linux kernel) wouldn't do this,
1802// but our "hardware" shouldn't allow this to any program.
1803
1804// For RV32 we leave the write masks the same as the
1805// "visible bits" masks that are defined above for now
1806
1807// Moreover, instead of writing out a write mask for
1808// every register, we only specify masks for registers
1809// whose write mask differs from the total visible bits.
1810// This saves space and improves readability.
1811// To use the map we lookup a CSR for its write-mask
1812// If the mask is present it is used, otherwise the write mask
1813// that should be used is the "visible bits" mask define above.
1814
1815const std::unordered_map<int, RegVal>
1816CSRWriteMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet] = {
1817 [RV32] = {
1818 [enums::M] = {},
1819 [enums::MU] = {},
1820 [enums::MSU] = {},
1821 },
1822 [RV64] = {
1823 [enums::M] = {
1824 {CSR_MIDELEG, 0ULL},
1825 {CSR_MEDELEG, 0ULL},
1826 {CSR_MSTATUS,
1827 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1828 STATUS_MIE_MASK | STATUS_MPIE_MASK | STATUS_MPP_MASK |
1829 STATUS_TW_MASK | STATUS_TVM_MASK
1830 },
1831 {CSR_MIP, 0ULL},
1832 {CSR_MIE,
1833 MSI_MASK | MTI_MASK | MEI_MASK
1834 },
1835 },
1836 [enums::MU] = {
1837 {CSR_MIDELEG, 0ULL},
1838 {CSR_MEDELEG, 0ULL},
1839 {CSR_MSTATUS,
1840 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1841 STATUS_MIE_MASK | STATUS_MPIE_MASK | STATUS_MPP_MASK |
1842 STATUS_TW_MASK | STATUS_TVM_MASK |
1843 STATUS_MPRV_MASK // added for U
1844 },
1845 {CSR_MIP, 0ULL},
1846 {CSR_MIE,
1847 MSI_MASK | MTI_MASK | MEI_MASK
1848 },
1849 },
1850 [enums::MSU] = {
1851 {CSR_MIDELEG, SSI_MASK | STI_MASK | SEI_MASK},
1852 {CSR_MEDELEG, DELEGABLE_EXCPS},
1853 {CSR_MSTATUS,
1854 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1855 STATUS_MIE_MASK | STATUS_MPIE_MASK | STATUS_MPP_MASK |
1856 STATUS_TW_MASK | STATUS_TVM_MASK |
1857 STATUS_MPRV_MASK | // added for U
1858 STATUS_TSR_MASK | STATUS_SIE_MASK | STATUS_SPIE_MASK |
1859 STATUS_SPP_MASK | STATUS_SUM_MASK | STATUS_MXR_MASK
1860 // added for S
1861 },
1862 {CSR_MIP,
1863 SEI_MASK | SSI_MASK | STI_MASK // added for S
1864 },
1865 {CSR_MIE,
1866 MSI_MASK | MTI_MASK | MEI_MASK |
1867 SSI_MASK | STI_MASK | SEI_MASK // added for S
1868 },
1869 {CSR_SSTATUS,
1870 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1871 STATUS_SIE_MASK | STATUS_SPIE_MASK | // no TSR here!
1872 STATUS_SPP_MASK | STATUS_SUM_MASK | STATUS_MXR_MASK
1873 // added for S
1874 },
1875 {CSR_SIP,
1876 SSI_MASK // added for S
1877 },
1878 {CSR_SIE,
1879 SSI_MASK | STI_MASK | SEI_MASK // added for S
1880 },
1881 },
1882 [enums::MHSU] = {
1883 {CSR_MIDELEG, SSI_MASK | STI_MASK | SEI_MASK},
1884 {CSR_MEDELEG, DELEGABLE_EXCPS_WITH_RVH},
1885 {CSR_MSTATUS,
1886 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1887 STATUS_MIE_MASK | STATUS_MPIE_MASK | STATUS_MPP_MASK |
1888 STATUS_TW_MASK | STATUS_TVM_MASK |
1889 STATUS_MPRV_MASK | // added for U
1890 STATUS_TSR_MASK | STATUS_SIE_MASK | STATUS_SPIE_MASK |
1891 STATUS_SPP_MASK | STATUS_SUM_MASK | STATUS_MXR_MASK |
1892 // added for S
1893 STATUS_GVA_MASK | STATUS_MPV_MASK // added for H
1894 },
1895 {CSR_MIP,
1896 SEI_MASK | SSI_MASK | STI_MASK | // added for S
1897 VSSI_MASK // added for H
1898 },
1899 {CSR_MIE,
1900 MSI_MASK | MTI_MASK | MEI_MASK |
1901 SSI_MASK | STI_MASK | SEI_MASK | // added for S
1902 HS_INTERRUPTS // added for H (multiple bits)
1903 },
1904 {CSR_SSTATUS,
1905 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1906 STATUS_SIE_MASK | STATUS_SPIE_MASK | // no TSR here!
1907 STATUS_SPP_MASK | STATUS_SUM_MASK | STATUS_MXR_MASK
1908 // added for S
1909 },
1910 {CSR_SIP,
1911 SSI_MASK // added for S
1912 },
1913 {CSR_SIE,
1914 SSI_MASK | STI_MASK | SEI_MASK // added for S
1915 },
1916 {CSR_HSTATUS,
1917 HSTATUS_VTSR_MASK | HSTATUS_VTW_MASK |
1918 HSTATUS_VTVM_MASK | HSTATUS_HU_MASK |
1919 HSTATUS_SPVP_MASK | HSTATUS_SPV_MASK |
1920 HSTATUS_GVA_MASK // added for H
1921 },
1922 {CSR_HIP,
1923 VSSI_MASK // added for H
1924 },
1925 {CSR_HIE,
1926 HS_INTERRUPTS // added for H
1927 },
1928 {CSR_HVIP,
1929 HS_INTERRUPTS & ~SGEI_MASK // added for H
1930 },
1931 {CSR_VSSTATUS,
1932 STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
1933 STATUS_SIE_MASK | STATUS_SPIE_MASK | // no TSR here!
1934 STATUS_SPP_MASK | STATUS_SUM_MASK | STATUS_MXR_MASK
1935 // added for H
1936 },
1937 {CSR_VSIP,
1938 VSSI_MASK // added for H
1939 },
1940 {CSR_VSIE,
1941 HS_INTERRUPTS & ~SGEI_MASK // added for H
1942 },
1943
1944 },
1945 },
1946};
1947
1948} // namespace RiscvISA
1949} // namespace gem5
1950
1951#endif // __ARCH_RISCV_REGS_MISC_HH__
types.hh
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
fault_codes.hh
BitUnion64
#define BitUnion64(name)
Use this to define conveniently sized values overlayed with bitfields.
Definition bitunion.hh:494
EndBitUnion
#define EndBitUnion(name)
This closes off the class and union started by the above macro.
Definition bitunion.hh:428
gem5::ArmISA::miscRegClass
constexpr RegClass miscRegClass
Definition misc.hh:2992
gem5::RiscvISA::STATUS_TSR_MASK
const RegVal STATUS_TSR_MASK
Definition misc.hh:1505
gem5::RiscvISA::HSTATUS_MASKS
const RegVal HSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1589
gem5::RiscvISA::nmie
Bitfield< 3 > nmie
Definition misc.hh:1384
gem5::RiscvISA::MSTATUSH_MASKS
const RegVal MSTATUSH_MASKS[enums::Num_PrivilegeModeSet]
Definition misc.hh:1582
gem5::RiscvISA::rvd
Bitfield< 3 > rvd
Definition misc.hh:1412
gem5::RiscvISA::SI_MASK
const RegVal SI_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1658
gem5::RiscvISA::msi
Bitfield< 3 > msi
Definition misc.hh:1433
gem5::RiscvISA::HSTATUS_SPV_MASK
const RegVal HSTATUS_SPV_MASK
Definition misc.hh:1530
gem5::RiscvISA::mpp
Bitfield< 12, 11 > mpp
Definition misc.hh:1350
gem5::RiscvISA::sbe
Bitfield< 36 > sbe
Definition misc.hh:1338
gem5::RiscvISA::tw
Bitfield< 21 > tw
Definition misc.hh:1343
gem5::RiscvISA::mpv
Bitfield< 39 > mpv
Definition misc.hh:1335
gem5::RiscvISA::spv
Bitfield< 7 > spv
Definition misc.hh:1370
gem5::RiscvISA::isaExtsFlags
constexpr uint64_t isaExtsFlags()
Definition misc.hh:600
gem5::RiscvISA::CSR_MHPMEVENT19
@ CSR_MHPMEVENT19
Definition misc.hh:508
gem5::RiscvISA::CSR_HPMCOUNTER18
@ CSR_HPMCOUNTER18
Definition misc.hh:327
gem5::RiscvISA::CSR_HPMCOUNTER05H
@ CSR_HPMCOUNTER05H
Definition misc.hh:348
gem5::RiscvISA::CSR_HPMCOUNTER11
@ CSR_HPMCOUNTER11
Definition misc.hh:320
gem5::RiscvISA::CSR_HPMCOUNTER03H
@ CSR_HPMCOUNTER03H
Definition misc.hh:346
gem5::RiscvISA::CSR_HPMCOUNTER05
@ CSR_HPMCOUNTER05
Definition misc.hh:314
gem5::RiscvISA::CSR_MHPMCOUNTER25H
@ CSR_MHPMCOUNTER25H
Definition misc.hh:483
gem5::RiscvISA::CSR_MHPMEVENT27
@ CSR_MHPMEVENT27
Definition misc.hh:516
gem5::RiscvISA::CSR_MHPMCOUNTER07H
@ CSR_MHPMCOUNTER07H
Definition misc.hh:465
gem5::RiscvISA::CSR_HPMCOUNTER23
@ CSR_HPMCOUNTER23
Definition misc.hh:332
gem5::RiscvISA::CSR_MHPMCOUNTER03H
@ CSR_MHPMCOUNTER03H
Definition misc.hh:461
gem5::RiscvISA::CSR_MHPMEVENT17
@ CSR_MHPMEVENT17
Definition misc.hh:506
gem5::RiscvISA::CSR_HPMCOUNTER20H
@ CSR_HPMCOUNTER20H
Definition misc.hh:363
gem5::RiscvISA::CSR_HPMCOUNTER17
@ CSR_HPMCOUNTER17
Definition misc.hh:326
gem5::RiscvISA::CSR_MHPMEVENT21
@ CSR_MHPMEVENT21
Definition misc.hh:510
gem5::RiscvISA::CSR_MHPMCOUNTER07
@ CSR_MHPMCOUNTER07
Definition misc.hh:432
gem5::RiscvISA::CSR_HPMCOUNTER16
@ CSR_HPMCOUNTER16
Definition misc.hh:325
gem5::RiscvISA::CSR_HPMCOUNTER15
@ CSR_HPMCOUNTER15
Definition misc.hh:324
gem5::RiscvISA::CSR_HPMCOUNTER06H
@ CSR_HPMCOUNTER06H
Definition misc.hh:349
gem5::RiscvISA::CSR_HPMCOUNTER07
@ CSR_HPMCOUNTER07
Definition misc.hh:316
gem5::RiscvISA::CSR_HPMCOUNTER27
@ CSR_HPMCOUNTER27
Definition misc.hh:336
gem5::RiscvISA::CSR_HPMCOUNTER08
@ CSR_HPMCOUNTER08
Definition misc.hh:317
gem5::RiscvISA::CSR_MHPMCOUNTER21H
@ CSR_MHPMCOUNTER21H
Definition misc.hh:479
gem5::RiscvISA::CSR_HPMCOUNTER21
@ CSR_HPMCOUNTER21
Definition misc.hh:330
gem5::RiscvISA::CSR_HPMCOUNTER24
@ CSR_HPMCOUNTER24
Definition misc.hh:333
gem5::RiscvISA::CSR_MHPMCOUNTER29H
@ CSR_MHPMCOUNTER29H
Definition misc.hh:487
gem5::RiscvISA::CSR_MHPMCOUNTER12H
@ CSR_MHPMCOUNTER12H
Definition misc.hh:470
gem5::RiscvISA::CSR_MHPMEVENT22
@ CSR_MHPMEVENT22
Definition misc.hh:511
gem5::RiscvISA::CSR_MHPMCOUNTER16
@ CSR_MHPMCOUNTER16
Definition misc.hh:441
gem5::RiscvISA::CSR_MHPMEVENT06
@ CSR_MHPMEVENT06
Definition misc.hh:495
gem5::RiscvISA::CSR_MHPMCOUNTER23
@ CSR_MHPMCOUNTER23
Definition misc.hh:448
gem5::RiscvISA::CSR_MHPMEVENT05
@ CSR_MHPMEVENT05
Definition misc.hh:494
gem5::RiscvISA::CSR_MHPMCOUNTER22
@ CSR_MHPMCOUNTER22
Definition misc.hh:447
gem5::RiscvISA::CSR_MHPMCOUNTER10H
@ CSR_MHPMCOUNTER10H
Definition misc.hh:468
gem5::RiscvISA::CSR_MHPMEVENT13
@ CSR_MHPMEVENT13
Definition misc.hh:502
gem5::RiscvISA::CSR_HPMCOUNTER29
@ CSR_HPMCOUNTER29
Definition misc.hh:338
gem5::RiscvISA::CSR_MHPMCOUNTER06
@ CSR_MHPMCOUNTER06
Definition misc.hh:431
gem5::RiscvISA::CSR_HPMCOUNTER04
@ CSR_HPMCOUNTER04
Definition misc.hh:313
gem5::RiscvISA::CSR_MHPMCOUNTER05H
@ CSR_MHPMCOUNTER05H
Definition misc.hh:463
gem5::RiscvISA::CSR_HPMCOUNTER25
@ CSR_HPMCOUNTER25
Definition misc.hh:334
gem5::RiscvISA::CSR_MHPMEVENT20
@ CSR_MHPMEVENT20
Definition misc.hh:509
gem5::RiscvISA::CSR_HPMCOUNTER10H
@ CSR_HPMCOUNTER10H
Definition misc.hh:353
gem5::RiscvISA::CSR_HPMCOUNTER26
@ CSR_HPMCOUNTER26
Definition misc.hh:335
gem5::RiscvISA::CSR_HPMCOUNTER11H
@ CSR_HPMCOUNTER11H
Definition misc.hh:354
gem5::RiscvISA::CSR_MHPMEVENT31
@ CSR_MHPMEVENT31
Definition misc.hh:520
gem5::RiscvISA::CSR_HPMCOUNTER28
@ CSR_HPMCOUNTER28
Definition misc.hh:337
gem5::RiscvISA::CSR_MHPMCOUNTER29
@ CSR_MHPMCOUNTER29
Definition misc.hh:454
gem5::RiscvISA::CSR_MHPMCOUNTER15
@ CSR_MHPMCOUNTER15
Definition misc.hh:440
gem5::RiscvISA::CSR_MHPMEVENT14
@ CSR_MHPMEVENT14
Definition misc.hh:503
gem5::RiscvISA::CSR_HPMCOUNTER10
@ CSR_HPMCOUNTER10
Definition misc.hh:319
gem5::RiscvISA::CSR_MHPMCOUNTER28
@ CSR_MHPMCOUNTER28
Definition misc.hh:453
gem5::RiscvISA::CSR_MHPMCOUNTER09H
@ CSR_MHPMCOUNTER09H
Definition misc.hh:467
gem5::RiscvISA::CSR_HPMCOUNTER19H
@ CSR_HPMCOUNTER19H
Definition misc.hh:362
gem5::RiscvISA::CSR_MHPMCOUNTER13H
@ CSR_MHPMCOUNTER13H
Definition misc.hh:471
gem5::RiscvISA::CSR_MHPMCOUNTER27
@ CSR_MHPMCOUNTER27
Definition misc.hh:452
gem5::RiscvISA::CSR_MHPMCOUNTER16H
@ CSR_MHPMCOUNTER16H
Definition misc.hh:474
gem5::RiscvISA::CSR_MHPMCOUNTER03
@ CSR_MHPMCOUNTER03
Definition misc.hh:428
gem5::RiscvISA::CSR_HPMCOUNTER04H
@ CSR_HPMCOUNTER04H
Definition misc.hh:347
gem5::RiscvISA::CSR_MHPMEVENT07
@ CSR_MHPMEVENT07
Definition misc.hh:496
gem5::RiscvISA::CSR_MHPMCOUNTER11
@ CSR_MHPMCOUNTER11
Definition misc.hh:436
gem5::RiscvISA::CSR_MHPMCOUNTER26H
@ CSR_MHPMCOUNTER26H
Definition misc.hh:484
gem5::RiscvISA::CSR_HPMCOUNTER07H
@ CSR_HPMCOUNTER07H
Definition misc.hh:350
gem5::RiscvISA::CSR_MHPMCOUNTER17H
@ CSR_MHPMCOUNTER17H
Definition misc.hh:475
gem5::RiscvISA::CSR_MHPMEVENT03
@ CSR_MHPMEVENT03
Definition misc.hh:492
gem5::RiscvISA::CSR_HPMCOUNTER30
@ CSR_HPMCOUNTER30
Definition misc.hh:339
gem5::RiscvISA::CSR_HPMCOUNTER28H
@ CSR_HPMCOUNTER28H
Definition misc.hh:371
gem5::RiscvISA::CSR_HPMCOUNTER25H
@ CSR_HPMCOUNTER25H
Definition misc.hh:368
gem5::RiscvISA::CSR_HPMCOUNTER17H
@ CSR_HPMCOUNTER17H
Definition misc.hh:360
gem5::RiscvISA::CSR_HPMCOUNTER29H
@ CSR_HPMCOUNTER29H
Definition misc.hh:372
gem5::RiscvISA::CSR_MHPMEVENT08
@ CSR_MHPMEVENT08
Definition misc.hh:497
gem5::RiscvISA::CSR_MHPMEVENT25
@ CSR_MHPMEVENT25
Definition misc.hh:514
gem5::RiscvISA::CSR_MHPMCOUNTER22H
@ CSR_MHPMCOUNTER22H
Definition misc.hh:480
gem5::RiscvISA::CSR_HPMCOUNTER31H
@ CSR_HPMCOUNTER31H
Definition misc.hh:374
gem5::RiscvISA::CSR_MHPMCOUNTER19
@ CSR_MHPMCOUNTER19
Definition misc.hh:444
gem5::RiscvISA::CSR_MHPMCOUNTER05
@ CSR_MHPMCOUNTER05
Definition misc.hh:430
gem5::RiscvISA::CSR_MHPMCOUNTER15H
@ CSR_MHPMCOUNTER15H
Definition misc.hh:473
gem5::RiscvISA::CSR_MHPMEVENT30
@ CSR_MHPMEVENT30
Definition misc.hh:519
gem5::RiscvISA::CSR_MHPMCOUNTER10
@ CSR_MHPMCOUNTER10
Definition misc.hh:435
gem5::RiscvISA::CSR_HPMCOUNTER16H
@ CSR_HPMCOUNTER16H
Definition misc.hh:359
gem5::RiscvISA::CSR_HPMCOUNTER30H
@ CSR_HPMCOUNTER30H
Definition misc.hh:373
gem5::RiscvISA::CSR_HPMCOUNTER22
@ CSR_HPMCOUNTER22
Definition misc.hh:331
gem5::RiscvISA::CSR_MHPMEVENT16
@ CSR_MHPMEVENT16
Definition misc.hh:505
gem5::RiscvISA::CSR_MHPMCOUNTER24H
@ CSR_MHPMCOUNTER24H
Definition misc.hh:482
gem5::RiscvISA::CSR_MHPMEVENT12
@ CSR_MHPMEVENT12
Definition misc.hh:501
gem5::RiscvISA::CSR_HPMCOUNTER23H
@ CSR_HPMCOUNTER23H
Definition misc.hh:366
gem5::RiscvISA::CSR_HPMCOUNTER20
@ CSR_HPMCOUNTER20
Definition misc.hh:329
gem5::RiscvISA::CSR_HPMCOUNTER14H
@ CSR_HPMCOUNTER14H
Definition misc.hh:357
gem5::RiscvISA::CSR_HPMCOUNTER08H
@ CSR_HPMCOUNTER08H
Definition misc.hh:351
gem5::RiscvISA::CSR_MHPMEVENT09
@ CSR_MHPMEVENT09
Definition misc.hh:498
gem5::RiscvISA::CSR_HPMCOUNTER26H
@ CSR_HPMCOUNTER26H
Definition misc.hh:369
gem5::RiscvISA::CSR_MHPMEVENT04
@ CSR_MHPMEVENT04
Definition misc.hh:493
gem5::RiscvISA::CSR_MHPMCOUNTER18H
@ CSR_MHPMCOUNTER18H
Definition misc.hh:476
gem5::RiscvISA::CSR_MHPMEVENT29
@ CSR_MHPMEVENT29
Definition misc.hh:518
gem5::RiscvISA::CSR_MHPMCOUNTER06H
@ CSR_MHPMCOUNTER06H
Definition misc.hh:464
gem5::RiscvISA::CSR_HPMCOUNTER27H
@ CSR_HPMCOUNTER27H
Definition misc.hh:370
gem5::RiscvISA::CSR_HPMCOUNTER18H
@ CSR_HPMCOUNTER18H
Definition misc.hh:361
gem5::RiscvISA::CSR_MHPMCOUNTER25
@ CSR_MHPMCOUNTER25
Definition misc.hh:450
gem5::RiscvISA::CSR_MHPMCOUNTER23H
@ CSR_MHPMCOUNTER23H
Definition misc.hh:481
gem5::RiscvISA::CSR_MHPMEVENT15
@ CSR_MHPMEVENT15
Definition misc.hh:504
gem5::RiscvISA::CSR_MHPMEVENT11
@ CSR_MHPMEVENT11
Definition misc.hh:500
gem5::RiscvISA::CSR_HPMCOUNTER09H
@ CSR_HPMCOUNTER09H
Definition misc.hh:352
gem5::RiscvISA::CSR_MHPMCOUNTER13
@ CSR_MHPMCOUNTER13
Definition misc.hh:438
gem5::RiscvISA::CSR_HPMCOUNTER15H
@ CSR_HPMCOUNTER15H
Definition misc.hh:358
gem5::RiscvISA::CSR_MHPMEVENT10
@ CSR_MHPMEVENT10
Definition misc.hh:499
gem5::RiscvISA::CSR_MHPMCOUNTER11H
@ CSR_MHPMCOUNTER11H
Definition misc.hh:469
gem5::RiscvISA::CSR_MHPMEVENT18
@ CSR_MHPMEVENT18
Definition misc.hh:507
gem5::RiscvISA::CSR_HPMCOUNTER06
@ CSR_HPMCOUNTER06
Definition misc.hh:315
gem5::RiscvISA::CSR_MHPMEVENT23
@ CSR_MHPMEVENT23
Definition misc.hh:512
gem5::RiscvISA::CSR_MHPMEVENT26
@ CSR_MHPMEVENT26
Definition misc.hh:515
gem5::RiscvISA::CSR_MHPMCOUNTER09
@ CSR_MHPMCOUNTER09
Definition misc.hh:434
gem5::RiscvISA::CSR_MHPMCOUNTER24
@ CSR_MHPMCOUNTER24
Definition misc.hh:449
gem5::RiscvISA::CSR_MHPMCOUNTER26
@ CSR_MHPMCOUNTER26
Definition misc.hh:451
gem5::RiscvISA::CSR_HPMCOUNTER21H
@ CSR_HPMCOUNTER21H
Definition misc.hh:364
gem5::RiscvISA::CSR_MHPMCOUNTER04H
@ CSR_MHPMCOUNTER04H
Definition misc.hh:462
gem5::RiscvISA::CSR_MHPMCOUNTER30H
@ CSR_MHPMCOUNTER30H
Definition misc.hh:488
gem5::RiscvISA::CSR_HPMCOUNTER22H
@ CSR_HPMCOUNTER22H
Definition misc.hh:365
gem5::RiscvISA::CSR_MHPMCOUNTER17
@ CSR_MHPMCOUNTER17
Definition misc.hh:442
gem5::RiscvISA::CSR_MHPMCOUNTER14H
@ CSR_MHPMCOUNTER14H
Definition misc.hh:472
gem5::RiscvISA::CSR_MHPMCOUNTER31H
@ CSR_MHPMCOUNTER31H
Definition misc.hh:489
gem5::RiscvISA::CSR_HPMCOUNTER13
@ CSR_HPMCOUNTER13
Definition misc.hh:322
gem5::RiscvISA::CSR_MHPMCOUNTER20
@ CSR_MHPMCOUNTER20
Definition misc.hh:445
gem5::RiscvISA::CSR_MHPMCOUNTER20H
@ CSR_MHPMCOUNTER20H
Definition misc.hh:478
gem5::RiscvISA::CSR_HPMCOUNTER12
@ CSR_HPMCOUNTER12
Definition misc.hh:321
gem5::RiscvISA::CSR_MHPMCOUNTER21
@ CSR_MHPMCOUNTER21
Definition misc.hh:446
gem5::RiscvISA::CSR_MHPMEVENT28
@ CSR_MHPMEVENT28
Definition misc.hh:517
gem5::RiscvISA::CSR_HPMCOUNTER14
@ CSR_HPMCOUNTER14
Definition misc.hh:323
gem5::RiscvISA::CSR_MHPMCOUNTER31
@ CSR_MHPMCOUNTER31
Definition misc.hh:456
gem5::RiscvISA::CSR_HPMCOUNTER31
@ CSR_HPMCOUNTER31
Definition misc.hh:340
gem5::RiscvISA::CSR_HPMCOUNTER13H
@ CSR_HPMCOUNTER13H
Definition misc.hh:356
gem5::RiscvISA::CSR_MHPMCOUNTER28H
@ CSR_MHPMCOUNTER28H
Definition misc.hh:486
gem5::RiscvISA::CSR_MHPMCOUNTER14
@ CSR_MHPMCOUNTER14
Definition misc.hh:439
gem5::RiscvISA::CSR_MHPMCOUNTER19H
@ CSR_MHPMCOUNTER19H
Definition misc.hh:477
gem5::RiscvISA::CSR_HPMCOUNTER12H
@ CSR_HPMCOUNTER12H
Definition misc.hh:355
gem5::RiscvISA::CSR_HPMCOUNTER09
@ CSR_HPMCOUNTER09
Definition misc.hh:318
gem5::RiscvISA::CSR_HPMCOUNTER19
@ CSR_HPMCOUNTER19
Definition misc.hh:328
gem5::RiscvISA::CSR_HPMCOUNTER03
@ CSR_HPMCOUNTER03
Definition misc.hh:312
gem5::RiscvISA::CSR_MHPMCOUNTER18
@ CSR_MHPMCOUNTER18
Definition misc.hh:443
gem5::RiscvISA::CSR_MHPMCOUNTER27H
@ CSR_MHPMCOUNTER27H
Definition misc.hh:485
gem5::RiscvISA::CSR_MHPMCOUNTER08H
@ CSR_MHPMCOUNTER08H
Definition misc.hh:466
gem5::RiscvISA::CSR_MHPMCOUNTER12
@ CSR_MHPMCOUNTER12
Definition misc.hh:437
gem5::RiscvISA::CSR_MHPMCOUNTER30
@ CSR_MHPMCOUNTER30
Definition misc.hh:455
gem5::RiscvISA::CSR_MHPMCOUNTER04
@ CSR_MHPMCOUNTER04
Definition misc.hh:429
gem5::RiscvISA::CSR_MHPMEVENT24
@ CSR_MHPMEVENT24
Definition misc.hh:513
gem5::RiscvISA::CSR_HPMCOUNTER24H
@ CSR_HPMCOUNTER24H
Definition misc.hh:367
gem5::RiscvISA::CSR_MHPMCOUNTER08
@ CSR_MHPMCOUNTER08
Definition misc.hh:433
gem5::RiscvISA::ssi
Bitfield< 1 > ssi
Definition misc.hh:1435
gem5::RiscvISA::HSTATUS_VSXL_MASK
const RegVal HSTATUS_VSXL_MASK
Definition misc.hh:1523
gem5::RiscvISA::sxl
Bitfield< 35, 34 > sxl
Definition misc.hh:1339
gem5::RiscvISA::pmm
Bitfield< 33, 32 > pmm
Definition misc.hh:1443
gem5::RiscvISA::RV32
constexpr enums::RiscvType RV32
Definition pcstate.hh:56
gem5::RiscvISA::FRM_MASK
const RegVal FRM_MASK
Definition misc.hh:1679
gem5::RiscvISA::VSEI_MASK
const RegVal VSEI_MASK
Definition misc.hh:1634
gem5::RiscvISA::rvi
Bitfield< 8 > rvi
Definition misc.hh:1407
gem5::RiscvISA::rvv
Bitfield< 21 > rvv
Definition misc.hh:1396
gem5::RiscvISA::STATUS_MBE_MASK
const RegVal STATUS_MBE_MASK[enums::Num_RiscvType]
Definition misc.hh:1492
gem5::RiscvISA::CAUSE_INTERRUPT_MASKS
const RegVal CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType]
Definition misc.hh:1681
gem5::RiscvISA::VSI_MASK
const RegVal VSI_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1671
gem5::RiscvISA::rvg
Bitfield< 6 > rvg
Definition misc.hh:1409
gem5::RiscvISA::vsti
Bitfield< 6 > vsti
Definition misc.hh:1431
gem5::RiscvISA::rvu
Bitfield< 20 > rvu
Definition misc.hh:1397
gem5::RiscvISA::sum
Bitfield< 18 > sum
Definition misc.hh:1346
gem5::RiscvISA::ube
Bitfield< 6 > ube
Definition misc.hh:1354
gem5::RiscvISA::vsei
Bitfield< 10 > vsei
Definition misc.hh:1428
gem5::RiscvISA::spp
Bitfield< 8 > spp
Definition misc.hh:1352
gem5::RiscvISA::mei
Bitfield< 11 > mei
Definition misc.hh:1427
gem5::RiscvISA::STATUS_SBE_MASK
const RegVal STATUS_SBE_MASK[enums::Num_RiscvType]
Definition misc.hh:1496
gem5::RiscvISA::rvh
Bitfield< 7 > rvh
Definition misc.hh:1408
gem5::RiscvISA::SGEI_MASK
const RegVal SGEI_MASK
Definition misc.hh:1632
gem5::RiscvISA::vtw
Bitfield< 21 > vtw
Definition misc.hh:1365
gem5::RiscvISA::fiom
Bitfield< 0 > fiom
Definition misc.hh:1449
gem5::RiscvISA::MEI_MASK
const RegVal MEI_MASK
Definition misc.hh:1633
gem5::RiscvISA::DELEGABLE_INTS_MASK
const RegVal DELEGABLE_INTS_MASK
Definition misc.hh:1688
gem5::RiscvISA::STATUS_UBE_MASK
const RegVal STATUS_UBE_MASK
Definition misc.hh:1517
gem5::RiscvISA::mprv
Bitfield< 17 > mprv
Definition misc.hh:1347
gem5::RiscvISA::SEI_MASK
const RegVal SEI_MASK
Definition misc.hh:1635
gem5::RiscvISA::rvx
Bitfield< 23 > rvx
Definition misc.hh:1395
gem5::RiscvISA::HSTATUS_SPVP_MASK
const RegVal HSTATUS_SPVP_MASK
Definition misc.hh:1529
gem5::RiscvISA::mbe
Bitfield< 37 > mbe
Definition misc.hh:1337
gem5::RiscvISA::SSI_MASK
const RegVal SSI_MASK
Definition misc.hh:1641
gem5::RiscvISA::vgein
Bitfield< 17, 12 > vgein
Definition misc.hh:1367
gem5::RiscvISA::UXL_OFFSET
const off_t UXL_OFFSET
Definition misc.hh:1471
gem5::RiscvISA::sti
Bitfield< 5 > sti
Definition misc.hh:1432
gem5::RiscvISA::sie
Bitfield< 1 > sie
Definition misc.hh:1357
gem5::RiscvISA::wpri_3
Bitfield< 3, 1 > wpri_3
Definition misc.hh:1448
gem5::RiscvISA::rvs
Bitfield< 18 > rvs
Definition misc.hh:1399
gem5::RiscvISA::SXL_OFFSET
const off_t SXL_OFFSET
Definition misc.hh:1469
gem5::RiscvISA::STATUS_MIE_MASK
const RegVal STATUS_MIE_MASK
Definition misc.hh:1519
gem5::RiscvISA::HSTATUS_VTSR_MASK
const RegVal HSTATUS_VTSR_MASK
Definition misc.hh:1524
gem5::RiscvISA::HS_INTERRUPTS
const RegVal HS_INTERRUPTS
Definition misc.hh:1691
gem5::RiscvISA::rv32_sd
Bitfield< 31 > rv32_sd
Definition misc.hh:1341
gem5::RiscvISA::STATUS_SIE_MASK
const RegVal STATUS_SIE_MASK
Definition misc.hh:1520
gem5::RiscvISA::FS_OFFSET
const off_t FS_OFFSET
Definition misc.hh:1472
gem5::RiscvISA::STATUS_TW_MASK
const RegVal STATUS_TW_MASK
Definition misc.hh:1506
gem5::RiscvISA::STATUS_MPIE_MASK
const RegVal STATUS_MPIE_MASK
Definition misc.hh:1516
gem5::RiscvISA::fs
Bitfield< 14, 13 > fs
Definition misc.hh:1349
gem5::RiscvISA::rvm
Bitfield< 12 > rvm
Definition misc.hh:1403
gem5::RiscvISA::SSTATUS_MASKS
const RegVal SSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1608
gem5::RiscvISA::STATUS_VS_MASK
const RegVal STATUS_VS_MASK
Definition misc.hh:1514
gem5::RiscvISA::VS_OFFSET
const off_t VS_OFFSET
Definition misc.hh:1473
gem5::RiscvISA::gva
Bitfield< 38 > gva
Definition misc.hh:1336
gem5::RiscvISA::MTI_MASK
const RegVal MTI_MASK
Definition misc.hh:1636
gem5::RiscvISA::MBE_OFFSET
const off_t MBE_OFFSET[enums::Num_RiscvType]
Definition misc.hh:1461
gem5::RiscvISA::HSTATUS_VTVM_MASK
const RegVal HSTATUS_VTVM_MASK
Definition misc.hh:1526
gem5::RiscvISA::tvm
Bitfield< 20 > tvm
Definition misc.hh:1344
gem5::RiscvISA::STATUS_XS_MASK
const RegVal STATUS_XS_MASK
Definition misc.hh:1511
gem5::RiscvISA::STATUS_GVA_MASK
const RegVal STATUS_GVA_MASK
Definition misc.hh:1502
gem5::RiscvISA::STATUS_SXL_MASK
const RegVal STATUS_SXL_MASK
Definition misc.hh:1503
gem5::RiscvISA::FFLAGS_MASK
const RegVal FFLAGS_MASK
Definition misc.hh:1678
gem5::RiscvISA::mti
Bitfield< 7 > mti
Definition misc.hh:1430
gem5::RiscvISA::EndBitUnion
EndBitUnion(SATP) enum AddrXlateMode
Definition pagetable.hh:49
gem5::RiscvISA::rva
Bitfield< 0 > rva
Definition misc.hh:1415
gem5::RiscvISA::rvq
Bitfield< 16 > rvq
Definition misc.hh:1400
gem5::RiscvISA::HSTATUS_HU_MASK
const RegVal HSTATUS_HU_MASK
Definition misc.hh:1528
gem5::RiscvISA::STATUS_MPRV_MASK
const RegVal STATUS_MPRV_MASK
Definition misc.hh:1510
gem5::RiscvISA::DELEGABLE_EXCPS
const RegVal DELEGABLE_EXCPS
Definition fault_codes.hh:154
gem5::RiscvISA::HSTATUS_VGEIN_MASK
const RegVal HSTATUS_VGEIN_MASK
Definition misc.hh:1527
gem5::RiscvISA::uxl
Bitfield< 33, 32 > uxl
Definition misc.hh:1340
gem5::RiscvISA::rvp
Bitfield< 15 > rvp
Definition misc.hh:1401
gem5::RiscvISA::VSXL_OFFSET
const off_t VSXL_OFFSET
Definition misc.hh:1470
gem5::RiscvISA::MSI_MASK
const RegVal MSI_MASK
Definition misc.hh:1639
gem5::RiscvISA::spie
Bitfield< 5 > spie
Definition misc.hh:1355
gem5::RiscvISA::vtvm
Bitfield< 20 > vtvm
Definition misc.hh:1366
gem5::RiscvISA::HSTATUS_VSBE_MASK
const RegVal HSTATUS_VSBE_MASK
Definition misc.hh:1532
gem5::RiscvISA::vssi
Bitfield< 2 > vssi
Definition misc.hh:1434
gem5::RiscvISA::vtsr
Bitfield< 22 > vtsr
Definition misc.hh:1364
gem5::RiscvISA::mie
Bitfield< 3 > mie
Definition misc.hh:1356
gem5::RiscvISA::mpie
Bitfield< 7 > mpie
Definition misc.hh:1353
gem5::RiscvISA::mnv
Bitfield< 7 > mnv
Definition misc.hh:1383
gem5::RiscvISA::STATUS_UXL_MASK
const RegVal STATUS_UXL_MASK
Definition misc.hh:1504
gem5::RiscvISA::STATUS_MXR_MASK
const RegVal STATUS_MXR_MASK
Definition misc.hh:1508
gem5::RiscvISA::CSRData
const std::unordered_map< int, CSRMetadata > CSRData
Definition misc.hh:604
gem5::RiscvISA::STATUS_MPV_MASK
const RegVal STATUS_MPV_MASK
Definition misc.hh:1501
gem5::RiscvISA::tsr
Bitfield< 22 > tsr
Definition misc.hh:1342
gem5::RiscvISA::CSRMasks
const std::unordered_map< int, RegVal > CSRMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1694
gem5::RiscvISA::LOCAL_MASK
const RegVal LOCAL_MASK
Definition misc.hh:1631
gem5::RiscvISA::VSTI_MASK
const RegVal VSTI_MASK
Definition misc.hh:1637
gem5::RiscvISA::cbcfe
Bitfield< 6 > cbcfe
Definition misc.hh:1446
gem5::RiscvISA::vsbe
Bitfield< 5 > vsbe
Definition misc.hh:1372
gem5::RiscvISA::STATUS_FS_MASK
const RegVal STATUS_FS_MASK
Definition misc.hh:1512
gem5::RiscvISA::STATUS_SPP_MASK
const RegVal STATUS_SPP_MASK
Definition misc.hh:1515
gem5::RiscvISA::VSSI_MASK
const RegVal VSSI_MASK
Definition misc.hh:1640
gem5::RiscvISA::HSTATUS_VTW_MASK
const RegVal HSTATUS_VTW_MASK
Definition misc.hh:1525
gem5::RiscvISA::ISA_EXT_MASK
const RegVal ISA_EXT_MASK
Definition misc.hh:1480
gem5::RiscvISA::cbie
Bitfield< 5, 4 > cbie
Definition misc.hh:1447
gem5::RiscvISA::sgei
Bitfield< 12 > sgei
Definition misc.hh:1426
gem5::RiscvISA::STATUS_SD_MASKS
const RegVal STATUS_SD_MASKS[enums::Num_RiscvType]
Definition misc.hh:1488
gem5::RiscvISA::CSRWriteMasks
const std::unordered_map< int, RegVal > CSRWriteMasks[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1816
gem5::RiscvISA::STATUS_SPIE_MASK
const RegVal STATUS_SPIE_MASK
Definition misc.hh:1518
gem5::RiscvISA::STATUS_MPP_MASK
const RegVal STATUS_MPP_MASK
Definition misc.hh:1513
gem5::RiscvISA::rvn
Bitfield< 13 > rvn
Definition misc.hh:1402
gem5::RiscvISA::rve
Bitfield< 4 > rve
Definition misc.hh:1411
gem5::RiscvISA::RV64
constexpr enums::RiscvType RV64
Definition pcstate.hh:57
gem5::RiscvISA::ISA_EXT_C_MASK
const RegVal ISA_EXT_C_MASK
Definition misc.hh:1481
gem5::RiscvISA::rvb
Bitfield< 1 > rvb
Definition misc.hh:1414
gem5::RiscvISA::MISCREG_PMPADDR11
@ MISCREG_PMPADDR11
Definition misc.hh:173
gem5::RiscvISA::MISCREG_HPMCOUNTER16H
@ MISCREG_HPMCOUNTER16H
Definition misc.hh:277
gem5::RiscvISA::MISCREG_HSTATUS
@ MISCREG_HSTATUS
Definition misc.hh:213
gem5::RiscvISA::MISCREG_HPMCOUNTER09
@ MISCREG_HPMCOUNTER09
Definition misc.hh:90
gem5::RiscvISA::MISCREG_HPMEVENT31
@ MISCREG_HPMEVENT31
Definition misc.hh:141
gem5::RiscvISA::MISCREG_IMPID
@ MISCREG_IMPID
Definition misc.hh:76
gem5::RiscvISA::MISCREG_HPMEVENT07
@ MISCREG_HPMEVENT07
Definition misc.hh:117
gem5::RiscvISA::MISCREG_RESERVED01
@ MISCREG_RESERVED01
Definition misc.hh:179
gem5::RiscvISA::MISCREG_HPMCOUNTER16
@ MISCREG_HPMCOUNTER16
Definition misc.hh:97
gem5::RiscvISA::MISCREG_HPMCOUNTER13H
@ MISCREG_HPMCOUNTER13H
Definition misc.hh:274
gem5::RiscvISA::MISCREG_SENVCFG
@ MISCREG_SENVCFG
Definition misc.hh:188
gem5::RiscvISA::MISCREG_HPMCOUNTER19
@ MISCREG_HPMCOUNTER19
Definition misc.hh:100
gem5::RiscvISA::MISCREG_PMPADDR12
@ MISCREG_PMPADDR12
Definition misc.hh:174
gem5::RiscvISA::MISCREG_HPMCOUNTER07
@ MISCREG_HPMCOUNTER07
Definition misc.hh:88
gem5::RiscvISA::MISCREG_HPMEVENT29
@ MISCREG_HPMEVENT29
Definition misc.hh:139
gem5::RiscvISA::MISCREG_HPMCOUNTER26
@ MISCREG_HPMCOUNTER26
Definition misc.hh:107
gem5::RiscvISA::MISCREG_PMPADDR05
@ MISCREG_PMPADDR05
Definition misc.hh:167
gem5::RiscvISA::MISCREG_RESERVED03
@ MISCREG_RESERVED03
Definition misc.hh:190
gem5::RiscvISA::MISCREG_HPMCOUNTER13
@ MISCREG_HPMCOUNTER13
Definition misc.hh:94
gem5::RiscvISA::MISCREG_PMPADDR10
@ MISCREG_PMPADDR10
Definition misc.hh:172
gem5::RiscvISA::MISCREG_PMPADDR14
@ MISCREG_PMPADDR14
Definition misc.hh:176
gem5::RiscvISA::MISCREG_PMPCFG3
@ MISCREG_PMPCFG3
Definition misc.hh:161
gem5::RiscvISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition misc.hh:295
gem5::RiscvISA::MISCREG_HPMCOUNTER22H
@ MISCREG_HPMCOUNTER22H
Definition misc.hh:283
gem5::RiscvISA::MISCREG_PMPADDR09
@ MISCREG_PMPADDR09
Definition misc.hh:171
gem5::RiscvISA::MISCREG_HPMEVENT06
@ MISCREG_HPMEVENT06
Definition misc.hh:116
gem5::RiscvISA::MISCREG_TSELECT
@ MISCREG_TSELECT
Definition misc.hh:142
gem5::RiscvISA::MISCREG_MSCRATCH
@ MISCREG_MSCRATCH
Definition misc.hh:154
gem5::RiscvISA::MISCREG_HPMCOUNTER04H
@ MISCREG_HPMCOUNTER04H
Definition misc.hh:265
gem5::RiscvISA::MISCREG_MNCAUSE
@ MISCREG_MNCAUSE
Definition misc.hh:255
gem5::RiscvISA::MISCREG_HPMEVENT21
@ MISCREG_HPMEVENT21
Definition misc.hh:131
gem5::RiscvISA::MISCREG_HPMCOUNTER12H
@ MISCREG_HPMCOUNTER12H
Definition misc.hh:273
gem5::RiscvISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition misc.hh:78
gem5::RiscvISA::MISCREG_HPMEVENT12
@ MISCREG_HPMEVENT12
Definition misc.hh:122
gem5::RiscvISA::MISCREG_HPMCOUNTER25
@ MISCREG_HPMCOUNTER25
Definition misc.hh:106
gem5::RiscvISA::MISCREG_RESERVED05
@ MISCREG_RESERVED05
Definition misc.hh:192
gem5::RiscvISA::MISCREG_PMPADDR04
@ MISCREG_PMPADDR04
Definition misc.hh:166
gem5::RiscvISA::MISCREG_INSTRETH
@ MISCREG_INSTRETH
Definition misc.hh:263
gem5::RiscvISA::MISCREG_MCOUNTEREN
@ MISCREG_MCOUNTEREN
Definition misc.hh:153
gem5::RiscvISA::MISCREG_PMPADDR00
@ MISCREG_PMPADDR00
Definition misc.hh:162
gem5::RiscvISA::MISCREG_HPMCOUNTER22
@ MISCREG_HPMCOUNTER22
Definition misc.hh:103
gem5::RiscvISA::MISCREG_RESERVED02
@ MISCREG_RESERVED02
Definition misc.hh:180
gem5::RiscvISA::MISCREG_HPMEVENT17
@ MISCREG_HPMEVENT17
Definition misc.hh:127
gem5::RiscvISA::MISCREG_RESERVED06
@ MISCREG_RESERVED06
Definition misc.hh:193
gem5::RiscvISA::MISCREG_HPMEVENT20
@ MISCREG_HPMEVENT20
Definition misc.hh:130
gem5::RiscvISA::MISCREG_HPMCOUNTER03H
@ MISCREG_HPMCOUNTER03H
Definition misc.hh:264
gem5::RiscvISA::MISCREG_HPMCOUNTER15H
@ MISCREG_HPMCOUNTER15H
Definition misc.hh:276
gem5::RiscvISA::MISCREG_MEDELEG
@ MISCREG_MEDELEG
Definition misc.hh:150
gem5::RiscvISA::MISCREG_HPMEVENT25
@ MISCREG_HPMEVENT25
Definition misc.hh:135
gem5::RiscvISA::MISCREG_HPMCOUNTER31H
@ MISCREG_HPMCOUNTER31H
Definition misc.hh:292
gem5::RiscvISA::MISCREG_HPMCOUNTER11
@ MISCREG_HPMCOUNTER11
Definition misc.hh:92
gem5::RiscvISA::MISCREG_HPMCOUNTER17H
@ MISCREG_HPMCOUNTER17H
Definition misc.hh:278
gem5::RiscvISA::MISCREG_HPMEVENT03
@ MISCREG_HPMEVENT03
Definition misc.hh:113
gem5::RiscvISA::MISCREG_PMPCFG1
@ MISCREG_PMPCFG1
Definition misc.hh:159
gem5::RiscvISA::MISCREG_HPMEVENT13
@ MISCREG_HPMEVENT13
Definition misc.hh:123
gem5::RiscvISA::MISCREG_PMPADDR13
@ MISCREG_PMPADDR13
Definition misc.hh:175
gem5::RiscvISA::MISCREG_FFLAGS_EXE
@ MISCREG_FFLAGS_EXE
Definition misc.hh:296
gem5::RiscvISA::MISCREG_HPMCOUNTER12
@ MISCREG_HPMCOUNTER12
Definition misc.hh:93
gem5::RiscvISA::MISCREG_HPMCOUNTER29H
@ MISCREG_HPMCOUNTER29H
Definition misc.hh:290
gem5::RiscvISA::MISCREG_HENVCFG
@ MISCREG_HENVCFG
Definition misc.hh:222
gem5::RiscvISA::MISCREG_HPMEVENT04
@ MISCREG_HPMEVENT04
Definition misc.hh:114
gem5::RiscvISA::MISCREG_HPMEVENT08
@ MISCREG_HPMEVENT08
Definition misc.hh:118
gem5::RiscvISA::MISCREG_HIDELEG
@ MISCREG_HIDELEG
Definition misc.hh:215
gem5::RiscvISA::MISCREG_HPMEVENT19
@ MISCREG_HPMEVENT19
Definition misc.hh:129
gem5::RiscvISA::MISCREG_DSCRATCH
@ MISCREG_DSCRATCH
Definition misc.hh:148
gem5::RiscvISA::MISCREG_HPMEVENT30
@ MISCREG_HPMEVENT30
Definition misc.hh:140
gem5::RiscvISA::MISCREG_PMPADDR06
@ MISCREG_PMPADDR06
Definition misc.hh:168
gem5::RiscvISA::MISCREG_HPMCOUNTER21
@ MISCREG_HPMCOUNTER21
Definition misc.hh:102
gem5::RiscvISA::MISCREG_HPMCOUNTER21H
@ MISCREG_HPMCOUNTER21H
Definition misc.hh:282
gem5::RiscvISA::MISCREG_PMPADDR03
@ MISCREG_PMPADDR03
Definition misc.hh:165
gem5::RiscvISA::MISCREG_SCOUNTEREN
@ MISCREG_SCOUNTEREN
Definition misc.hh:182
gem5::RiscvISA::MISCREG_HPMCOUNTER18H
@ MISCREG_HPMCOUNTER18H
Definition misc.hh:279
gem5::RiscvISA::MISCREG_HPMCOUNTER06
@ MISCREG_HPMCOUNTER06
Definition misc.hh:87
gem5::RiscvISA::MISCREG_HPMCOUNTER20H
@ MISCREG_HPMCOUNTER20H
Definition misc.hh:281
gem5::RiscvISA::MISCREG_HPMCOUNTER28
@ MISCREG_HPMCOUNTER28
Definition misc.hh:109
gem5::RiscvISA::MISCREG_PMPADDR02
@ MISCREG_PMPADDR02
Definition misc.hh:164
gem5::RiscvISA::MISCREG_MIDELEG
@ MISCREG_MIDELEG
Definition misc.hh:151
gem5::RiscvISA::MISCREG_HPMCOUNTER30
@ MISCREG_HPMCOUNTER30
Definition misc.hh:111
gem5::RiscvISA::MISCREG_VSSCRATCH
@ MISCREG_VSSCRATCH
Definition misc.hh:229
gem5::RiscvISA::MISCREG_HPMCOUNTER14
@ MISCREG_HPMCOUNTER14
Definition misc.hh:95
gem5::RiscvISA::MISCREG_MSTATUSH
@ MISCREG_MSTATUSH
Definition misc.hh:259
gem5::RiscvISA::MISCREG_HPMEVENT10
@ MISCREG_HPMEVENT10
Definition misc.hh:120
gem5::RiscvISA::MISCREG_HPMEVENT26
@ MISCREG_HPMEVENT26
Definition misc.hh:136
gem5::RiscvISA::MISCREG_HPMEVENT18
@ MISCREG_HPMEVENT18
Definition misc.hh:128
gem5::RiscvISA::MISCREG_VSSTATUS
@ MISCREG_VSSTATUS
Definition misc.hh:227
gem5::RiscvISA::MISCREG_HPMEVENT23
@ MISCREG_HPMEVENT23
Definition misc.hh:133
gem5::RiscvISA::MISCREG_INSTRET
@ MISCREG_INSTRET
Definition misc.hh:83
gem5::RiscvISA::MISCREG_HARTID
@ MISCREG_HARTID
Definition misc.hh:77
gem5::RiscvISA::MISCREG_MNSTATUS
@ MISCREG_MNSTATUS
Definition misc.hh:256
gem5::RiscvISA::MISCREG_HPMCOUNTER05H
@ MISCREG_HPMCOUNTER05H
Definition misc.hh:266
gem5::RiscvISA::MISCREG_HPMCOUNTER20
@ MISCREG_HPMCOUNTER20
Definition misc.hh:101
gem5::RiscvISA::MISCREG_HPMEVENT09
@ MISCREG_HPMEVENT09
Definition misc.hh:119
gem5::RiscvISA::MISCREG_HPMCOUNTER04
@ MISCREG_HPMCOUNTER04
Definition misc.hh:85
gem5::RiscvISA::MISCREG_HPMCOUNTER25H
@ MISCREG_HPMCOUNTER25H
Definition misc.hh:286
gem5::RiscvISA::MISCREG_HPMCOUNTER27H
@ MISCREG_HPMCOUNTER27H
Definition misc.hh:288
gem5::RiscvISA::MISCREG_HPMCOUNTER06H
@ MISCREG_HPMCOUNTER06H
Definition misc.hh:267
gem5::RiscvISA::MISCREG_RESERVED07
@ MISCREG_RESERVED07
Definition misc.hh:194
gem5::RiscvISA::MISCREG_PMPADDR07
@ MISCREG_PMPADDR07
Definition misc.hh:169
gem5::RiscvISA::MISCREG_HPMCOUNTER08H
@ MISCREG_HPMCOUNTER08H
Definition misc.hh:269
gem5::RiscvISA::MISCREG_HPMEVENT16
@ MISCREG_HPMEVENT16
Definition misc.hh:126
gem5::RiscvISA::MISCREG_HPMCOUNTER18
@ MISCREG_HPMCOUNTER18
Definition misc.hh:99
gem5::RiscvISA::MISCREG_SSCRATCH
@ MISCREG_SSCRATCH
Definition misc.hh:183
gem5::RiscvISA::MISCREG_HPMCOUNTER19H
@ MISCREG_HPMCOUNTER19H
Definition misc.hh:280
gem5::RiscvISA::MISCREG_HPMEVENT14
@ MISCREG_HPMEVENT14
Definition misc.hh:124
gem5::RiscvISA::MISCREG_VSCAUSE
@ MISCREG_VSCAUSE
Definition misc.hh:231
gem5::RiscvISA::MISCREG_HPMCOUNTER10H
@ MISCREG_HPMCOUNTER10H
Definition misc.hh:271
gem5::RiscvISA::MISCREG_HPMCOUNTER05
@ MISCREG_HPMCOUNTER05
Definition misc.hh:86
gem5::RiscvISA::MISCREG_HPMCOUNTER30H
@ MISCREG_HPMCOUNTER30H
Definition misc.hh:291
gem5::RiscvISA::MISCREG_HPMCOUNTER17
@ MISCREG_HPMCOUNTER17
Definition misc.hh:98
gem5::RiscvISA::MISCREG_HCONTEXT
@ MISCREG_HCONTEXT
Definition misc.hh:224
gem5::RiscvISA::MISCREG_HPMCOUNTER09H
@ MISCREG_HPMCOUNTER09H
Definition misc.hh:270
gem5::RiscvISA::MISCREG_HPMCOUNTER27
@ MISCREG_HPMCOUNTER27
Definition misc.hh:108
gem5::RiscvISA::MISCREG_HPMCOUNTER24
@ MISCREG_HPMCOUNTER24
Definition misc.hh:105
gem5::RiscvISA::MISCREG_HPMCOUNTER28H
@ MISCREG_HPMCOUNTER28H
Definition misc.hh:289
gem5::RiscvISA::MISCREG_HPMCOUNTER14H
@ MISCREG_HPMCOUNTER14H
Definition misc.hh:275
gem5::RiscvISA::MISCREG_HPMCOUNTER23
@ MISCREG_HPMCOUNTER23
Definition misc.hh:104
gem5::RiscvISA::MISCREG_CYCLE
@ MISCREG_CYCLE
Definition misc.hh:81
gem5::RiscvISA::MISCREG_RESERVED04
@ MISCREG_RESERVED04
Definition misc.hh:191
gem5::RiscvISA::MISCREG_HPMCOUNTER07H
@ MISCREG_HPMCOUNTER07H
Definition misc.hh:268
gem5::RiscvISA::MISCREG_MNSCRATCH
@ MISCREG_MNSCRATCH
Definition misc.hh:253
gem5::RiscvISA::MISCREG_HPMCOUNTER15
@ MISCREG_HPMCOUNTER15
Definition misc.hh:96
gem5::RiscvISA::MISCREG_HPMEVENT24
@ MISCREG_HPMEVENT24
Definition misc.hh:134
gem5::RiscvISA::MISCREG_HPMCOUNTER10
@ MISCREG_HPMCOUNTER10
Definition misc.hh:91
gem5::RiscvISA::MISCREG_HPMCOUNTER29
@ MISCREG_HPMCOUNTER29
Definition misc.hh:110
gem5::RiscvISA::MISCREG_VENDORID
@ MISCREG_VENDORID
Definition misc.hh:74
gem5::RiscvISA::MISCREG_PMPADDR01
@ MISCREG_PMPADDR01
Definition misc.hh:163
gem5::RiscvISA::MISCREG_HEDELEG
@ MISCREG_HEDELEG
Definition misc.hh:214
gem5::RiscvISA::MISCREG_HPMEVENT27
@ MISCREG_HPMEVENT27
Definition misc.hh:137
gem5::RiscvISA::MISCREG_HPMEVENT15
@ MISCREG_HPMEVENT15
Definition misc.hh:125
gem5::RiscvISA::MISCREG_HPMEVENT05
@ MISCREG_HPMEVENT05
Definition misc.hh:115
gem5::RiscvISA::MISCREG_ARCHID
@ MISCREG_ARCHID
Definition misc.hh:75
gem5::RiscvISA::MISCREG_HPMCOUNTER24H
@ MISCREG_HPMCOUNTER24H
Definition misc.hh:285
gem5::RiscvISA::MISCREG_HPMEVENT11
@ MISCREG_HPMEVENT11
Definition misc.hh:121
gem5::RiscvISA::MISCREG_HPMCOUNTER31
@ MISCREG_HPMCOUNTER31
Definition misc.hh:112
gem5::RiscvISA::MISCREG_HPMCOUNTER23H
@ MISCREG_HPMCOUNTER23H
Definition misc.hh:284
gem5::RiscvISA::MISCREG_HTIMEDELTA
@ MISCREG_HTIMEDELTA
Definition misc.hh:225
gem5::RiscvISA::MISCREG_HPMCOUNTER11H
@ MISCREG_HPMCOUNTER11H
Definition misc.hh:272
gem5::RiscvISA::MISCREG_PMPADDR08
@ MISCREG_PMPADDR08
Definition misc.hh:170
gem5::RiscvISA::MISCREG_HPMCOUNTER03
@ MISCREG_HPMCOUNTER03
Definition misc.hh:84
gem5::RiscvISA::MISCREG_PMPADDR15
@ MISCREG_PMPADDR15
Definition misc.hh:177
gem5::RiscvISA::MISCREG_HPMEVENT28
@ MISCREG_HPMEVENT28
Definition misc.hh:138
gem5::RiscvISA::MISCREG_HCOUNTEREN
@ MISCREG_HCOUNTEREN
Definition misc.hh:216
gem5::RiscvISA::MISCREG_HPMEVENT22
@ MISCREG_HPMEVENT22
Definition misc.hh:132
gem5::RiscvISA::MISCREG_PMPCFG0
@ MISCREG_PMPCFG0
Definition misc.hh:158
gem5::RiscvISA::MISCREG_HPMCOUNTER08
@ MISCREG_HPMCOUNTER08
Definition misc.hh:89
gem5::RiscvISA::MISCREG_HPMCOUNTER26H
@ MISCREG_HPMCOUNTER26H
Definition misc.hh:287
gem5::RiscvISA::MISCREG_PMPCFG2
@ MISCREG_PMPCFG2
Definition misc.hh:160
gem5::RiscvISA::MISA_MASKS
const RegVal MISA_MASKS[enums::Num_RiscvType]
Definition misc.hh:1482
gem5::RiscvISA::rvk
Bitfield< 10 > rvk
Definition misc.hh:1405
gem5::RiscvISA::HSTATUS_GVA_MASK
const RegVal HSTATUS_GVA_MASK
Definition misc.hh:1531
gem5::RiscvISA::rvt
Bitfield< 19 > rvt
Definition misc.hh:1398
gem5::RiscvISA::FRM_OFFSET
const off_t FRM_OFFSET
Definition misc.hh:1474
gem5::RiscvISA::vs
Bitfield< 9, 5 > vs
Definition pra_constants.hh:149
gem5::RiscvISA::xs
Bitfield< 16, 15 > xs
Definition misc.hh:1348
gem5::RiscvISA::ISA_MXL_MASKS
const RegVal ISA_MXL_MASKS[enums::Num_RiscvType]
Definition misc.hh:1476
gem5::RiscvISA::wpri_2
Bitfield< 31, 8 > wpri_2
Definition misc.hh:1444
gem5::RiscvISA::STI_MASK
const RegVal STI_MASK
Definition misc.hh:1638
gem5::RiscvISA::spvp
Bitfield< 8 > spvp
Definition misc.hh:1369
gem5::RiscvISA::MI_MASK
const RegVal MI_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1643
gem5::RiscvISA::MIDELEG_MASK
const RegVal MIDELEG_MASK[enums::Num_PrivilegeModeSet]
Definition misc.hh:1664
gem5::RiscvISA::STATUS_SUM_MASK
const RegVal STATUS_SUM_MASK
Definition misc.hh:1509
gem5::RiscvISA::BitUnion64
BitUnion64(SATP) Bitfield< 63
gem5::RiscvISA::rvf
Bitfield< 5 > rvf
Definition misc.hh:1410
gem5::RiscvISA::rvj
Bitfield< 9 > rvj
Definition misc.hh:1406
gem5::RiscvISA::rv32_mxl
Bitfield< 31, 30 > rv32_mxl
Definition misc.hh:1394
gem5::RiscvISA::rvc
Bitfield< 2 > rvc
Definition misc.hh:1413
gem5::RiscvISA::rvl
Bitfield< 11 > rvl
Definition misc.hh:1404
gem5::RiscvISA::SBE_OFFSET
const off_t SBE_OFFSET[enums::Num_RiscvType]
Definition misc.hh:1465
gem5::RiscvISA::cbze
Bitfield< 7 > cbze
Definition misc.hh:1445
gem5::RiscvISA::mxr
Bitfield< 19 > mxr
Definition misc.hh:1345
gem5::RiscvISA::DELEGABLE_EXCPS_WITH_RVH
const RegVal DELEGABLE_EXCPS_WITH_RVH
Definition fault_codes.hh:173
gem5::RiscvISA::rvTypeFlags
constexpr uint64_t rvTypeFlags(T... args)
Definition misc.hh:591
gem5::RiscvISA::sei
Bitfield< 9 > sei
Definition misc.hh:1429
gem5::RiscvISA::STATUS_TVM_MASK
const RegVal STATUS_TVM_MASK
Definition misc.hh:1507
gem5::RiscvISA::hu
Bitfield< 9 > hu
Definition misc.hh:1368
gem5::RiscvISA::MSTATUS_MASKS
const RegVal MSTATUS_MASKS[enums::Num_RiscvType][enums::Num_PrivilegeModeSet]
Definition misc.hh:1535
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
gem5::MiscRegClassName
constexpr char MiscRegClassName[]
Definition reg_class.hh:82
gem5::RegVal
uint64_t RegVal
Definition types.hh:173
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition reg_class.hh:70
reg_class.hh
gem5::RiscvISA::CSRMetadata::rvTypes
const uint64_t rvTypes
Definition misc.hh:585
gem5::RiscvISA::CSRMetadata::isaExts
const uint64_t isaExts
Definition misc.hh:586
gem5::RiscvISA::CSRMetadata::name
const std::string name
Definition misc.hh:583
vec_pred_reg.hh
vec_reg.hh
Vector Registers layout specification.
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