#include <thread_context.hh>

Inheritance diagram for gem5::Iris::ThreadContext:

Classes
struct	BpInfo

Public Types
typedef std::map< std::string, iris::ResourceInfo >	ResourceMap
typedef std::vector< iris::ResourceId >	ResourceIds
typedef std::map< int, std::string >	IdxNameMap
typedef std::unordered_map< Iris::CanonicalMsn, iris::MemorySpaceId >	MemorySpaceMap
Public Types inherited from gem5::ThreadContext
enum	Status { Active , Suspended , Halting , Halted }

Public Member Functions
	ThreadContext (gem5::BaseCPU cpu, int id, System system, gem5::BaseMMU mmu, gem5::BaseISA isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
virtual	~ThreadContext ()
virtual bool	translateAddress (Addr &paddr, Addr vaddr)=0
bool	schedule (PCEvent *e) override
bool	remove (PCEvent *e) override
void	scheduleInstCountEvent (Event *event, Tick count) override
void	descheduleInstCountEvent (Event *event) override
Tick	getCurrentInstCount () override
gem5::BaseCPU *	getCpuPtr () override
int	cpuId () const override
uint32_t	socketId () const override
int	threadId () const override
void	setThreadId (int id) override
int	contextId () const override
void	setContextId (int id) override
BaseMMU *	getMMUPtr () override
CheckerCPU *	getCheckerCpuPtr () override
InstDecoder *	getDecoderPtr () override
System *	getSystemPtr () override
BaseISA *	getIsaPtr () const override
void	sendFunctional (PacketPtr pkt) override
Process *	getProcessPtr () override
void	setProcessPtr (Process *p) override
Status	status () const override
void	setStatus (Status new_status) override
void	activate () override
	Set the status to Active.
void	suspend () override
	Set the status to Suspended.
void	halt () override
	Set the status to Halted.
void	takeOverFrom (gem5::ThreadContext *old_context) override
void	regStats (const std::string &name) override
Tick	readLastActivate () override
Tick	readLastSuspend () override
void	copyArchRegs (gem5::ThreadContext *tc) override
void	clearArchRegs () override
RegVal	getReg (const RegId &reg) const override
void	getReg (const RegId &reg, void *val) const override
void *	getWritableReg (const RegId &reg) override
void	setReg (const RegId &reg, RegVal val) override
void	setReg (const RegId &reg, const void *val) override
iris::ResourceId	getIntRegRscId (RegIndex int_reg) const
virtual RegVal	readIntReg (RegIndex reg_idx) const
iris::ResourceId	getVecRegRscId (RegIndex vec_reg) const
virtual const ArmISA::VecRegContainer &	readVecReg (const RegId &reg) const
virtual ArmISA::VecRegContainer &	getWritableVecReg (const RegId &reg)
virtual RegVal	readVecElem (const RegId &reg) const
iris::ResourceId	getVecPredRegRscId (RegIndex vec_reg) const
virtual const ArmISA::VecPredRegContainer &	readVecPredReg (const RegId &reg) const
virtual ArmISA::VecPredRegContainer &	getWritableVecPredReg (const RegId &reg)
virtual RegVal	readCCReg (RegIndex reg_idx) const
virtual void	setIntReg (RegIndex reg_idx, RegVal val)
virtual void	setVecReg (const RegId &reg, const ArmISA::VecRegContainer &val)
virtual void	setVecElem (const RegId &reg, RegVal val)
virtual void	setVecPredReg (const RegId &reg, const ArmISA::VecPredRegContainer &val)
virtual void	setCCReg (RegIndex reg_idx, RegVal val)
void	pcStateNoRecord (const PCStateBase &val) override
const PCStateBase &	pcState () const override
void	pcState (const PCStateBase &val) override
iris::ResourceId	getMiscRegRscId (RegIndex misc_reg) const
RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override
RegVal	readMiscReg (RegIndex misc_reg) override
void	setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override
void	setMiscReg (RegIndex misc_reg, const RegVal val) override
unsigned	readStCondFailures () const override
void	setStCondFailures (unsigned sc_failures) override
void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override
BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override
void	setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt) override
void	readMemWithCurrentMsn (Addr vaddr, size_t size, char *data)
void	writeMemWithCurrentMsn (Addr vaddr, size_t size, const char *data)

iris::ResourceId	getIntRegFlatRscId (RegIndex int_reg) const
	Flat register interfaces.
virtual RegVal	readIntRegFlat (RegIndex idx) const
virtual void	setIntRegFlat (RegIndex idx, uint64_t val)
virtual const ArmISA::VecRegContainer &	readVecRegFlat (RegIndex idx) const
virtual ArmISA::VecRegContainer &	getWritableVecRegFlat (RegIndex idx)
virtual void	setVecRegFlat (RegIndex idx, const ArmISA::VecRegContainer &val)
virtual RegVal	readVecElemFlat (RegIndex idx) const
virtual void	setVecElemFlat (RegIndex idx, RegVal val)
virtual ArmISA::VecPredRegContainer	readVecPredRegFlat (RegIndex idx) const
virtual ArmISA::VecPredRegContainer &	getWritableVecPredRegFlat (RegIndex idx)
virtual void	setVecPredRegFlat (RegIndex idx, const ArmISA::VecPredRegContainer &val)
iris::ResourceId	getCCRegFlatRscId (RegIndex cc_reg) const
virtual RegVal	readCCRegFlat (RegIndex idx) const
virtual void	setCCRegFlat (RegIndex idx, RegVal val)
Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()
void	setUseForClone (bool new_val)
void	quiesce ()
	Quiesce thread context.
void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume.
void	pcState (Addr addr)
virtual int	exit ()

Protected Types
using	BpId = uint64_t
using	BpInfoPtr = std::unique_ptr<BpInfo>
using	BpInfoMap = std::map<Addr, BpInfoPtr>
using	BpInfoIt = BpInfoMap::iterator

Protected Member Functions
virtual void	initFromIrisInstance (const ResourceMap &resources)
iris::ResourceId	extractResourceId (const ResourceMap &resources, const std::string &name)
void	extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
iris::MemorySpaceId	getMemorySpaceId (const Iris::CanonicalMsn &msn) const
void	maintainStepping ()
BpInfoIt	getOrAllocBp (Addr pc)
void	installBp (BpInfoIt it)
void	uninstallBp (BpInfoIt it)
void	delBp (BpInfoIt it)
virtual const std::vector< iris::MemorySpaceId > &	getBpSpaceIds () const =0
iris::IrisErrorCode	instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
iris::IrisErrorCode	phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
iris::IrisErrorCode	simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
iris::IrisErrorCode	breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
iris::IrisErrorCode	semihostingEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
iris::IrisCppAdapter &	call () const
iris::IrisCppAdapter &	noThrow () const
void	readMem (iris::MemorySpaceId space, Addr addr, void *p, size_t size)
void	writeMem (iris::MemorySpaceId space, Addr addr, const void *p, size_t size)
bool	translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)

Protected Attributes
gem5::BaseCPU *	_cpu
int	_threadId
ContextID	_contextId
System *	_system
gem5::BaseMMU *	_mmu
gem5::BaseISA *	_isa
std::string	_irisPath
iris::InstanceId	_instId = iris::IRIS_UINT64_MAX
std::vector< ArmISA::VecRegContainer >	vecRegs
std::vector< ArmISA::VecPredRegContainer >	vecPredRegs
Status	_status = Active
Event *	enableAfterPseudoEvent
ResourceIds	miscRegIds
ResourceIds	intReg32Ids
ResourceIds	intReg64Ids
ResourceIds	flattenedIntIds
ResourceIds	ccRegIds
iris::ResourceId	pcRscId = iris::IRIS_UINT64_MAX
iris::ResourceId	icountRscId
ResourceIds	vecRegIds
ResourceIds	vecPredRegIds
std::vector< iris::MemorySpaceInfo >	memorySpaces
std::vector< iris::MemorySupportedAddressTranslationResult >	translations
MemorySpaceMap	memorySpaceIds
EventQueue	comInstEventQueue
BpInfoMap	bps
std::optional< Addr >	bpAddr
iris::EventStreamId	regEventStreamId
iris::EventStreamId	initEventStreamId
iris::EventStreamId	timeEventStreamId
iris::EventStreamId	breakpointEventStreamId
iris::EventStreamId	semihostingEventStreamId
iris::IrisInstance	client
ArmISA::PCState	pc
Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Additional Inherited Members
Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext one, ThreadContext two)
	function to compare two thread contexts (for debugging)
Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult
double	floatResult = DefaultFloatResult
int	intOffset = 0
Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []
static const double	floats []
static const int	DefaultIntResult = 0
static const double	DefaultFloatResult = 0.0

Detailed Description

Definition at line 54 of file thread_context.hh.

Member Typedef Documentation

◆ BpId

using gem5::Iris::ThreadContext::BpId = uint64_t

protected

Definition at line 117 of file thread_context.hh.

◆ BpInfoIt

using gem5::Iris::ThreadContext::BpInfoIt = BpInfoMap::iterator

protected

Definition at line 134 of file thread_context.hh.

◆ BpInfoMap

using gem5::Iris::ThreadContext::BpInfoMap = std::map<Addr, BpInfoPtr>

protected

Definition at line 133 of file thread_context.hh.

◆ BpInfoPtr

using gem5::Iris::ThreadContext::BpInfoPtr = std::unique_ptr<BpInfo>

protected

Definition at line 132 of file thread_context.hh.

◆ IdxNameMap

typedef std::map<int, std::string> gem5::Iris::ThreadContext::IdxNameMap

Definition at line 60 of file thread_context.hh.

◆ MemorySpaceMap

typedef std::unordered_map<Iris::CanonicalMsn, iris::MemorySpaceId> gem5::Iris::ThreadContext::MemorySpaceMap

Definition at line 63 of file thread_context.hh.

◆ ResourceIds

typedef std::vector<iris::ResourceId> gem5::Iris::ThreadContext::ResourceIds

Definition at line 59 of file thread_context.hh.

◆ ResourceMap

typedef std::map<std::string, iris::ResourceInfo> gem5::Iris::ThreadContext::ResourceMap

Definition at line 57 of file thread_context.hh.

Constructor & Destructor Documentation

◆ ThreadContext()

gem5::Iris::ThreadContext::ThreadContext	(	gem5::BaseCPU *	cpu,
		int	id,
		System *	system,
		gem5::BaseMMU *	mmu,
		gem5::BaseISA *	isa,
		iris::IrisConnectionInterface *	iris_if,
		const std::string &	iris_path )

◆ ~ThreadContext()

gem5::Iris::ThreadContext::~ThreadContext ( )

virtual

Reimplemented from gem5::ThreadContext.

Definition at line 401 of file thread_context.cc.

References call(), client, gem5::EventManager::deschedule(), enableAfterPseudoEvent, getCpuPtr(), initEventStreamId, regEventStreamId, and timeEventStreamId.

Member Function Documentation

◆ activate()

void gem5::Iris::ThreadContext::activate ( )

inlineoverridevirtual

Set the status to Active.

Implements gem5::ThreadContext.

Definition at line 245 of file thread_context.hh.

References gem5::ThreadContext::Active, and setStatus().

◆ breakpointHit()

iris::IrisErrorCode gem5::Iris::ThreadContext::breakpointHit	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out )

protected

Definition at line 301 of file thread_context.cc.

References bpAddr, and pc.

◆ call()

iris::IrisCppAdapter & gem5::Iris::ThreadContext::call ( ) const

inlineprotected

◆ clearArchRegs()

void gem5::Iris::ThreadContext::clearArchRegs ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 276 of file thread_context.hh.

References warn.

◆ contextId()

int gem5::Iris::ThreadContext::contextId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 206 of file thread_context.hh.

References _contextId.

◆ copyArchRegs()

void gem5::Iris::ThreadContext::copyArchRegs ( gem5::ThreadContext * tc )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 270 of file thread_context.hh.

References panic.

◆ cpuId()

int gem5::Iris::ThreadContext::cpuId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 200 of file thread_context.hh.

References _cpu.

◆ delBp()

void gem5::Iris::ThreadContext::delBp ( BpInfoIt it )

protected

Definition at line 199 of file thread_context.cc.

References bps, panic_if, and uninstallBp().

Referenced by remove().

◆ descheduleInstCountEvent()

void gem5::Iris::ThreadContext::descheduleInstCountEvent ( Event * event )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 510 of file thread_context.cc.

References comInstEventQueue, gem5::MipsISA::event, and maintainStepping().

◆ extractResourceId()

iris::ResourceId gem5::Iris::ThreadContext::extractResourceId	(	const ResourceMap &	resources,
		const std::string &	name )

protected

Definition at line 107 of file thread_context.cc.

References name().

Referenced by extractResourceMap(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and gem5::fastmodel::CortexR52TC::initFromIrisInstance().

◆ extractResourceMap()

void gem5::Iris::ThreadContext::extractResourceMap	(	ResourceIds &	ids,
		const ResourceMap &	resources,
		const IdxNameMap &	idx_names )

protected

Definition at line 114 of file thread_context.cc.

References extractResourceId(), gem5::ArmISA::ids, and name().

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and gem5::fastmodel::CortexR52TC::initFromIrisInstance().

◆ getBpSpaceIds()

virtual const std::vector< iris::MemorySpaceId > & gem5::Iris::ThreadContext::getBpSpaceIds ( ) const

protectedpure virtual

Implemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Referenced by installBp().

◆ getCCRegFlatRscId()

iris::ResourceId gem5::Iris::ThreadContext::getCCRegFlatRscId ( RegIndex cc_reg ) const

Definition at line 853 of file thread_context.cc.

References ccRegIds.

Referenced by readCCRegFlat(), and setCCRegFlat().

◆ getCheckerCpuPtr()

CheckerCPU * gem5::Iris::ThreadContext::getCheckerCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 215 of file thread_context.hh.

◆ getCpuPtr()

gem5::BaseCPU * gem5::Iris::ThreadContext::getCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 199 of file thread_context.hh.

References _cpu.

Referenced by semihostingEvent(), setStatus(), and ~ThreadContext().

◆ getCurrentInstCount()

Tick gem5::Iris::ThreadContext::getCurrentInstCount ( )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 517 of file thread_context.cc.

References _instId, call(), gem5::X86ISA::count, and panic_if.

Referenced by maintainStepping(), and scheduleInstCountEvent().

◆ getDecoderPtr()

InstDecoder * gem5::Iris::ThreadContext::getDecoderPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 217 of file thread_context.hh.

References panic.

◆ getHtmCheckpointPtr()

BaseHTMCheckpointPtr & gem5::Iris::ThreadContext::getHtmCheckpointPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 449 of file thread_context.hh.

References panic.

◆ getIntRegFlatRscId()

iris::ResourceId gem5::Iris::ThreadContext::getIntRegFlatRscId ( RegIndex int_reg ) const

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Definition at line 818 of file thread_context.cc.

References flattenedIntIds.

Referenced by readIntRegFlat(), and setIntRegFlat().

◆ getIntRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getIntRegRscId ( RegIndex int_reg ) const

Definition at line 788 of file thread_context.cc.

References intReg32Ids, intReg64Ids, gem5::ArmISA::intRegClass, gem5::ArmISA::MISCREG_CPSR, panic_if, and readMiscRegNoEffect().

Referenced by readIntReg(), and setIntReg().

◆ getIsaPtr()

BaseISA * gem5::Iris::ThreadContext::getIsaPtr ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 225 of file thread_context.hh.

References _isa.

◆ getMemorySpaceId()

iris::MemorySpaceId gem5::Iris::ThreadContext::getMemorySpaceId ( const Iris::CanonicalMsn & msn ) const

protected

Definition at line 130 of file thread_context.cc.

References memorySpaceIds.

Referenced by gem5::fastmodel::CortexA76TC::getBpSpaceIds(), gem5::fastmodel::CortexR52TC::getBpSpaceIds(), readMemWithCurrentMsn(), gem5::fastmodel::CortexR52TC::sendFunctional(), sendFunctional(), gem5::fastmodel::CortexA76TC::translateAddress(), and writeMemWithCurrentMsn().

◆ getMiscRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getMiscRegRscId ( RegIndex misc_reg ) const

Definition at line 613 of file thread_context.cc.

References gem5::ArmISA::miscRegClass, miscRegIds, and panic_if.

Referenced by readMiscRegNoEffect(), and setMiscRegNoEffect().

◆ getMMUPtr()

BaseMMU * gem5::Iris::ThreadContext::getMMUPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 210 of file thread_context.hh.

References _mmu.

◆ getOrAllocBp()

ThreadContext::BpInfoIt gem5::Iris::ThreadContext::getOrAllocBp ( Addr pc )

protected

Definition at line 166 of file thread_context.cc.

References bps, panic_if, and pc.

Referenced by remove(), schedule(), and simulationTimeEvent().

◆ getProcessPtr()

Process * gem5::Iris::ThreadContext::getProcessPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 233 of file thread_context.hh.

References panic.

◆ getReg() [1/2]

RegVal gem5::Iris::ThreadContext::getReg ( const RegId & reg ) const

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 641 of file thread_context.cc.

References getReg(), gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by getReg().

◆ getReg() [2/2]

void gem5::Iris::ThreadContext::getReg	(	const RegId &	reg,
		void *	val ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 655 of file thread_context.cc.

References gem5::CCRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, readCCReg(), readCCRegFlat(), readIntReg(), readIntRegFlat(), readVecElem(), readVecElemFlat(), readVecPredReg(), readVecPredRegFlat(), readVecReg(), readVecRegFlat(), gem5::X86ISA::reg, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ getSystemPtr()

System * gem5::Iris::ThreadContext::getSystemPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 222 of file thread_context.hh.

References _cpu.

◆ getVecPredRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getVecPredRegRscId ( RegIndex vec_reg ) const

Definition at line 922 of file thread_context.cc.

References vecPredRegIds.

Referenced by readVecPredReg().

◆ getVecRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getVecRegRscId ( RegIndex vec_reg ) const

Definition at line 884 of file thread_context.cc.

References vecRegIds.

Referenced by readVecReg().

◆ getWritableReg()

void * gem5::Iris::ThreadContext::getWritableReg ( const RegId & reg )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 761 of file thread_context.cc.

References getWritableVecPredReg(), getWritableVecPredRegFlat(), getWritableVecReg(), getWritableVecRegFlat(), panic, gem5::X86ISA::reg, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ getWritableVecPredReg()

virtual ArmISA::VecPredRegContainer & gem5::Iris::ThreadContext::getWritableVecPredReg ( const RegId & reg )

inlinevirtual

Definition at line 312 of file thread_context.hh.

References panic, and gem5::X86ISA::reg.

Referenced by getWritableReg().

◆ getWritableVecPredRegFlat()

virtual ArmISA::VecPredRegContainer & gem5::Iris::ThreadContext::getWritableVecPredRegFlat ( RegIndex idx )

inlinevirtual

Definition at line 425 of file thread_context.hh.

References panic.

Referenced by getWritableReg().

◆ getWritableVecReg()

virtual ArmISA::VecRegContainer & gem5::Iris::ThreadContext::getWritableVecReg ( const RegId & reg )

inlinevirtual

Definition at line 297 of file thread_context.hh.

References panic, and gem5::X86ISA::reg.

Referenced by getWritableReg().

◆ getWritableVecRegFlat()

virtual ArmISA::VecRegContainer & gem5::Iris::ThreadContext::getWritableVecRegFlat ( RegIndex idx )

inlinevirtual

Definition at line 402 of file thread_context.hh.

References panic.

Referenced by getWritableReg().

◆ halt()

void gem5::Iris::ThreadContext::halt ( )

inlineoverridevirtual

Set the status to Halted.

Implements gem5::ThreadContext.

Definition at line 247 of file thread_context.hh.

References gem5::ThreadContext::Halted, and setStatus().

◆ htmAbortTransaction()

void gem5::Iris::ThreadContext::htmAbortTransaction	(	uint64_t	htm_uid,
		HtmFailureFaultCause	cause )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 443 of file thread_context.hh.

References panic.

◆ initFromIrisInstance()

void gem5::Iris::ThreadContext::initFromIrisInstance ( const ResourceMap & resources )

protectedvirtual

Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Definition at line 66 of file thread_context.cc.

References _instId, _status, gem5::ThreadContext::Active, bps, breakpointEventStreamId, call(), client, gem5::statistics::enabled(), installBp(), memorySpaceIds, memorySpaces, semihostingEventStreamId, suspend(), gem5::ThreadContext::Suspended, ThreadContext(), and translations.

Referenced by phaseInitLeave().

◆ installBp()

void gem5::Iris::ThreadContext::installBp ( BpInfoIt it )

protected

Definition at line 179 of file thread_context.cc.

References _instId, call(), getBpSpaceIds(), gem5::ArmISA::id, and pc.

Referenced by initFromIrisInstance(), and schedule().

◆ instanceRegistryChanged()

iris::IrisErrorCode gem5::Iris::ThreadContext::instanceRegistryChanged	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out )

protected

Definition at line 211 of file thread_context.cc.

References _instId, _irisPath, gem5::MipsISA::event, gem5::ArmISA::id, name(), and panic.

◆ maintainStepping()

void gem5::Iris::ThreadContext::maintainStepping ( )

protected

Definition at line 137 of file thread_context.cc.

References _instId, call(), comInstEventQueue, and getCurrentInstCount().

Referenced by descheduleInstCountEvent(), scheduleInstCountEvent(), and simulationTimeEvent().

◆ noThrow()

iris::IrisCppAdapter & gem5::Iris::ThreadContext::noThrow ( ) const

inlineprotected

Definition at line 172 of file thread_context.hh.

References client.

Referenced by ThreadContext(), and translateAddress().

◆ pcState() [1/2]

const PCStateBase & gem5::Iris::ThreadContext::pcState ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 578 of file thread_context.cc.

References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::itState(), gem5::ArmISA::MISCREG_CPSR, pc, pcRscId, and readMiscRegNoEffect().

Referenced by pcStateNoRecord().

◆ pcState() [2/2]

void gem5::Iris::ThreadContext::pcState ( const PCStateBase & val )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 600 of file thread_context.cc.

References _instId, call(), gem5::ArmISA::MISCREG_CPSR, pc, pcRscId, readMiscRegNoEffect(), and gem5::X86ISA::val.

◆ pcStateNoRecord()

void gem5::Iris::ThreadContext::pcStateNoRecord ( const PCStateBase & val )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 350 of file thread_context.hh.

References pcState(), and gem5::X86ISA::val.

◆ phaseInitLeave()

iris::IrisErrorCode gem5::Iris::ThreadContext::phaseInitLeave	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out )

protected

Definition at line 233 of file thread_context.cc.

References _instId, call(), initFromIrisInstance(), and name().

◆ readCCReg()

virtual RegVal gem5::Iris::ThreadContext::readCCReg ( RegIndex reg_idx ) const

inlinevirtual

Definition at line 318 of file thread_context.hh.

References readCCRegFlat().

Referenced by getReg().

◆ readCCRegFlat()

RegVal gem5::Iris::ThreadContext::readCCRegFlat ( RegIndex idx ) const

virtual

Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Definition at line 862 of file thread_context.cc.

References _instId, call(), and getCCRegFlatRscId().

Referenced by getReg(), readCCReg(), gem5::fastmodel::CortexA76TC::readCCRegFlat(), and gem5::fastmodel::CortexR52TC::readCCRegFlat().

◆ readIntReg()

RegVal gem5::Iris::ThreadContext::readIntReg ( RegIndex reg_idx ) const

virtual

Reimplemented in gem5::fastmodel::CortexR52TC.

Definition at line 803 of file thread_context.cc.

References _instId, call(), and getIntRegRscId().

Referenced by getReg(), and semihostingEvent().

◆ readIntRegFlat()

RegVal gem5::Iris::ThreadContext::readIntRegFlat ( RegIndex idx ) const

virtual

Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Definition at line 831 of file thread_context.cc.

References _instId, call(), and getIntRegFlatRscId().

Referenced by getReg().

◆ readLastActivate()

Tick gem5::Iris::ThreadContext::readLastActivate ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 260 of file thread_context.hh.

References panic.

◆ readLastSuspend()

Tick gem5::Iris::ThreadContext::readLastSuspend ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 264 of file thread_context.hh.

References panic.

◆ readMem()

void gem5::Iris::ThreadContext::readMem	(	iris::MemorySpaceId	space,
		Addr	addr,
		void *	p,
		size_t	size )

protected

Definition at line 448 of file thread_context.cc.

References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::err, gem5::MipsISA::p, panic_if, and gem5::MipsISA::r.

Referenced by readMemWithCurrentMsn(), gem5::fastmodel::CortexR52TC::sendFunctional(), and sendFunctional().

◆ readMemWithCurrentMsn()

void gem5::Iris::ThreadContext::readMemWithCurrentMsn	(	Addr	vaddr,
		size_t	size,
		char *	data )

Definition at line 544 of file thread_context.cc.

References gem5::Iris::CurrentMsn, data, getMemorySpaceId(), readMem(), and gem5::MipsISA::vaddr.

◆ readMiscReg()

RegVal gem5::Iris::ThreadContext::readMiscReg ( RegIndex misc_reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 358 of file thread_context.hh.

References readMiscRegNoEffect().

◆ readMiscRegNoEffect()

RegVal gem5::Iris::ThreadContext::readMiscRegNoEffect ( RegIndex misc_reg ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 626 of file thread_context.cc.

References _instId, call(), and getMiscRegRscId().

Referenced by getIntRegRscId(), pcState(), pcState(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), readMiscReg(), gem5::fastmodel::CortexR52TC::readMiscRegNoEffect(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), and gem5::fastmodel::CortexA76TC::setIntRegFlat().

◆ readStCondFailures()

unsigned gem5::Iris::ThreadContext::readStCondFailures ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 373 of file thread_context.hh.

References panic.

◆ readVecElem()

virtual RegVal gem5::Iris::ThreadContext::readVecElem ( const RegId & reg ) const

inlinevirtual

Definition at line 303 of file thread_context.hh.

References panic, and gem5::X86ISA::reg.

Referenced by getReg().

◆ readVecElemFlat()

virtual RegVal gem5::Iris::ThreadContext::readVecElemFlat ( RegIndex idx ) const

inlinevirtual

Definition at line 413 of file thread_context.hh.

References panic.

Referenced by getReg().

◆ readVecPredReg()

const ArmISA::VecPredRegContainer & gem5::Iris::ThreadContext::readVecPredReg ( const RegId & reg ) const

virtual

Definition at line 931 of file thread_context.cc.

References _instId, call(), getVecPredRegRscId(), gem5::RegId::index(), gem5::ArmISA::offset, gem5::X86ISA::reg, and vecPredRegs.

Referenced by getReg(), and readVecPredRegFlat().

◆ readVecPredRegFlat()

ArmISA::VecPredRegContainer gem5::Iris::ThreadContext::readVecPredRegFlat ( RegIndex idx ) const

virtual

Definition at line 961 of file thread_context.cc.

References readVecPredReg(), and gem5::ArmISA::vecPredRegClass.

Referenced by getReg().

◆ readVecReg()

const ArmISA::VecRegContainer & gem5::Iris::ThreadContext::readVecReg ( const RegId & reg ) const

virtual

Reimplemented in gem5::fastmodel::CortexR52TC.

Definition at line 893 of file thread_context.cc.

References _instId, call(), getVecRegRscId(), gem5::RegId::index(), gem5::X86ISA::reg, and vecRegs.

Referenced by getReg(), and readVecRegFlat().

◆ readVecRegFlat()

const ArmISA::VecRegContainer & gem5::Iris::ThreadContext::readVecRegFlat ( RegIndex idx ) const

virtual

Definition at line 916 of file thread_context.cc.

References readVecReg(), and gem5::ArmISA::vecRegClass.

Referenced by getReg().

◆ regStats()

void gem5::Iris::ThreadContext::regStats ( const std::string & name )

inlineoverridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 255 of file thread_context.hh.

References name().

◆ remove()

bool gem5::Iris::ThreadContext::remove ( PCEvent * e )

overridevirtual

Implements gem5::PCEventScope.

Definition at line 436 of file thread_context.cc.

References delBp(), gem5::ArmISA::e, and getOrAllocBp().

◆ schedule()

bool gem5::Iris::ThreadContext::schedule ( PCEvent * e )

overridevirtual

Implements gem5::PCEventScope.

Definition at line 424 of file thread_context.cc.

References _instId, gem5::ArmISA::e, getOrAllocBp(), and installBp().

◆ scheduleInstCountEvent()

void gem5::Iris::ThreadContext::scheduleInstCountEvent	(	Event *	event,
		Tick	count )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 499 of file thread_context.cc.

References call(), comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, getCurrentInstCount(), and maintainStepping().

◆ semihostingEvent()

iris::IrisErrorCode gem5::Iris::ThreadContext::semihostingEvent	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out )

protected

Definition at line 313 of file thread_context.cc.

References _instId, call(), gem5::ArmSystem::callSemihosting(), gem5::curTick(), enableAfterPseudoEvent, getCpuPtr(), readIntReg(), and gem5::EventManager::schedule().

◆ sendFunctional()

void gem5::Iris::ThreadContext::sendFunctional ( PacketPtr pkt )

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 526 of file thread_context.cc.

References gem5::X86ISA::addr, data, gem5::Packet::getAddr(), getMemorySpaceId(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::Packet::isRead(), gem5::ArmISA::isSecure(), gem5::Packet::makeResponse(), gem5::Iris::PhysicalMemoryNonSecureMsn, gem5::Iris::PhysicalMemorySecureMsn, readMem(), and writeMem().

◆ setCCReg()

virtual void gem5::Iris::ThreadContext::setCCReg	(	RegIndex	reg_idx,
		RegVal	val )

inlinevirtual

Definition at line 345 of file thread_context.hh.

References setCCRegFlat(), and gem5::X86ISA::val.

Referenced by setReg().

◆ setCCRegFlat()

void gem5::Iris::ThreadContext::setCCRegFlat	(	RegIndex	idx,
		RegVal	val )

virtual

Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Definition at line 873 of file thread_context.cc.

References _instId, call(), gem5::ArmISA::ccRegClass, getCCRegFlatRscId(), panic_if, and gem5::X86ISA::val.

Referenced by setCCReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), and setReg().

◆ setContextId()

void gem5::Iris::ThreadContext::setContextId ( int id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 207 of file thread_context.hh.

References _contextId, and gem5::ArmISA::id.

◆ setHtmCheckpointPtr()

void gem5::Iris::ThreadContext::setHtmCheckpointPtr ( BaseHTMCheckpointPtr cpt )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 455 of file thread_context.hh.

References panic.

◆ setIntReg()

void gem5::Iris::ThreadContext::setIntReg	(	RegIndex	reg_idx,
		RegVal	val )

virtual

Reimplemented in gem5::fastmodel::CortexR52TC.

Definition at line 811 of file thread_context.cc.

References _instId, call(), getIntRegRscId(), and gem5::X86ISA::val.

Referenced by setReg().

◆ setIntRegFlat()

void gem5::Iris::ThreadContext::setIntRegFlat	(	RegIndex	idx,
		uint64_t	val )

virtual

Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.

Definition at line 842 of file thread_context.cc.

References _instId, call(), getIntRegFlatRscId(), gem5::ArmISA::intRegClass, panic_if, and gem5::X86ISA::val.

Referenced by setReg().

◆ setMiscReg()

void gem5::Iris::ThreadContext::setMiscReg	(	RegIndex	misc_reg,
		const RegVal	val )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 365 of file thread_context.hh.

References setMiscRegNoEffect(), and gem5::X86ISA::val.

Referenced by gem5::fastmodel::CortexA76TC::setIntRegFlat().

◆ setMiscRegNoEffect()

void gem5::Iris::ThreadContext::setMiscRegNoEffect	(	RegIndex	misc_reg,
		const RegVal	val )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 634 of file thread_context.cc.

References _instId, call(), getMiscRegRscId(), and gem5::X86ISA::val.

Referenced by setMiscReg(), and gem5::fastmodel::CortexR52TC::setMiscRegNoEffect().

◆ setProcessPtr()

void gem5::Iris::ThreadContext::setProcessPtr ( Process * p )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 238 of file thread_context.hh.

References gem5::MipsISA::p, and panic.

◆ setReg() [1/2]

void gem5::Iris::ThreadContext::setReg	(	const RegId &	reg,
		const void *	val )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 708 of file thread_context.cc.

References gem5::CCRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, gem5::X86ISA::reg, setCCReg(), setCCRegFlat(), setIntReg(), setIntRegFlat(), setVecElem(), setVecElemFlat(), setVecPredReg(), setVecPredRegFlat(), setVecReg(), setVecRegFlat(), gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ setReg() [2/2]

void gem5::Iris::ThreadContext::setReg	(	const RegId &	reg,
		RegVal	val )

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 649 of file thread_context.cc.

References gem5::X86ISA::reg, setReg(), and gem5::X86ISA::val.

Referenced by setReg().

◆ setStatus()

void gem5::Iris::ThreadContext::setStatus ( Status new_status )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 563 of file thread_context.cc.

References _instId, _status, gem5::ThreadContext::Active, call(), gem5::EventManager::deschedule(), enableAfterPseudoEvent, and getCpuPtr().

Referenced by activate(), halt(), and suspend().

◆ setStCondFailures()

void gem5::Iris::ThreadContext::setStCondFailures ( unsigned sc_failures )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 379 of file thread_context.hh.

References panic.

◆ setThreadId()

void gem5::Iris::ThreadContext::setThreadId ( int id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 204 of file thread_context.hh.

References _threadId, and gem5::ArmISA::id.

◆ setVecElem()

virtual void gem5::Iris::ThreadContext::setVecElem	(	const RegId &	reg,
		RegVal	val )

inlinevirtual

Definition at line 332 of file thread_context.hh.

References panic, gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by setReg().

◆ setVecElemFlat()

virtual void gem5::Iris::ThreadContext::setVecElemFlat	(	RegIndex	idx,
		RegVal	val )

inlinevirtual

Definition at line 418 of file thread_context.hh.

References panic, and gem5::X86ISA::val.

Referenced by setReg().

◆ setVecPredReg()

virtual void gem5::Iris::ThreadContext::setVecPredReg	(	const RegId &	reg,
		const ArmISA::VecPredRegContainer &	val )

inlinevirtual

Definition at line 338 of file thread_context.hh.

References panic, gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by setReg().

◆ setVecPredRegFlat()

virtual void gem5::Iris::ThreadContext::setVecPredRegFlat	(	RegIndex	idx,
		const ArmISA::VecPredRegContainer &	val )

inlinevirtual

Definition at line 430 of file thread_context.hh.

References panic, and gem5::X86ISA::val.

Referenced by setReg().

◆ setVecReg()

virtual void gem5::Iris::ThreadContext::setVecReg	(	const RegId &	reg,
		const ArmISA::VecRegContainer &	val )

inlinevirtual

Definition at line 326 of file thread_context.hh.

References panic, gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by setReg().

◆ setVecRegFlat()

virtual void gem5::Iris::ThreadContext::setVecRegFlat	(	RegIndex	idx,
		const ArmISA::VecRegContainer &	val )

inlinevirtual

Definition at line 407 of file thread_context.hh.

References panic, and gem5::X86ISA::val.

Referenced by setReg().

◆ simulationTimeEvent()

iris::IrisErrorCode gem5::Iris::ThreadContext::simulationTimeEvent	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out )