#include <instructions.hh>

Inheritance diagram for gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >:

Public Member Functions
	Inst_VOP3P_MAI__V_MFMA_I8 (InFmt_VOP3P_MAI *iFmt)
	~Inst_VOP3P_MAI__V_MFMA_I8 ()
int	getNumOperands () override
int	numDstRegOperands () override
int	numSrcRegOperands () override
int	getOperandSize (int opIdx) override
void	execute (GPUDynInstPtr gpuDynInst) override
Public Member Functions inherited from gem5::VegaISA::Inst_VOP3P_MAI
	Inst_VOP3P_MAI (InFmt_VOP3P_MAI *, const std::string &opcode)
	~Inst_VOP3P_MAI ()
int	instSize () const override
void	generateDisassembly () override
void	initOperandInfo () override
Public Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
	VEGAGPUStaticInst (const std::string &opcode)
	~VEGAGPUStaticInst ()
void	generateDisassembly () override
bool	isFlatScratchRegister (int opIdx) override
bool	isExecMaskRegister (int opIdx) override
void	initOperandInfo () override
int	getOperandSize (int opIdx) override
int	coalescerTokenCount () const override
	Return the number of tokens needed by the coalescer.
ScalarRegU32	srcLiteral () const override
Public Member Functions inherited from gem5::GPUStaticInst
	GPUStaticInst (const std::string &opcode)
virtual	~GPUStaticInst ()
void	instAddr (int inst_addr)
int	instAddr () const
int	nextInstAddr () const
void	instNum (int num)
int	instNum ()
void	ipdInstNum (int num)
int	ipdInstNum () const
void	initDynOperandInfo (Wavefront wf, ComputeUnit cu)
const std::string &	disassemble ()
int	numSrcVecOperands ()
int	numDstVecOperands ()
int	numSrcVecDWords ()
int	numDstVecDWords ()
int	numSrcScalarOperands ()
int	numDstScalarOperands ()
int	numSrcScalarDWords ()
int	numDstScalarDWords ()
int	maxOperandSize ()
bool	isALU () const
bool	isBranch () const
bool	isCondBranch () const
bool	isNop () const
bool	isReturn () const
bool	isEndOfKernel () const
bool	isKernelLaunch () const
bool	isSDWAInst () const
bool	isDPPInst () const
bool	isUnconditionalJump () const
bool	isSpecialOp () const
bool	isWaitcnt () const
bool	isSleep () const
bool	isBarrier () const
bool	isMemSync () const
bool	isMemRef () const
bool	isFlat () const
bool	isFlatGlobal () const
bool	isFlatScratch () const
bool	isLoad () const
bool	isStore () const
bool	isAtomic () const
bool	isAtomicNoRet () const
bool	isAtomicRet () const
bool	isScalar () const
bool	readsSCC () const
bool	writesSCC () const
bool	readsVCC () const
bool	writesVCC () const
bool	readsEXEC () const
bool	writesEXEC () const
bool	readsMode () const
bool	writesMode () const
bool	ignoreExec () const
bool	isAtomicAnd () const
bool	isAtomicOr () const
bool	isAtomicXor () const
bool	isAtomicCAS () const
bool	isAtomicExch () const
bool	isAtomicAdd () const
bool	isAtomicSub () const
bool	isAtomicInc () const
bool	isAtomicDec () const
bool	isAtomicMax () const
bool	isAtomicMin () const
bool	isArgLoad () const
bool	isGlobalMem () const
bool	isLocalMem () const
bool	isArgSeg () const
bool	isGlobalSeg () const
bool	isGroupSeg () const
bool	isKernArgSeg () const
bool	isPrivateSeg () const
bool	isReadOnlySeg () const
bool	isSpillSeg () const
bool	isGloballyCoherent () const
	Coherence domain of a memory instruction.
bool	isSystemCoherent () const
bool	isI8 () const
bool	isF16 () const
bool	isF32 () const
bool	isF64 () const
bool	isFMA () const
bool	isMAC () const
bool	isMAD () const
bool	isMFMA () const
bool	hasNoAddr () const
virtual void	initiateAcc (GPUDynInstPtr gpuDynInst)
virtual void	completeAcc (GPUDynInstPtr gpuDynInst)
virtual uint32_t	getTargetPc ()
void	setFlag (Flags flag)
const std::string &	opcode () const
const std::vector< OperandInfo > &	srcOperands () const
const std::vector< OperandInfo > &	dstOperands () const
const std::vector< OperandInfo > &	srcVecRegOperands () const
const std::vector< OperandInfo > &	dstVecRegOperands () const
const std::vector< OperandInfo > &	srcScalarRegOperands () const
const std::vector< OperandInfo > &	dstScalarRegOperands () const

Private Types
using	DT = int8_t

Static Private Attributes
static constexpr int	DT_bits = sizeof(DT) * 8
static constexpr int	gpr_ratio = 32 / DT_bits
static constexpr int	gprs_a = M * K * B / (64 * gpr_ratio)
static constexpr int	gprs_b = K * N * B / (64 * gpr_ratio)
static constexpr int	gprs_c_d = M * N * B / 64

Additional Inherited Members
Public Types inherited from gem5::GPUStaticInst
enum	OpType { SRC_VEC , SRC_SCALAR , DST_VEC , DST_SCALAR }
typedef int(RegisterManager::*	MapRegFn) (Wavefront *, int)
Public Attributes inherited from gem5::GPUStaticInst
enums::StorageClassType	executed_as
Static Public Attributes inherited from gem5::GPUStaticInst
static uint64_t	dynamic_id_count
Protected Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
void	panicUnimplemented () const
Protected Attributes inherited from gem5::VegaISA::Inst_VOP3P_MAI
InFmt_VOP3P_MAI	instData
InFmt_VOP3P_MAI_1	extData
Protected Attributes inherited from gem5::VegaISA::VEGAGPUStaticInst
ScalarRegU32	_srcLiteral
	if the instruction has a src literal - an immediate value that is part of the instruction stream - we store that here
Protected Attributes inherited from gem5::GPUStaticInst
const std::string	_opcode
std::string	disassembly
int	_instNum
int	_instAddr
std::vector< OperandInfo >	srcOps
std::vector< OperandInfo >	dstOps

Detailed Description

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>
class gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >

Definition at line 44683 of file instructions.hh.

Member Typedef Documentation

◆ DT

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

using gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::DT = int8_t

private

Definition at line 44688 of file instructions.hh.

Constructor & Destructor Documentation

◆ Inst_VOP3P_MAI__V_MFMA_I8()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::Inst_VOP3P_MAI__V_MFMA_I8 ( InFmt_VOP3P_MAI * iFmt )

inline

Definition at line 44700 of file instructions.hh.

◆ ~Inst_VOP3P_MAI__V_MFMA_I8()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::~Inst_VOP3P_MAI__V_MFMA_I8 ( )

inline

Definition at line 44707 of file instructions.hh.

Member Function Documentation

◆ execute()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

void gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::execute ( GPUDynInstPtr gpuDynInst )

inlineoverridevirtual

Implements gem5::GPUStaticInst.

Definition at line 44733 of file instructions.hh.

◆ getNumOperands()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::getNumOperands ( )

inlineoverridevirtual

Implements gem5::GPUStaticInst.

Definition at line 44709 of file instructions.hh.

◆ getOperandSize()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::getOperandSize ( int opIdx )

inlineoverridevirtual

Implements gem5::GPUStaticInst.

Definition at line 44716 of file instructions.hh.

◆ numDstRegOperands()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::numDstRegOperands ( )

inlineoverridevirtual

Implements gem5::GPUStaticInst.

Definition at line 44713 of file instructions.hh.

Referenced by gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< 16, 16, 16, 1, &MNEM__V_MFMA_I32_16X16X16_I8 >::getNumOperands().

◆ numSrcRegOperands()

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::numSrcRegOperands ( )

inlineoverridevirtual

Implements gem5::GPUStaticInst.

Definition at line 44714 of file instructions.hh.

Referenced by gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< 16, 16, 16, 1, &MNEM__V_MFMA_I32_16X16X16_I8 >::getNumOperands().

Member Data Documentation

◆ DT_bits

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::DT_bits = sizeof(DT) * 8

staticconstexprprivate

Definition at line 44689 of file instructions.hh.

◆ gpr_ratio

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::gpr_ratio = 32 / DT_bits

staticconstexprprivate

Definition at line 44692 of file instructions.hh.

◆ gprs_a

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::gprs_a = M * K * B / (64 * gpr_ratio)

staticconstexprprivate

Definition at line 44693 of file instructions.hh.

◆ gprs_b

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::gprs_b = K * N * B / (64 * gpr_ratio)

staticconstexprprivate

Definition at line 44694 of file instructions.hh.

◆ gprs_c_d

template<const int M, const int N, const int K, const int B, const char ** MNEMONIC>

int gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::gprs_c_d = M * N * B / 64

staticconstexprprivate

Definition at line 44697 of file instructions.hh.

The documentation for this class was generated from the following file:

arch/amdgpu/vega/insts/instructions.hh

Public Member Functions

Private Types

Static Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ DT

Constructor & Destructor Documentation

◆ Inst_VOP3P_MAI__V_MFMA_I8()

◆ ~Inst_VOP3P_MAI__V_MFMA_I8()

Member Function Documentation

◆ execute()

◆ getNumOperands()

◆ getOperandSize()

◆ numDstRegOperands()

◆ numSrcRegOperands()

Member Data Documentation

◆ DT_bits

◆ gpr_ratio

◆ gprs_a

◆ gprs_b

◆ gprs_c_d