vector.hh File Reference

#include <string>
#include "arch/riscv/faults.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/regs/misc.hh"
#include "arch/riscv/utility.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"

Go to the source code of this file.

Classes
class	gem5::RiscvISA::VConfOp
	Base class for Vector Config operations. More...
class	gem5::RiscvISA::VectorNonSplitInst
class	gem5::RiscvISA::VectorMacroInst
class	gem5::RiscvISA::VectorMicroInst
class	gem5::RiscvISA::VectorNopMicroInst
class	gem5::RiscvISA::VectorArithMicroInst
class	gem5::RiscvISA::VectorArithMacroInst
class	gem5::RiscvISA::VectorVMUNARY0MicroInst
class	gem5::RiscvISA::VectorVMUNARY0MacroInst
class	gem5::RiscvISA::VectorSlideMacroInst
class	gem5::RiscvISA::VectorSlideMicroInst
class	gem5::RiscvISA::VectorMemMicroInst
class	gem5::RiscvISA::VectorMemMacroInst
class	gem5::RiscvISA::VleMacroInst
class	gem5::RiscvISA::VseMacroInst
class	gem5::RiscvISA::VleMicroInst
class	gem5::RiscvISA::VseMicroInst
class	gem5::RiscvISA::VlWholeMacroInst
class	gem5::RiscvISA::VlWholeMicroInst
class	gem5::RiscvISA::VsWholeMacroInst
class	gem5::RiscvISA::VsWholeMicroInst
class	gem5::RiscvISA::VlElementMacroInst
class	gem5::RiscvISA::VlElementMicroInst
class	gem5::RiscvISA::VsElementMacroInst
class	gem5::RiscvISA::VsElementMicroInst
class	gem5::RiscvISA::VlIndexMacroInst
class	gem5::RiscvISA::VlIndexMicroInst
class	gem5::RiscvISA::VsIndexMacroInst
class	gem5::RiscvISA::VsIndexMicroInst
class	gem5::RiscvISA::VMvWholeMacroInst
class	gem5::RiscvISA::VMvWholeMicroInst
class	gem5::RiscvISA::VMaskMergeMicroInst
class	gem5::RiscvISA::VxsatMicroInst
class	gem5::RiscvISA::VlFFTrimVlMicroOp
class	gem5::RiscvISA::VlSegMacroInst
class	gem5::RiscvISA::VlSegMicroInst
class	gem5::RiscvISA::VlSegDeIntrlvMicroInst
class	gem5::RiscvISA::VsSegMacroInst
class	gem5::RiscvISA::VsSegMicroInst
class	gem5::RiscvISA::VsSegIntrlvMicroInst
class	gem5::RiscvISA::VCpyVsMicroInst
class	gem5::RiscvISA::VPinVdMicroInst

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::RiscvISA

Functions
float	gem5::RiscvISA::getVflmul (uint32_t vlmul_encoding)
	This function translates the 3-bit value of vlmul bits to the corresponding lmul value as specified in RVV 1.0 spec p11-12 chapter 3.4.2.
uint32_t	gem5::RiscvISA::getSew (uint32_t vsew)
uint32_t	gem5::RiscvISA::getVlmax (VTYPE vtype, uint32_t vlen)
uint32_t	gem5::RiscvISA::get_emul (uint32_t eew, uint32_t sew, float vflmul, bool is_mask_ldst)
uint8_t	gem5::RiscvISA::checked_vtype (bool vill, uint8_t vtype)