gem5 v25.0.0.1
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pagetable_walker.hh
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1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2020 Barkhausen Institut
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#ifndef __ARCH_RISCV_TABLE_WALKER_HH__
40#define __ARCH_RISCV_TABLE_WALKER_HH__
41
42#include <vector>
43
44#include "arch/generic/mmu.hh"
47#include "arch/riscv/pmp.hh"
48#include "arch/riscv/tlb.hh"
49#include "base/statistics.hh"
50#include "base/types.hh"
51#include "mem/packet.hh"
52#include "params/RiscvPagetableWalker.hh"
53#include "sim/clocked_object.hh"
54#include "sim/faults.hh"
55#include "sim/system.hh"
56
57namespace gem5
58{
59
60class ThreadContext;
61
62namespace RiscvISA
63{
64 class Walker : public ClockedObject
65 {
66 protected:
67 // Port for accessing memory
68 class WalkerPort : public RequestPort
69 {
70 public:
71 WalkerPort(const std::string &_name, Walker * _walker) :
72 RequestPort(_name), walker(_walker)
73 {}
74
75 protected:
77
78 bool recvTimingResp(PacketPtr pkt);
79 void recvReqRetry();
80 };
81
82 friend class WalkerPort;
84
85 // State to track each walk of the page table
87 {
88 friend class Walker;
89 private:
90
91 struct WalkFlags
92 {
93 bool doEndWalk = false;
94 bool doTLBInsert = false;
95 bool doWrite = false;
96 bool pteIsLeaf = false;
97 };
98
105
112
113 protected:
122 int level;
124 unsigned inflight;
134 SATP satp;
135 SATP hgatp;
136 STATUS status;
139 bool timing;
143 public:
144 WalkerState(Walker * _walker, BaseMMU::Translation *_translation,
145 const RequestPtr &_req, bool _isFunctional = false) :
146 walker(_walker), req(_req), state(Ready),
147 nextState(Ready), level(0), glevel(0), inflight(0),
148 translation(_translation),
149 functional(_isFunctional), timing(false),
150 retrying(false), started(false), squashed(false)
151 {
152 }
153 void initState(ThreadContext * _tc, BaseMMU::Mode _mode,
154 bool _isTiming = false);
155
156 Fault walk();
157 Fault startFunctional(Addr &addr, unsigned &logBytes);
158 bool recvPacket(PacketPtr pkt);
159 unsigned numInflight() const;
160 bool isRetrying();
161 bool wasStarted();
162 bool isTiming();
163 void retry();
164 void squash();
165 std::string name() const {return walker->name();}
166
167 private:
169 PTESv39 pte, WalkFlags& stepWalkFlags, int level);
171 Fault stepWalk(PacketPtr &write);
173 Fault walkGStage(Addr guest_paddr, Addr& host_paddr);
176 void sendPackets();
177 void endWalk();
180 PacketPtr createReqPacket(Addr paddr, MemCmd cmd, size_t bytes);
181 };
182
183 friend class WalkerState;
184 // State for timing and atomic accesses (need multiple per walker in
185 // the case of multiple outstanding requests in timing mode)
187 // State for functional accesses (only need one of these per walker)
189
191 {
194 senderWalk(_senderWalk) {}
195 };
196
197 public:
198 // Kick off the state machine.
199 Fault start(ThreadContext * _tc, BaseMMU::Translation *translation,
200 const RequestPtr &req, BaseMMU::Mode mode,
201 TlbEntry* result_entry = nullptr);
203 unsigned &logBytes, BaseMMU::Mode mode);
204 Port &getPort(const std::string &if_name,
205 PortID idx=InvalidPortID) override;
206
207 protected:
208 // The TLB we're supposed to load.
214
215 // The number of outstanding walks that can be squashed per cycle.
217
218 // Wrapper for checking for squashes before starting a translation.
219 void startWalkWrapper();
220
225
226 // Functions for dealing with packets.
227 bool recvTimingResp(PacketPtr pkt);
228 void recvReqRetry();
229 bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
230
240
241
242 public:
243
244 void setTLB(TLB * _tlb)
245 {
246 tlb = _tlb;
247 }
248
249 using Params = RiscvPagetableWalkerParams;
250
252 ClockedObject(params), port(name() + ".port", this),
253 funcState(this, NULL, NULL, true), tlb(NULL), sys(params.system),
254 pma(params.pma_checker),
255 pmp(params.pmp),
256 requestorId(sys->getRequestorId(this)),
257 numSquashable(params.num_squash_per_cycle),
259 pagewalkerstats(this)
260 {
261 }
262 };
263
264} // namespace RiscvISA
265} // namespace gem5
266
267#endif // __ARCH_RISCV_PAGE_TABLE_WALKER_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
ClockedObject(const ClockedObjectParams &p)
const std::string _name
Definition named.hh:54
virtual std::string name() const
Definition named.hh:60
Ports are used to interface objects to each other.
Definition port.hh:62
RequestPort(const std::string &name, SimObject *_owner, PortID id=InvalidPortID)
Request port.
Definition port.cc:125
Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the...
This class helps to implement RISCV's physical memory protection (pmp) primitive.
Definition pmp.hh:58
WalkerPort(const std::string &_name, Walker *_walker)
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Fault startFunctional(Addr &addr, unsigned &logBytes)
PacketPtr createReqPacket(Addr paddr, MemCmd cmd, size_t bytes)
Fault checkPTEPermissions(PTESv39 pte, WalkFlags &stepWalkFlags, int level)
WalkerState(Walker *_walker, BaseMMU::Translation *_translation, const RequestPtr &_req, bool _isFunctional=false)
Fault walkGStage(Addr guest_paddr, Addr &host_paddr)
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseMMU::Mode mode)
EventFunctionWrapper startWalkWrapperEvent
Event used to call startWalkWrapper.
Fault start(ThreadContext *_tc, BaseMMU::Translation *translation, const RequestPtr &req, BaseMMU::Mode mode, TlbEntry *result_entry=nullptr)
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
bool sendTiming(WalkerState *sendingState, PacketPtr pkt)
gem5::RiscvISA::Walker::PagewalkerStats pagewalkerstats
bool recvTimingResp(PacketPtr pkt)
std::list< WalkerState * > currStates
RiscvPagetableWalkerParams Params
Walker(const Params &params)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Statistics container.
Definition group.hh:93
This is a simple scalar statistic, like a counter.
STL list class.
Definition stl.hh:51
STL vector class.
Definition stl.hh:37
ClockedObject declaration and implementation.
virtual void initState()
initState() is called on each SimObject when not restoring from a checkpoint.
Definition sim_object.cc:91
const Params & params() const
Bitfield< 15 > system
Definition misc.hh:1032
Bitfield< 20 > level
Definition intmessage.hh:51
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
const PortID InvalidPortID
Definition types.hh:246
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint16_t RequestorID
Definition request.hh:95
Packet * PacketPtr
Declaration of the Packet class.
PMP header file.
Declaration of Statistics objects.
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition packet.hh:469

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