tlb.hh

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/*
 * Copyright (c) 2001-2005 The Regents of The University of Michigan
 * Copyright (c) 2007 MIPS Technologies, Inc.
 * Copyright (c) 2020 Barkhausen Institut
 * Copyright (c) 2021 Huawei International
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __ARCH_RISCV_TLB_HH__
#define __ARCH_RISCV_TLB_HH__
 
#include <list>
 
#include "arch/generic/tlb.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pma_checker.hh"
#include "arch/riscv/regs/misc.hh"
#include "arch/riscv/utility.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/RiscvTLB.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
class ThreadContext;
 
/* To maintain compatibility with other architectures, we'll
   simply create an ITLB and DTLB that will point to the real TLB */
namespace RiscvISA {
 
class MemAccessInfo
{
  public:
    PrivilegeMode priv;
    bool virt;
    bool force_virt;
    bool hlvx;
    bool lr;
 
    MemAccessInfo() = default;
    MemAccessInfo(
      PrivilegeMode priv, bool virt, bool force_virt, bool hlvx, bool lr) :
      priv(priv), virt(virt), force_virt(force_virt), hlvx(hlvx), lr(lr) {}
 
    bool
    bypassTLB() const
    {
        return (force_virt || hlvx);
    }
};
 
enum XlateStage
{
  FIRST_STAGE,
  GSTAGE
};
 
class Walker;
 
class TLB : public BaseTLB
{
    typedef std::list<TlbEntry *> EntryList;
 
  protected:
    size_t size;
    std::vector<TlbEntry> tlb;  // our TLB
    TlbEntryTrie trie;          // for quick access
    EntryList freeList;         // free entries
    uint64_t lruSeq;
 
    Walker *walker;
 
    struct TlbStats : public statistics::Group
    {
        TlbStats(statistics::Group *parent);
 
        statistics::Scalar readHits;
        statistics::Scalar readMisses;
        statistics::Scalar readAccesses;
        statistics::Scalar writeHits;
        statistics::Scalar writeMisses;
        statistics::Scalar writeAccesses;
 
        statistics::Formula hits;
        statistics::Formula misses;
        statistics::Formula accesses;
    } stats;
 
  public:
    BasePMAChecker *pma;
    PMP *pmp;
 
  public:
    typedef RiscvTLBParams Params;
    TLB(const Params &p);
 
    Walker *getWalker();
 
    void takeOverFrom(BaseTLB *old) override {}

    TlbEntry *insert(Addr vpn, const TlbEntry &entry);
    void flushAll() override;
    void demapPage(Addr vaddr, uint64_t asn) override;
 
    Fault checkPermissions(ThreadContext* tc, MemAccessInfo mem_access,
                            Addr vaddr, BaseMMU::Mode mode, PTESv39 pte,
                            Addr gvaddr = 0x0,
                            XlateStage stage = XlateStage::FIRST_STAGE);
 
    Fault createPagefault(Addr vaddr, BaseMMU::Mode mode, Addr gvaddr = 0x0,
                          bool gpf = false, bool virt = false);
 
    MemAccessInfo getMemAccessInfo(ThreadContext *tc, BaseMMU::Mode mode,
                                  const Request::ArchFlagsType arch_flags);
 
    // Checkpointing
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

    Port *getTableWalkerPort() override;
 
    Addr hiddenTranslateWithTLB(Addr vaddr, uint16_t asid, Addr xmode,
                                BaseMMU::Mode mode);
 
    Fault translateAtomic(const RequestPtr &req,
                          ThreadContext *tc, BaseMMU::Mode mode) override;
    void translateTiming(const RequestPtr &req, ThreadContext *tc,
                         BaseMMU::Translation *translation,
                         BaseMMU::Mode mode) override;
    Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
                              BaseMMU::Mode mode) override;
    Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc,
                           BaseMMU::Mode mode) const override;
 
    Addr
    getValidAddr(Addr vaddr, ThreadContext *tc, BaseMMU::Mode mode)
    {
        ISA* isa = static_cast<ISA*>(tc->getIsaPtr());
        if (isa->rvType() == RV32) {
            return bits(vaddr, 31, 0);
        }
        return vaddr;
    }

    TlbEntry *lookup(Addr vpn, uint16_t asid, BaseMMU::Mode mode, bool hidden);
 
  private:
    uint64_t nextSeq() { return ++lruSeq; }
 
    void evictLRU();
    void remove(size_t idx);
 
    Fault translate(const RequestPtr &req, ThreadContext *tc,
                    BaseMMU::Translation *translation, BaseMMU::Mode mode,
                    bool &delayed);
    Fault doTranslate(const RequestPtr &req, ThreadContext *tc,
                      BaseMMU::Translation *translation, BaseMMU::Mode mode,
                      bool &delayed);
};
 
} // namespace RiscvISA
} // namespace gem5
 
#endif // __RISCV_MEMORY_HH__