vector.cc File Reference

#include "arch/riscv/insts/vector.hh"
#include <sstream>
#include <string>
#include "arch/riscv/insts/static_inst.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/regs/misc.hh"
#include "arch/riscv/regs/vector.hh"
#include "arch/riscv/utility.hh"
#include "cpu/static_inst.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::RiscvISA

Functions
float	gem5::RiscvISA::getVflmul (uint32_t vlmul_encoding)
	This function translates the 3-bit value of vlmul bits to the corresponding lmul value as specified in RVV 1.0 spec p11-12 chapter 3.4.2.
uint32_t	gem5::RiscvISA::getVlmax (VTYPE vtype, uint32_t vlen)