zcmt.hh

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#ifndef __ARCH_RISCV_INSTS_ZCMT_HH__
#define __ARCH_RISCV_INSTS_ZCMT_HH__
 
#include <string>
 
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
class ZcmtSecondFetchInst : public RiscvStaticInst
{
  private:
    RegId srcRegIdxArr[0];
    RegId destRegIdxArr[0];
    Addr jvtEntry;
 
  public:
    ZcmtSecondFetchInst(ExtMachInst machInst, Addr entry);
    Fault execute(ExecContext *, trace::InstRecord *) const override;
 
    std::string
    generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const override;
 
    std::unique_ptr<PCStateBase> branchTarget(
        const PCStateBase &branch_pc) const override;
 
    using StaticInst::branchTarget;
};
 
} // namespace RiscvISA
} // namespace gem5
 
#endif // __ARCH_RISCV_INSTS_ZCMT_HH__