gem5 v25.0.0.1
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Public Member Functions | Public Attributes | Protected Member Functions | List of all members
gem5::RiscvISA::RiscvStaticInst Class Reference

Base class for all RISC-V static instructions. More...

#include <static_inst.hh>

Inheritance diagram for gem5::RiscvISA::RiscvStaticInst:
gem5::StaticInst gem5::RefCounted gem5::RiscvISA::BSOp gem5::RiscvISA::CSROp gem5::RiscvISA::CompRegOp gem5::RiscvISA::ImmOp< I > gem5::RiscvISA::MemInst gem5::RiscvISA::PseudoOp gem5::RiscvISA::RegOp gem5::RiscvISA::RiscvMacroInst gem5::RiscvISA::RiscvMicroInst gem5::RiscvISA::SystemOp gem5::RiscvISA::Unknown gem5::RiscvISA::VConfOp gem5::RiscvISA::VectorNonSplitInst gem5::RiscvISA::ZcmtSecondFetchInst

Public Member Functions

void advancePC (PCStateBase &pc) const override
void advancePC (ThreadContext *tc) const override
uint64_t getEMI () const override
std::unique_ptr< PCStateBase > buildRetPC (const PCStateBase &cur_pc, const PCStateBase &call_pc) const override
size_t asBytes (void *buf, size_t size) override
 Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.
Public Member Functions inherited from gem5::StaticInst
uint8_t numSrcRegs () const
 Number of source registers.
uint8_t numDestRegs () const
 Number of destination registers.
uint8_t numDestRegs (RegClassType type) const
 Number of destination registers of a particular type.
bool isNop () const
bool isMemRef () const
bool isLoad () const
bool isStore () const
bool isAtomic () const
bool isStoreConditional () const
bool isInstPrefetch () const
bool isDataPrefetch () const
bool isPrefetch () const
bool isInteger () const
bool isFloating () const
bool isVector () const
bool isMatrix () const
bool isControl () const
bool isCall () const
bool isReturn () const
bool isDirectCtrl () const
bool isIndirectCtrl () const
bool isCondCtrl () const
bool isUncondCtrl () const
bool isSerializing () const
bool isSerializeBefore () const
bool isSerializeAfter () const
bool isSquashAfter () const
bool isFullMemBarrier () const
bool isReadBarrier () const
bool isWriteBarrier () const
bool isNonSpeculative () const
bool isQuiesce () const
bool isUnverifiable () const
bool isPseudo () const
bool isSyscall () const
bool isMacroop () const
bool isMicroop () const
bool isDelayedCommit () const
bool isLastMicroop () const
bool isFirstMicroop () const
bool isHtmStart () const
bool isHtmStop () const
bool isHtmCancel () const
bool isInvalid () const
bool isHtmCmd () const
void setFirstMicroop ()
void setLastMicroop ()
void setDelayedCommit ()
void setFlag (Flags f)
OpClass opClass () const
 Operation class. Used to select appropriate function unit in issue.
const RegId & destRegIdx (int i) const
 Return logical index (architectural reg num) of i'th destination reg.
void setDestRegIdx (int i, const RegId &val)
const RegId & srcRegIdx (int i) const
 Return logical index (architectural reg num) of i'th source reg.
void setSrcRegIdx (int i, const RegId &val)
virtual ~StaticInst ()
virtual Fault execute (ExecContext *xc, trace::InstRecord *traceData) const =0
virtual Fault initiateAcc (ExecContext *xc, trace::InstRecord *traceData) const
virtual Fault completeAcc (Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) const
size_t size () const
virtual void size (size_t newSize)
virtual StaticInstPtr fetchMicroop (MicroPC upc) const
 Return the microop that goes with a particular micropc.
virtual std::unique_ptr< PCStateBase > branchTarget (const PCStateBase &pc) const
 Return the target address for a PC-relative branch.
virtual std::unique_ptr< PCStateBase > branchTarget (ThreadContext *tc) const
 Return the target address for an indirect branch (jump).
virtual const std::string & disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const
 Return string representation of disassembled instruction.
void printFlags (std::ostream &outs, const std::string &separator) const
 Print a separator separated list of this instruction's set flag names on the given stream.
std::string getName ()
 Return name of machine instruction.
Public Member Functions inherited from gem5::RefCounted
 RefCounted ()
 We initialize the reference count to zero and the first object to take ownership of it must increment it to one.
virtual ~RefCounted ()
 We make the destructor virtual because we're likely to have virtual functions on reference counted objects.
void incref () const
 Increment the reference count.
void decref () const
 Decrement the reference count and destroy the object if all references are gone.

Public Attributes

ExtMachInst machInst

Protected Member Functions

 RiscvStaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
template<typename T>
T rvSelect (T v32, T v64) const
template<typename T32, typename T64>
T64 rvExt (T64 x) const
uint64_t rvZext (uint64_t x) const
int64_t rvSext (int64_t x) const
void setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest)
 Set the pointers which point to the arrays of source and destination register indices.
virtual std::string generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const =0
 Internal function to generate disassembly string.
 StaticInst (const char *_mnemonic, OpClass op_class)
 Constructor.
template<typename T>
size_t simpleAsBytes (void *buf, size_t max_size, const T &t)

Additional Inherited Members

Public Types inherited from gem5::StaticInst
using RegIdArrayPtr = RegId (StaticInst:: *)[]
static StaticInstPtr nullStaticInstPtr
 Pointer to a statically allocated "null" instruction object.
Protected Attributes inherited from gem5::StaticInst
std::bitset< Num_Flags > flags
 Flag values for this instruction.
OpClass _opClass
 See opClass().
uint8_t _numSrcRegs = 0
 See numSrcRegs().
uint8_t _numDestRegs = 0
 See numDestRegs().
std::array< uint8_t, MiscRegClass+1 > _numTypedDestRegs = {}
size_t _size = 0
 Instruction size in bytes.
const char * mnemonic
 Base mnemonic (e.g., "add").
std::unique_ptr< std::string > cachedDisassembly
 String representation of disassembly (lazily evaluated via disassemble()).

Detailed Description

Base class for all RISC-V static instructions.

Definition at line 52 of file static_inst.hh.

Constructor & Destructor Documentation

◆ RiscvStaticInst()

gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst ( const char * _mnemonic,
ExtMachInst _machInst,
OpClass __opClass )
inlineprotected

Definition at line 55 of file static_inst.hh.

References machInst, and gem5::StaticInst::StaticInst().

Referenced by gem5::RiscvISA::BSOp::BSOp(), gem5::RiscvISA::CSROp::CSROp(), gem5::RiscvISA::ImmOp< I >::ImmOp(), gem5::RiscvISA::MemInst::MemInst(), gem5::RiscvISA::RiscvMacroInst::RiscvMacroInst(), gem5::RiscvISA::RiscvMicroInst::RiscvMicroInst(), gem5::RiscvISA::Unknown::Unknown(), gem5::RiscvISA::VConfOp::VConfOp(), gem5::RiscvISA::VectorNonSplitInst::VectorNonSplitInst(), and gem5::RiscvISA::ZcmtSecondFetchInst::ZcmtSecondFetchInst().

Member Function Documentation

◆ advancePC() [1/2]

void gem5::RiscvISA::RiscvStaticInst::advancePC ( PCStateBase & pc) const
inlineoverridevirtual

Implements gem5::StaticInst.

Definition at line 76 of file static_inst.hh.

References gem5::RiscvISA::pc.

◆ advancePC() [2/2]

void gem5::RiscvISA::RiscvStaticInst::advancePC ( ThreadContext * tc) const
inlineoverridevirtual

Reimplemented from gem5::StaticInst.

Definition at line 82 of file static_inst.hh.

References gem5::PCStateBase::as(), gem5::RiscvISA::pc, and gem5::ThreadContext::pcState().

◆ asBytes()

size_t gem5::RiscvISA::RiscvStaticInst::asBytes ( void * buf,
size_t max_size )
inlineoverridevirtual

Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst.

buf is a buffer to hold the bytes. max_size is the size allocated for that buffer by the caller. The return value is how much data was actually put into the buffer, zero if no data was put in the buffer, or the necessary size of the buffer if there wasn't enough space.

Reimplemented from gem5::StaticInst.

Definition at line 102 of file static_inst.hh.

References machInst, gem5::StaticInst::simpleAsBytes(), and gem5::StaticInst::size().

◆ buildRetPC()

std::unique_ptr< PCStateBase > gem5::RiscvISA::RiscvStaticInst::buildRetPC ( const PCStateBase & cur_pc,
const PCStateBase & call_pc ) const
inlineoverridevirtual

Reimplemented from gem5::StaticInst.

Definition at line 92 of file static_inst.hh.

References gem5::GenericISA::SimplePCState< InstWidth >::advance(), gem5::PCStateBase::as(), and gem5::PCStateBase::clone().

◆ getEMI()

uint64_t gem5::RiscvISA::RiscvStaticInst::getEMI ( ) const
inlineoverridevirtual

Reimplemented from gem5::StaticInst.

Definition at line 89 of file static_inst.hh.

References machInst.

◆ rvExt()

template<typename T32, typename T64>
T64 gem5::RiscvISA::RiscvStaticInst::rvExt ( T64 x) const
inlineprotected

Definition at line 68 of file static_inst.hh.

References rvSelect(), and gem5::RiscvISA::x.

Referenced by rvSext(), and rvZext().

◆ rvSelect()

template<typename T>
T gem5::RiscvISA::RiscvStaticInst::rvSelect ( T v32,
T v64 ) const
inlineprotected

Definition at line 62 of file static_inst.hh.

References machInst, and gem5::RiscvISA::RV32.

Referenced by rvExt().

◆ rvSext()

int64_t gem5::RiscvISA::RiscvStaticInst::rvSext ( int64_t x) const
inlineprotected

Definition at line 70 of file static_inst.hh.

References rvExt(), and gem5::RiscvISA::x.

Referenced by gem5::RiscvISA::ZcmtSecondFetchInst::branchTarget(), gem5::RiscvISA::ZcmtSecondFetchInst::execute(), and gem5::RiscvISA::ZcmtSecondFetchInst::generateDisassembly().

◆ rvZext()

uint64_t gem5::RiscvISA::RiscvStaticInst::rvZext ( uint64_t x) const
inlineprotected

Definition at line 69 of file static_inst.hh.

References rvExt(), and gem5::RiscvISA::x.

Member Data Documentation

◆ machInst

ExtMachInst gem5::RiscvISA::RiscvStaticInst::machInst

Definition at line 73 of file static_inst.hh.

Referenced by asBytes(), gem5::RiscvISA::CmMacroInst::CmMacroInst(), gem5::RiscvISA::Unknown::execute(), gem5::RiscvISA::VCpyVsMicroInst::execute(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::RiscvISA::VlSegDeIntrlvMicroInst::execute(), gem5::RiscvISA::VPinVdMicroInst::execute(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::MemFenceMicro::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::Unknown::generateDisassembly(), gem5::RiscvISA::VectorArithMacroInst::generateDisassembly(), gem5::RiscvISA::VectorArithMicroInst::generateDisassembly(), gem5::RiscvISA::VectorNonSplitInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMacroInst::generateDisassembly(), gem5::RiscvISA::VectorSlideMicroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MacroInst::generateDisassembly(), gem5::RiscvISA::VectorVMUNARY0MicroInst::generateDisassembly(), gem5::RiscvISA::VlElementMacroInst::generateDisassembly(), gem5::RiscvISA::VlElementMicroInst::generateDisassembly(), gem5::RiscvISA::VleMacroInst::generateDisassembly(), gem5::RiscvISA::VleMicroInst::generateDisassembly(), gem5::RiscvISA::VlIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VlIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VlSegMacroInst::generateDisassembly(), gem5::RiscvISA::VlSegMicroInst::generateDisassembly(), gem5::RiscvISA::VPinVdMicroInst::generateDisassembly(), gem5::RiscvISA::VsElementMacroInst::generateDisassembly(), gem5::RiscvISA::VsElementMicroInst::generateDisassembly(), gem5::RiscvISA::VseMacroInst::generateDisassembly(), gem5::RiscvISA::VseMicroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMacroInst::generateDisassembly(), gem5::RiscvISA::VsIndexMicroInst::generateDisassembly(), gem5::RiscvISA::VsSegMacroInst::generateDisassembly(), gem5::RiscvISA::VsSegMicroInst::generateDisassembly(), getEMI(), gem5::RiscvISA::CmMacroInst::getRlistStr(), RiscvStaticInst(), rvSelect(), gem5::RiscvISA::CmMacroInst::stackAdj(), and gem5::RiscvISA::ZcmtSecondFetchInst::ZcmtSecondFetchInst().

The documentation for this class was generated from the following file:
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