gem5  v21.0.1.0
remote_gdb.cc
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1 /*
2  * Copyright (c) 2021 Huawei International
3  * Copyright 2015 LabWare
4  * Copyright 2014 Google, Inc.
5  * Copyright (c) 2010 ARM Limited
6  * Copyright (c) 2020 Barkhausen Institut
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9  * The license below extends only to copyright in the software and shall
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16  * modified or unmodified, in source code or in binary form.
17  *
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21  *
22  * Redistribution and use in source and binary forms, with or without
23  * modification, are permitted provided that the following conditions are
24  * met: redistributions of source code must retain the above copyright
25  * notice, this list of conditions and the following disclaimer;
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28  * documentation and/or other materials provided with the distribution;
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31  * this software without specific prior written permission.
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39  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44  */
45 
46 /*
47  * Copyright (c) 1990, 1993 The Regents of the University of California
48  * All rights reserved
49  *
50  * This software was developed by the Computer Systems Engineering group
51  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
52  * contributed to Berkeley.
53  *
54  * All advertising materials mentioning features or use of this software
55  * must display the following acknowledgement:
56  * This product includes software developed by the University of
57  * California, Lawrence Berkeley Laboratories.
58  *
59  * Redistribution and use in source and binary forms, with or without
60  * modification, are permitted provided that the following conditions
61  * are met:
62  * 1. Redistributions of source code must retain the above copyright
63  * notice, this list of conditions and the following disclaimer.
64  * 2. Redistributions in binary form must reproduce the above copyright
65  * notice, this list of conditions and the following disclaimer in the
66  * documentation and/or other materials provided with the distribution.
67  * 3. All advertising materials mentioning features or use of this software
68  * must display the following acknowledgement:
69  * This product includes software developed by the University of
70  * California, Berkeley and its contributors.
71  * 4. Neither the name of the University nor the names of its contributors
72  * may be used to endorse or promote products derived from this software
73  * without specific prior written permission.
74  *
75  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85  * SUCH DAMAGE.
86  *
87  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
88  */
89 
90 /*-
91  * Copyright (c) 2001 The NetBSD Foundation, Inc.
92  * All rights reserved.
93  *
94  * This code is derived from software contributed to The NetBSD Foundation
95  * by Jason R. Thorpe.
96  *
97  * Redistribution and use in source and binary forms, with or without
98  * modification, are permitted provided that the following conditions
99  * are met:
100  * 1. Redistributions of source code must retain the above copyright
101  * notice, this list of conditions and the following disclaimer.
102  * 2. Redistributions in binary form must reproduce the above copyright
103  * notice, this list of conditions and the following disclaimer in the
104  * documentation and/or other materials provided with the distribution.
105  * 3. All advertising materials mentioning features or use of this software
106  * must display the following acknowledgement:
107  * This product includes software developed by the NetBSD
108  * Foundation, Inc. and its contributors.
109  * 4. Neither the name of The NetBSD Foundation nor the names of its
110  * contributors may be used to endorse or promote products derived
111  * from this software without specific prior written permission.
112  *
113  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
114  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
115  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
116  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
117  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
118  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
119  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
120  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
121  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
122  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
123  * POSSIBILITY OF SUCH DAMAGE.
124  */
125 
126 /*
127  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
128  *
129  * Taken from NetBSD
130  *
131  * "Stub" to allow remote cpu to debug over a serial line using gdb.
132  */
133 
134 #include "arch/riscv/remote_gdb.hh"
135 
136 #include <string>
137 
138 #include "arch/riscv/mmu.hh"
139 #include "arch/riscv/pagetable_walker.hh"
140 #include "arch/riscv/registers.hh"
141 #include "arch/riscv/tlb.hh"
142 #include "blobs/gdb_xml_riscv_cpu.hh"
143 #include "blobs/gdb_xml_riscv_csr.hh"
144 #include "blobs/gdb_xml_riscv_fpu.hh"
145 #include "blobs/gdb_xml_riscv_target.hh"
146 #include "cpu/thread_state.hh"
147 #include "debug/GDBAcc.hh"
148 #include "mem/page_table.hh"
149 #include "sim/full_system.hh"
150 
151 using namespace RiscvISA;
152 
153 RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
154  : BaseRemoteGDB(_system, tc, _port), regCache(this)
155 {
156 }
157 
158 bool
159 RemoteGDB::acc(Addr va, size_t len)
160 {
161  if (FullSystem)
162  {
163  MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
164  unsigned logBytes;
165  Addr paddr = va;
166 
167  PrivilegeMode pmode = mmu->getMemPriv(context(), BaseTLB::Read);
168  SATP satp = context()->readMiscReg(MISCREG_SATP);
169  if (pmode != PrivilegeMode::PRV_M &&
170  satp.mode != AddrXlateMode::BARE) {
171  Walker *walker = mmu->getDataWalker();
172  Fault fault = walker->startFunctional(
173  context(), paddr, logBytes, BaseTLB::Read);
174  if (fault != NoFault)
175  return false;
176  }
177  return true;
178  }
179 
180  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
181 }
182 
183 void
184 RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
185 {
186  DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
187 
188  // General registers
189  for (int i = 0; i < NumIntArchRegs; i++)
190  {
191  r.gpr[i] = context->readIntReg(i);
192  }
193  r.pc = context->pcState().pc();
194 
195  // Floating point registers
196  for (int i = 0; i < NumFloatRegs; i++)
197  r.fpu[i] = context->readFloatReg(i);
198  r.fflags = context->readMiscRegNoEffect(
199  CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
200  r.frm = context->readMiscRegNoEffect(
201  CSRData.at(CSR_FRM).physIndex) & CSRMasks.at(CSR_FRM);
202  r.fcsr = context->readMiscRegNoEffect(
203  CSRData.at(CSR_FCSR).physIndex) & CSRMasks.at(CSR_FCSR);
204 
205  // CSR registers
206  r.cycle = context->readMiscRegNoEffect(
207  CSRData.at(CSR_CYCLE).physIndex);
208  r.time = context->readMiscRegNoEffect(
209  CSRData.at(CSR_TIME).physIndex);
210 
211  // U mode CSR
212  r.ustatus = context->readMiscRegNoEffect(
213  CSRData.at(CSR_USTATUS).physIndex) & CSRMasks.at(CSR_USTATUS);
214  r.uie = context->readMiscReg(
215  CSRData.at(CSR_UIE).physIndex) & CSRMasks.at(CSR_UIE);
216  r.utvec = context->readMiscRegNoEffect(
217  CSRData.at(CSR_UTVEC).physIndex);
218  r.uscratch = context->readMiscRegNoEffect(
219  CSRData.at(CSR_USCRATCH).physIndex);
220  r.uepc = context->readMiscRegNoEffect(
221  CSRData.at(CSR_UEPC).physIndex);
222  r.ucause = context->readMiscRegNoEffect(
223  CSRData.at(CSR_UCAUSE).physIndex);
224  r.utval = context->readMiscRegNoEffect(
225  CSRData.at(CSR_UTVAL).physIndex);
226  r.uip = context->readMiscReg(
227  CSRData.at(CSR_UIP).physIndex) & CSRMasks.at(CSR_UIP);
228 
229  // S mode CSR
230  r.sstatus = context->readMiscRegNoEffect(
231  CSRData.at(CSR_SSTATUS).physIndex) & CSRMasks.at(CSR_SSTATUS);
232  r.sedeleg = context->readMiscRegNoEffect(
233  CSRData.at(CSR_SEDELEG).physIndex);
234  r.sideleg = context->readMiscRegNoEffect(
235  CSRData.at(CSR_SIDELEG).physIndex);
236  r.sie = context->readMiscReg(
237  CSRData.at(CSR_SIE).physIndex) & CSRMasks.at(CSR_SIE);
238  r.stvec = context->readMiscRegNoEffect(
239  CSRData.at(CSR_STVEC).physIndex);
240  r.scounteren = context->readMiscRegNoEffect(
241  CSRData.at(CSR_SCOUNTEREN).physIndex);
242  r.sscratch = context->readMiscRegNoEffect(
243  CSRData.at(CSR_SSCRATCH).physIndex);
244  r.sepc = context->readMiscRegNoEffect(
245  CSRData.at(CSR_SEPC).physIndex);
246  r.scause = context->readMiscRegNoEffect(
247  CSRData.at(CSR_SCAUSE).physIndex);
248  r.stval = context->readMiscRegNoEffect(
249  CSRData.at(CSR_STVAL).physIndex);
250  r.sip = context->readMiscReg(
251  CSRData.at(CSR_SIP).physIndex) & CSRMasks.at(CSR_SIP);
252  r.satp = context->readMiscRegNoEffect(
253  CSRData.at(CSR_SATP).physIndex);
254 
255  // M mode CSR
256  r.mvendorid = context->readMiscRegNoEffect(
257  CSRData.at(CSR_MVENDORID).physIndex);
258  r.marchid = context->readMiscRegNoEffect(
259  CSRData.at(CSR_MARCHID).physIndex);
260  r.mimpid = context->readMiscRegNoEffect(
261  CSRData.at(CSR_MIMPID).physIndex);
262  r.mhartid = context->readMiscRegNoEffect(
263  CSRData.at(CSR_MHARTID).physIndex);
264  r.mstatus = context->readMiscRegNoEffect(
265  CSRData.at(CSR_MSTATUS).physIndex) & CSRMasks.at(CSR_MSTATUS);
266  r.misa = context->readMiscRegNoEffect(
267  CSRData.at(CSR_MISA).physIndex) & CSRMasks.at(CSR_MISA);
268  r.medeleg = context->readMiscRegNoEffect(
269  CSRData.at(CSR_MEDELEG).physIndex);
270  r.mideleg = context->readMiscRegNoEffect(
271  CSRData.at(CSR_MIDELEG).physIndex);
272  r.mie = context->readMiscReg(
273  CSRData.at(CSR_MIE).physIndex) & CSRMasks.at(CSR_MIE);
274  r.mtvec = context->readMiscRegNoEffect(
275  CSRData.at(CSR_MTVEC).physIndex);
276  r.mcounteren = context->readMiscRegNoEffect(
277  CSRData.at(CSR_MCOUNTEREN).physIndex);
278  r.mscratch = context->readMiscRegNoEffect(
279  CSRData.at(CSR_MSCRATCH).physIndex);
280  r.mepc = context->readMiscRegNoEffect(
281  CSRData.at(CSR_MEPC).physIndex);
282  r.mcause = context->readMiscRegNoEffect(
283  CSRData.at(CSR_MCAUSE).physIndex);
284  r.mtval = context->readMiscRegNoEffect(
285  CSRData.at(CSR_MTVAL).physIndex);
286  r.mip = context->readMiscReg(
287  CSRData.at(CSR_MIP).physIndex) & CSRMasks.at(CSR_MIP);
288 
289  // H mode CSR (to be implemented)
290 }
291 
292 void
293 RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
294 {
295  // NOTE: no error will be reported for attempting to set masked bits.
296  RegVal oldVal;
297  int mask;
298  RegVal newVal;
299 
300  DPRINTF(GDBAcc, "setregs in remotegdb \n");
301  for (int i = 0; i < NumIntArchRegs; i++)
302  context->setIntReg(i, r.gpr[i]);
303  context->pcState(r.pc);
304 
305  // Floating point registers
306  for (int i = 0; i < NumFloatRegs; i++)
307  context->setFloatReg(i, r.fpu[i]);
308 
309  oldVal = context->readMiscRegNoEffect(
310  CSRData.at(CSR_FFLAGS).physIndex);
311  mask = CSRMasks.at(CSR_FFLAGS);
312  newVal = (oldVal & ~mask) | (r.fflags & mask);
313  context->setMiscRegNoEffect(
314  CSRData.at(CSR_FFLAGS).physIndex, newVal);
315 
316  oldVal = context->readMiscRegNoEffect(
317  CSRData.at(CSR_FRM).physIndex);
318  mask = CSRMasks.at(CSR_FRM);
319  newVal = (oldVal & ~mask) | (r.frm & mask);
320  context->setMiscRegNoEffect(
321  CSRData.at(CSR_FRM).physIndex, newVal);
322 
323  oldVal = context->readMiscRegNoEffect(
324  CSRData.at(CSR_FCSR).physIndex);
325  mask = CSRMasks.at(CSR_FCSR);
326  newVal = (oldVal & ~mask) | (r.fcsr & mask);
327  context->setMiscRegNoEffect(
328  CSRData.at(CSR_FCSR).physIndex, newVal);
329 
330  // CSR registers
331  context->setMiscRegNoEffect(
332  CSRData.at(CSR_CYCLE).physIndex, r.cycle);
333  context->setMiscRegNoEffect(
334  CSRData.at(CSR_TIME).physIndex, r.time);
335 
336  // U mode CSR
337  oldVal = context->readMiscRegNoEffect(
338  CSRData.at(CSR_USTATUS).physIndex);
339  mask = CSRMasks.at(CSR_USTATUS);
340  newVal = (oldVal & ~mask) | (r.ustatus & mask);
341  context->setMiscRegNoEffect(
342  CSRData.at(CSR_USTATUS).physIndex, newVal);
343  oldVal = context->readMiscReg(
344  CSRData.at(CSR_UIE).physIndex);
345  mask = CSRMasks.at(CSR_UIE);
346  newVal = (oldVal & ~mask) | (r.uie & mask);
347  context->setMiscReg(
348  CSRData.at(CSR_UIE).physIndex, newVal);
349  context->setMiscRegNoEffect(
350  CSRData.at(CSR_UTVEC).physIndex, r.utvec);
351  context->setMiscRegNoEffect(
352  CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
353  context->setMiscRegNoEffect(
354  CSRData.at(CSR_UEPC).physIndex, r.uepc);
355  context->setMiscRegNoEffect(
356  CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
357  context->setMiscRegNoEffect(
358  CSRData.at(CSR_UTVAL).physIndex, r.utval);
359  oldVal = context->readMiscReg(
360  CSRData.at(CSR_UIP).physIndex);
361  mask = CSRMasks.at(CSR_UIP);
362  newVal = (oldVal & ~mask) | (r.uip & mask);
363  context->setMiscReg(
364  CSRData.at(CSR_UIP).physIndex, newVal);
365 
366  // S mode CSR
367  oldVal = context->readMiscRegNoEffect(
368  CSRData.at(CSR_SSTATUS).physIndex);
369  mask = CSRMasks.at(CSR_SSTATUS);
370  newVal = (oldVal & ~mask) | (r.sstatus & mask);
371  context->setMiscRegNoEffect(
372  CSRData.at(CSR_SSTATUS).physIndex, newVal);
373  context->setMiscRegNoEffect(
374  CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
375  context->setMiscRegNoEffect(
376  CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
377  oldVal = context->readMiscReg(
378  CSRData.at(CSR_SIE).physIndex);
379  mask = CSRMasks.at(CSR_SIE);
380  newVal = (oldVal & ~mask) | (r.sie & mask);
381  context->setMiscReg(
382  CSRData.at(CSR_SIE).physIndex, newVal);
383  context->setMiscRegNoEffect(
384  CSRData.at(CSR_STVEC).physIndex, r.stvec);
385  context->setMiscRegNoEffect(
386  CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
387  context->setMiscRegNoEffect(
388  CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
389  context->setMiscRegNoEffect(
390  CSRData.at(CSR_SEPC).physIndex, r.sepc);
391  context->setMiscRegNoEffect(
392  CSRData.at(CSR_SCAUSE).physIndex, r.scause);
393  context->setMiscRegNoEffect(
394  CSRData.at(CSR_STVAL).physIndex, r.stval);
395  oldVal = context->readMiscReg(
396  CSRData.at(CSR_SIP).physIndex);
397  mask = CSRMasks.at(CSR_SIP);
398  newVal = (oldVal & ~mask) | (r.sip & mask);
399  context->setMiscReg(
400  CSRData.at(CSR_SIP).physIndex, newVal);
401  context->setMiscRegNoEffect(
402  CSRData.at(CSR_SATP).physIndex, r.satp);
403 
404  // M mode CSR
405  context->setMiscRegNoEffect(
406  CSRData.at(CSR_MVENDORID).physIndex, r.mvendorid);
407  context->setMiscRegNoEffect(
408  CSRData.at(CSR_MARCHID).physIndex, r.marchid);
409  context->setMiscRegNoEffect(
410  CSRData.at(CSR_MIMPID).physIndex, r.mimpid);
411  context->setMiscRegNoEffect(
412  CSRData.at(CSR_MHARTID).physIndex, r.mhartid);
413  oldVal = context->readMiscRegNoEffect(
414  CSRData.at(CSR_MSTATUS).physIndex);
415  mask = CSRMasks.at(CSR_MSTATUS);
416  newVal = (oldVal & ~mask) | (r.mstatus & mask);
417  context->setMiscRegNoEffect(
418  CSRData.at(CSR_MSTATUS).physIndex, newVal);
419  oldVal = context->readMiscRegNoEffect(
420  CSRData.at(CSR_MISA).physIndex);
421  mask = CSRMasks.at(CSR_MISA);
422  newVal = (oldVal & ~mask) | (r.misa & mask);
423  context->setMiscRegNoEffect(
424  CSRData.at(CSR_MISA).physIndex, newVal);
425  context->setMiscRegNoEffect(
426  CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
427  context->setMiscRegNoEffect(
428  CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
429  oldVal = context->readMiscReg(
430  CSRData.at(CSR_MIE).physIndex);
431  mask = CSRMasks.at(CSR_MIE);
432  newVal = (oldVal & ~mask) | (r.mie & mask);
433  context->setMiscReg(
434  CSRData.at(CSR_MIE).physIndex, newVal);
435  context->setMiscRegNoEffect(
436  CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
437  context->setMiscRegNoEffect(
438  CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
439  context->setMiscRegNoEffect(
440  CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
441  context->setMiscRegNoEffect(
442  CSRData.at(CSR_MEPC).physIndex, r.mepc);
443  context->setMiscRegNoEffect(
444  CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
445  context->setMiscRegNoEffect(
446  CSRData.at(CSR_MTVAL).physIndex, r.mtval);
447  oldVal = context->readMiscReg(
448  CSRData.at(CSR_MIP).physIndex);
449  mask = CSRMasks.at(CSR_MIP);
450  newVal = (oldVal & ~mask) | (r.mip & mask);
451  context->setMiscReg(
452  CSRData.at(CSR_MIP).physIndex, newVal);
453 
454  // H mode CSR (to be implemented)
455 }
456 
457 bool
458 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
459 {
466 #define GDB_XML(x, s) \
467  { \
468  x, std::string(reinterpret_cast<const char *>(Blobs::s), \
469  Blobs::s##_len) \
470  }
471  static const std::map<std::string, std::string> annexMap{
472  GDB_XML("target.xml", gdb_xml_riscv_target),
473  GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_cpu),
474  GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_fpu),
475  GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_csr)};
476 #undef GDB_XML
477  auto it = annexMap.find(annex);
478  if (it == annexMap.end())
479  return false;
480  output = it->second;
481  return true;
482 }
483 
484 BaseGdbRegCache *
485 RemoteGDB::gdbRegs()
486 {
487  return &regCache;
488 }
RiscvISA::CSR_STVEC
@ CSR_STVEC
Definition: registers.hh:333
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
RiscvISA::CSR_USCRATCH
@ CSR_USCRATCH
Definition: registers.hh:287
RiscvISA::CSR_FCSR
@ CSR_FCSR
Definition: registers.hh:294
output
static void output(const char *filename)
Definition: debug.cc:60
thread_state.hh
BaseTLB::Read
@ Read
Definition: tlb.hh:57
RiscvISA::RemoteGDB::getXferFeaturesRead
bool getXferFeaturesRead(const std::string &annex, std::string &output) override
Reply to qXfer:features:read:xxx.xml qeuries.
Definition: remote_gdb.cc:458
RiscvISA::MMU
Definition: mmu.hh:50
RiscvISA::CSR_MEDELEG
@ CSR_MEDELEG
Definition: registers.hh:348
RiscvISA::CSRMasks
const std::map< int, RegVal > CSRMasks
Definition: registers.hh:736
RiscvISA::CSR_SATP
@ CSR_SATP
Definition: registers.hh:340
RiscvISA::CSR_MIE
@ CSR_MIE
Definition: registers.hh:350
RiscvISA::CSR_MTVEC
@ CSR_MTVEC
Definition: registers.hh:351
RiscvISA::CSR_MIMPID
@ CSR_MIMPID
Definition: registers.hh:344
RiscvISA::CSR_MCAUSE
@ CSR_MCAUSE
Definition: registers.hh:355
ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
RiscvISA::CSR_SCOUNTEREN
@ CSR_SCOUNTEREN
Definition: registers.hh:334
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs
void getRegs(ThreadContext *)
Fill the raw buffer from the registers in the ThreadContext.
Definition: remote_gdb.cc:184
RiscvISA::RemoteGDB::RiscvGdbRegCache::r
struct RiscvISA::RemoteGDB::RiscvGdbRegCache::@15 r
RISC-V Register Cache Order and sizes of registers found in ext/gdb-xml/riscv.xml To add support for ...
Process::pTable
EmulationPageTable * pTable
Definition: process.hh:169
RiscvISA::CSR_UTVAL
@ CSR_UTVAL
Definition: registers.hh:290
RiscvISA::CSR_MSTATUS
@ CSR_MSTATUS
Definition: registers.hh:346
RiscvISA::CSR_MCOUNTEREN
@ CSR_MCOUNTEREN
Definition: registers.hh:352
RiscvISA::CSR_SIE
@ CSR_SIE
Definition: registers.hh:332
RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs
void setRegs(ThreadContext *) const
Set the ThreadContext's registers from the values in the raw buffer.
Definition: remote_gdb.cc:293
RiscvISA::CSR_MISA
@ CSR_MISA
Definition: registers.hh:347
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:204
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
RiscvISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs() override
Definition: remote_gdb.cc:485
GDB_XML
#define GDB_XML(x, s)
RiscvISA::CSR_SIP
@ CSR_SIP
Definition: registers.hh:339
RiscvISA::CSR_MHARTID
@ CSR_MHARTID
Definition: registers.hh:345
RiscvISA::CSR_UIP
@ CSR_UIP
Definition: registers.hh:291
RiscvISA::RemoteGDB::RiscvGdbRegCache::size
size_t size() const
Return the size of the raw buffer, in bytes (i.e., half of the number of digits in the g/G packet).
Definition: remote_gdb.hh:129
RiscvISA::CSR_MVENDORID
@ CSR_MVENDORID
Definition: registers.hh:342
RiscvISA::CSR_USTATUS
@ CSR_USTATUS
Definition: registers.hh:284
EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:130
RiscvISA
Definition: fs_workload.cc:37
RiscvISA::MMU::getMemPriv
PrivilegeMode getMemPriv(ThreadContext *tc, BaseTLB::Mode mode)
Definition: mmu.hh:60
RiscvISA::CSR_UIE
@ CSR_UIE
Definition: registers.hh:285
ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:303
RiscvISA::CSR_CYCLE
@ CSR_CYCLE
Definition: registers.hh:295
RiscvISA::CSR_TIME
@ CSR_TIME
Definition: registers.hh:296
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
RiscvISA::CSR_UCAUSE
@ CSR_UCAUSE
Definition: registers.hh:289
RiscvISA::CSR_SSTATUS
@ CSR_SSTATUS
Definition: registers.hh:329
tlb.hh
System
Definition: system.hh:73
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:237
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:246
RiscvISA::CSR_SEDELEG
@ CSR_SEDELEG
Definition: registers.hh:330
RiscvISA::Walker
Definition: pagetable_walker.hh:58
RiscvISA::MMU::getDataWalker
Walker * getDataWalker()
Definition: mmu.hh:66
RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:56
RiscvISA::CSR_UTVEC
@ CSR_UTVEC
Definition: registers.hh:286
RiscvISA::RemoteGDB::acc
bool acc(Addr addr, size_t len) override
Definition: remote_gdb.cc:159
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:251
RiscvISA::NumIntArchRegs
const int NumIntArchRegs
Definition: registers.hh:109
BaseRemoteGDB
Definition: remote_gdb.hh:43
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:72
registers.hh
full_system.hh
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
RiscvISA::CSR_STVAL
@ CSR_STVAL
Definition: registers.hh:338
RiscvISA::CSR_MEPC
@ CSR_MEPC
Definition: registers.hh:354
remote_gdb.hh
RiscvISA::mask
mask
Definition: pra_constants.hh:70
RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:276
RiscvISA::RemoteGDB::regCache
RiscvGdbRegCache regCache
Definition: remote_gdb.hh:140
RiscvISA::CSR_SCAUSE
@ CSR_SCAUSE
Definition: registers.hh:337
mmu.hh
ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
RiscvISA::CSR_SIDELEG
@ CSR_SIDELEG
Definition: registers.hh:331
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ArmISA::len
Bitfield< 18, 16 > len
Definition: miscregs_types.hh:439
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:72
RiscvISA::CSR_MIDELEG
@ CSR_MIDELEG
Definition: registers.hh:349
RiscvISA::CSR_MSCRATCH
@ CSR_MSCRATCH
Definition: registers.hh:353
RiscvISA::CSR_MTVAL
@ CSR_MTVAL
Definition: registers.hh:356
RiscvISA::CSR_SEPC
@ CSR_SEPC
Definition: registers.hh:336
RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:112
RiscvISA::CSR_UEPC
@ CSR_UEPC
Definition: registers.hh:288
RiscvISA::MISCREG_SATP
@ MISCREG_SATP
Definition: registers.hh:269
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
RiscvISA::CSR_SSCRATCH
@ CSR_SSCRATCH
Definition: registers.hh:335
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
page_table.hh
RiscvISA::CSRData
const std::map< int, CSRMetadata > CSRData
Definition: registers.hh:455
RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:60
RiscvISA::Walker::startFunctional
Fault startFunctional(ThreadContext *_tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode)
Definition: pagetable_walker.cc:94
RiscvISA::CSR_MIP
@ CSR_MIP
Definition: registers.hh:357
RiscvISA::CSR_FRM
@ CSR_FRM
Definition: registers.hh:293
RiscvISA::CSR_FFLAGS
@ CSR_FFLAGS
Definition: registers.hh:292
RegVal
uint64_t RegVal
Definition: types.hh:174
ArmISA::va
Bitfield< 8 > va
Definition: miscregs_types.hh:272
RiscvISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, ThreadContext *tc, int _port)
Definition: remote_gdb.cc:153
RiscvISA::CSR_MARCHID
@ CSR_MARCHID
Definition: registers.hh:343
pagetable_walker.hh
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