gem5  v21.0.1.0
static_inst.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved.
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions are
17  * met: redistributions of source code must retain the above copyright
18  * notice, this list of conditions and the following disclaimer;
19  * redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in the
21  * documentation and/or other materials provided with the distribution;
22  * neither the name of the copyright holders nor the names of its
23  * contributors may be used to endorse or promote products derived from
24  * this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37  */
38 
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "cpu/reg_class.hh"
43 
44 namespace X86ISA
45 {
46 
47 void
48 X86StaticInst::printMnemonic(std::ostream &os, const char *mnemonic) const
49 {
50  ccprintf(os, " %s ", mnemonic);
51 }
52 
53 void
54 X86StaticInst::printMnemonic(std::ostream &os, const char *instMnemonic,
55  const char *mnemonic) const
56 {
57  ccprintf(os, " %s : %s ", instMnemonic, mnemonic);
58 }
59 
60 void X86StaticInst::printSegment(std::ostream &os, int segment) const
61 {
62  switch (segment)
63  {
64  case SEGMENT_REG_ES:
65  ccprintf(os, "ES");
66  break;
67  case SEGMENT_REG_CS:
68  ccprintf(os, "CS");
69  break;
70  case SEGMENT_REG_SS:
71  ccprintf(os, "SS");
72  break;
73  case SEGMENT_REG_DS:
74  ccprintf(os, "DS");
75  break;
76  case SEGMENT_REG_FS:
77  ccprintf(os, "FS");
78  break;
79  case SEGMENT_REG_GS:
80  ccprintf(os, "GS");
81  break;
82  case SEGMENT_REG_HS:
83  ccprintf(os, "HS");
84  break;
85  case SEGMENT_REG_TSL:
86  ccprintf(os, "TSL");
87  break;
88  case SEGMENT_REG_TSG:
89  ccprintf(os, "TSG");
90  break;
91  case SEGMENT_REG_LS:
92  ccprintf(os, "LS");
93  break;
94  case SEGMENT_REG_MS:
95  ccprintf(os, "MS");
96  break;
97  case SYS_SEGMENT_REG_TR:
98  ccprintf(os, "TR");
99  break;
101  ccprintf(os, "IDTR");
102  break;
103  default:
104  panic("Unrecognized segment %d\n", segment);
105  }
106 }
107 
108 void
109 X86StaticInst::printSrcReg(std::ostream &os, int reg, int size) const
110 {
111  if (_numSrcRegs > reg)
112  printReg(os, srcRegIdx(reg), size);
113 }
114 
115 void
116 X86StaticInst::printDestReg(std::ostream &os, int reg, int size) const
117 {
118  if (_numDestRegs > reg)
119  printReg(os, destRegIdx(reg), size);
120 }
121 
122 void
123 X86StaticInst::printReg(std::ostream &os, RegId reg, int size) const
124 {
125  assert(size == 1 || size == 2 || size == 4 || size == 8);
126  static const char * abcdFormats[9] =
127  {"", "%s", "%sx", "", "e%sx", "", "", "", "r%sx"};
128  static const char * piFormats[9] =
129  {"", "%s", "%s", "", "e%s", "", "", "", "r%s"};
130  static const char * longFormats[9] =
131  {"", "r%sb", "r%sw", "", "r%sd", "", "", "", "r%s"};
132  static const char * microFormats[9] =
133  {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"};
134 
135  RegIndex reg_idx = reg.index();
136 
137  if (reg.isIntReg()) {
138  const char * suffix = "";
139  bool fold = reg_idx & IntFoldBit;
140  reg_idx &= ~IntFoldBit;
141 
142  if (fold)
143  suffix = "h";
144  else if (reg_idx < 8 && size == 1)
145  suffix = "l";
146 
147  switch (reg_idx) {
148  case INTREG_RAX:
149  ccprintf(os, abcdFormats[size], "a");
150  break;
151  case INTREG_RBX:
152  ccprintf(os, abcdFormats[size], "b");
153  break;
154  case INTREG_RCX:
155  ccprintf(os, abcdFormats[size], "c");
156  break;
157  case INTREG_RDX:
158  ccprintf(os, abcdFormats[size], "d");
159  break;
160  case INTREG_RSP:
161  ccprintf(os, piFormats[size], "sp");
162  break;
163  case INTREG_RBP:
164  ccprintf(os, piFormats[size], "bp");
165  break;
166  case INTREG_RSI:
167  ccprintf(os, piFormats[size], "si");
168  break;
169  case INTREG_RDI:
170  ccprintf(os, piFormats[size], "di");
171  break;
172  case INTREG_R8W:
173  ccprintf(os, longFormats[size], "8");
174  break;
175  case INTREG_R9W:
176  ccprintf(os, longFormats[size], "9");
177  break;
178  case INTREG_R10W:
179  ccprintf(os, longFormats[size], "10");
180  break;
181  case INTREG_R11W:
182  ccprintf(os, longFormats[size], "11");
183  break;
184  case INTREG_R12W:
185  ccprintf(os, longFormats[size], "12");
186  break;
187  case INTREG_R13W:
188  ccprintf(os, longFormats[size], "13");
189  break;
190  case INTREG_R14W:
191  ccprintf(os, longFormats[size], "14");
192  break;
193  case INTREG_R15W:
194  ccprintf(os, longFormats[size], "15");
195  break;
196  default:
197  ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS);
198  }
199  ccprintf(os, suffix);
200 
201  } else if (reg.isFloatReg()) {
202  if (reg_idx < NumMMXRegs) {
203  ccprintf(os, "%%mmx%d", reg_idx);
204  return;
205  }
206  reg_idx -= NumMMXRegs;
207  if (reg_idx < NumXMMRegs * 2) {
208  ccprintf(os, "%%xmm%d_%s", reg_idx / 2,
209  (reg_idx % 2) ? "high": "low");
210  return;
211  }
212  reg_idx -= NumXMMRegs * 2;
213  if (reg_idx < NumMicroFpRegs) {
214  ccprintf(os, "%%ufp%d", reg_idx);
215  return;
216  }
217  reg_idx -= NumMicroFpRegs;
218  ccprintf(os, "%%st(%d)", reg_idx);
219 
220  } else if (reg.isCCReg()) {
221  ccprintf(os, "%%cc%d", reg_idx);
222 
223  } else if (reg.isMiscReg()) {
224  switch (reg_idx) {
225  default:
226  ccprintf(os, "%%ctrl%d", reg_idx);
227  }
228  }
229 }
230 
231 void
232 X86StaticInst::printMem(std::ostream &os, uint8_t segment,
233  uint8_t scale, RegIndex index, RegIndex base,
234  uint64_t disp, uint8_t addressSize, bool rip) const
235 {
236  bool someAddr = false;
237  printSegment(os, segment);
238  os << ":[";
239  if (rip) {
240  os << "rip";
241  someAddr = true;
242  } else {
243  if (scale != 0 && index != ZeroReg) {
244  if (scale != 1)
245  ccprintf(os, "%d*", scale);
246  printReg(os, InstRegIndex(index), addressSize);
247  someAddr = true;
248  }
249  if (base != ZeroReg) {
250  if (someAddr)
251  os << " + ";
252  printReg(os, InstRegIndex(base), addressSize);
253  someAddr = true;
254  }
255  }
256  if (disp != 0) {
257  if (someAddr)
258  os << " + ";
259  ccprintf(os, "%#x", disp);
260  someAddr = true;
261  }
262  if (!someAddr)
263  os << "0";
264  os << "]";
265 }
266 
267 std::string
269  Addr pc, const Loader::SymbolTable *symtab) const
270 {
271  std::stringstream ss;
272 
274 
275  return ss.str();
276 }
277 
278 }
X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:151
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:234
static_inst.hh
X86ISA::SEGMENT_REG_FS
@ SEGMENT_REG_FS
Definition: segment.hh:49
X86ISA::SEGMENT_REG_TSG
@ SEGMENT_REG_TSG
Definition: segment.hh:53
Loader::SymbolTable
Definition: symtab.hh:58
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:138
X86ISA::X86StaticInst::printDestReg
void printDestReg(std::ostream &os, int reg, int size) const
Definition: static_inst.cc:116
X86ISA::SYS_SEGMENT_REG_IDTR
@ SYS_SEGMENT_REG_IDTR
Definition: segment.hh:60
X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:59
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:88
X86ISA::scale
scale
Definition: types.hh:93
X86ISA::SEGMENT_REG_LS
@ SEGMENT_REG_LS
Definition: segment.hh:54
X86ISA::X86StaticInst::printReg
void printReg(std::ostream &os, RegId reg, int size) const
Definition: static_inst.cc:123
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
X86ISA::SEGMENT_REG_HS
@ SEGMENT_REG_HS
Definition: segment.hh:51
X86ISA::InstRegIndex
Class for register indices passed to instruction constructors.
Definition: static_inst.hh:53
X86ISA::SEGMENT_REG_TSL
@ SEGMENT_REG_TSL
Definition: segment.hh:52
X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:94
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
X86ISA::SEGMENT_REG_MS
@ SEGMENT_REG_MS
Definition: segment.hh:55
segment.hh
X86ISA::X86StaticInst::printSegment
void printSegment(std::ostream &os, int segment) const
Definition: static_inst.cc:60
X86ISA::X86StaticInst::printMnemonic
void printMnemonic(std::ostream &os, const char *mnemonic) const
Definition: static_inst.cc:48
X86ISA::X86StaticInst::printMem
void printMem(std::ostream &os, uint8_t segment, uint8_t scale, RegIndex index, RegIndex base, uint64_t disp, uint8_t addressSize, bool rip) const
Definition: static_inst.cc:232
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:284
StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:244
X86ISA::X86StaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:268
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
X86ISA::ZeroReg
const int ZeroReg
Definition: registers.hh:81
X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:58
X86ISA::SEGMENT_REG_DS
@ SEGMENT_REG_DS
Definition: segment.hh:48
X86ISA::SEGMENT_REG_SS
@ SEGMENT_REG_SS
Definition: segment.hh:47
X86ISA::SEGMENT_REG_CS
@ SEGMENT_REG_CS
Definition: segment.hh:46
RegIndex
uint16_t RegIndex
Definition: types.hh:52
X86ISA::SYS_SEGMENT_REG_TR
@ SYS_SEGMENT_REG_TR
Definition: segment.hh:59
X86ISA::X86StaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg, int size) const
Definition: static_inst.cc:109
ArmISA::NUM_INTREGS
@ NUM_INTREGS
Definition: intregs.hh:123
reg_class.hh
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
X86ISA::SEGMENT_REG_ES
@ SEGMENT_REG_ES
Definition: segment.hh:45
X86ISA::SEGMENT_REG_GS
@ SEGMENT_REG_GS
Definition: segment.hh:50
StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:106
X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:109
X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:57
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

Generated on Tue Jun 22 2021 15:28:20 for gem5 by doxygen 1.8.17