gem5
v21.0.1.0
arch
arm
fastmodel
iris
isa.hh
Go to the documentation of this file.
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#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
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#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
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#include "
arch/arm/utility.hh
"
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#include "
arch/generic/isa.hh
"
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namespace
Iris
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{
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class
ISA
:
public
BaseISA
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{
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public
:
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ISA
(
const
Params
&
p
) :
BaseISA
(
p
) {}
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void
serialize
(
CheckpointOut
&
cp
)
const
;
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bool
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inUserMode
()
const override
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{
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CPSR cpsr =
tc
->
readMiscRegNoEffect
(
MISCREG_CPSR
);
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return ::inUserMode
(cpsr);
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}
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};
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}
// namespace Iris
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#endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
SimObject::Params
SimObjectParams Params
Definition:
sim_object.hh:162
Iris
Definition:
cpu.cc:34
Iris::ISA::ISA
ISA(const Params &p)
Definition:
isa.hh:40
cp
Definition:
cprintf.cc:37
Iris::ISA::inUserMode
bool inUserMode() const override
Definition:
isa.hh:45
BaseISA::tc
ThreadContext * tc
Definition:
isa.hh:52
Iris::ISA
Definition:
isa.hh:37
utility.hh
isa.hh
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition:
miscregs.hh:57
CheckpointOut
std::ostream CheckpointOut
Definition:
serialize.hh:64
Iris::ISA::serialize
void serialize(CheckpointOut &cp) const
Serialize an object.
Definition:
isa.cc:36
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition:
utility.hh:108
BaseISA
Definition:
isa.hh:47
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