gem5  v21.0.1.0
isa.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
30 
31 #include "arch/arm/utility.hh"
32 #include "arch/generic/isa.hh"
33 
34 namespace Iris
35 {
36 
37 class ISA : public BaseISA
38 {
39  public:
40  ISA(const Params &p) : BaseISA(p) {}
41 
42  void serialize(CheckpointOut &cp) const;
43 
44  bool
45  inUserMode() const override
46  {
47  CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
48  return ::inUserMode(cpsr);
49  }
50 };
51 
52 } // namespace Iris
53 
54 #endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:162
Iris
Definition: cpu.cc:34
Iris::ISA::ISA
ISA(const Params &p)
Definition: isa.hh:40
cp
Definition: cprintf.cc:37
Iris::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:45
BaseISA::tc
ThreadContext * tc
Definition: isa.hh:52
Iris::ISA
Definition: isa.hh:37
utility.hh
isa.hh
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:64
Iris::ISA::serialize
void serialize(CheckpointOut &cp) const
Serialize an object.
Definition: isa.cc:36
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition: utility.hh:108
BaseISA
Definition: isa.hh:47

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