gem5  v21.1.0.2
gpu_static_inst.hh
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33 
34 #ifndef __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
35 #define __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
36 
42 #include "gpu-compute/wavefront.hh"
43 
44 namespace gem5
45 {
46 
47 namespace Gcn3ISA
48 {
50  {
51  public:
52  GCN3GPUStaticInst(const std::string &opcode);
54 
55  void generateDisassembly() override { disassembly = _opcode; }
56 
57  bool
58  isFlatScratchRegister(int opIdx) override
59  {
60  return isFlatScratchReg(opIdx);
61  }
62 
63  bool
64  isExecMaskRegister(int opIdx) override
65  {
66  return isExecMask(opIdx);
67  }
68 
69  void initOperandInfo() override { return; }
70  int getOperandSize(int opIdx) override { return 0; }
71 
79  int coalescerTokenCount() const override { return 1; }
80  ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
81 
82  protected:
83  void panicUnimplemented() const;
84 
91  }; // class GCN3GPUStaticInst
92 
93 } // namespace Gcn3ISA
94 } // namespace gem5
95 
96 #endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
gem5::Gcn3ISA::GCN3GPUStaticInst::generateDisassembly
void generateDisassembly() override
Definition: gpu_static_inst.hh:55
gem5::Gcn3ISA::GCN3GPUStaticInst::srcLiteral
ScalarRegU32 srcLiteral() const override
Definition: gpu_static_inst.hh:80
gem5::Gcn3ISA::GCN3GPUStaticInst::_srcLiteral
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
Definition: gpu_static_inst.hh:90
gem5::GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:300
gpu_registers.hh
gpu_static_inst.hh
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:63
gem5::Gcn3ISA::GCN3GPUStaticInst::isFlatScratchRegister
bool isFlatScratchRegister(int opIdx) override
Definition: gpu_static_inst.hh:58
gem5::Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:200
wavefront.hh
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:264
vector_register_file.hh
gem5::Gcn3ISA::GCN3GPUStaticInst::initOperandInfo
void initOperandInfo() override
Definition: gpu_static_inst.hh:69
gem5::Gcn3ISA::GCN3GPUStaticInst::isExecMaskRegister
bool isExecMaskRegister(int opIdx) override
Definition: gpu_static_inst.hh:64
scalar_register_file.hh
operand.hh
gem5::Gcn3ISA::GCN3GPUStaticInst::~GCN3GPUStaticInst
~GCN3GPUStaticInst()
Definition: gpu_static_inst.cc:51
gem5::Gcn3ISA::GCN3GPUStaticInst::GCN3GPUStaticInst
GCN3GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:46
gem5::GPUStaticInst::_opcode
const std::string _opcode
Definition: gpu_static_inst.hh:299
gem5::Gcn3ISA::GCN3GPUStaticInst::coalescerTokenCount
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
Definition: gpu_static_inst.hh:79
gem5::Gcn3ISA::GCN3GPUStaticInst::getOperandSize
int getOperandSize(int opIdx) override
Definition: gpu_static_inst.hh:70
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gcn3ISA::GCN3GPUStaticInst::panicUnimplemented
void panicUnimplemented() const
Definition: gpu_static_inst.cc:56
gem5::Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:212
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:155
gem5::Gcn3ISA::GCN3GPUStaticInst
Definition: gpu_static_inst.hh:49

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