gem5
v21.1.0.2
arch
arm
fastmodel
iris
isa.hh
Go to the documentation of this file.
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#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
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#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
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#include "
arch/arm/utility.hh
"
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#include "
arch/generic/isa.hh
"
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namespace
gem5
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{
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namespace
Iris
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{
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class
ISA
:
public
BaseISA
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{
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public
:
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ISA
(
const
Params
&
p
) :
BaseISA
(
p
) {}
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void
serialize
(
CheckpointOut
&cp)
const override
;
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void
copyRegsFrom
(
ThreadContext
*src)
override
;
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bool
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inUserMode
()
const override
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{
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ArmISA::CPSR cpsr =
tc
->
readMiscRegNoEffect
(
ArmISA::MISCREG_CPSR
);
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return
ArmISA::inUserMode
(cpsr);
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}
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};
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}
// namespace Iris
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}
// namespace gem5
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#endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition:
misc.hh:61
gem5::BaseISA::tc
ThreadContext * tc
Definition:
isa.hh:62
gem5::Iris::ISA
Definition:
isa.hh:40
gem5::Iris::ISA::inUserMode
bool inUserMode() const override
Definition:
isa.hh:50
gem5::SimObject::Params
SimObjectParams Params
Definition:
sim_object.hh:170
gem5::Iris::ThreadContext
Definition:
thread_context.hh:51
gem5::MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:326
gem5::Iris::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition:
isa.cc:48
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
utility.hh
isa.hh
gem5::ArmISA::inUserMode
static bool inUserMode(CPSR cpsr)
Definition:
utility.hh:96
gem5::Iris::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition:
isa.cc:39
gem5::CheckpointOut
std::ostream CheckpointOut
Definition:
serialize.hh:66
gem5::BaseISA
Definition:
isa.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
decoder.cc:40
gem5::Iris::ISA::ISA
ISA(const Params &p)
Definition:
isa.hh:43
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