pseudo.hh

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/*
 * Copyright (c) 2014,2016,2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2007-2008 The Florida State University
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 */
 
#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
#define __ARCH_ARM_INSTS_PSEUDO_HH__
 
#include "arch/arm/insts/static_inst.hh"
 
namespace gem5
{
 
class DecoderFaultInst : public ArmISA::ArmStaticInst
{
  protected:
    ArmISA::DecoderFault faultId;
 
    const char *faultName() const;
 
  public:
    DecoderFaultInst(ArmISA::ExtMachInst _machInst);
 
    Fault execute(ExecContext *xc,
                  Trace::InstRecord *traceData) const override;
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class FailUnimplemented : public ArmISA::ArmStaticInst
{
  private:
    std::string fullMnemonic;
 
  public:
    FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst);
    FailUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
                      const std::string& _fullMnemonic);
 
    Fault execute(ExecContext *xc,
                  Trace::InstRecord *traceData) const override;
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class WarnUnimplemented : public ArmISA::ArmStaticInst
{
  private:
    mutable bool warned;
    std::string fullMnemonic;
 
  public:
    WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst);
    WarnUnimplemented(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
                      const std::string& _fullMnemonic);
 
    Fault execute(ExecContext *xc,
                  Trace::InstRecord *traceData) const override;
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class IllegalExecInst : public ArmISA::ArmStaticInst
{
  public:
    IllegalExecInst(ArmISA::ExtMachInst _machInst);
 
    Fault execute(ExecContext *xc,
                  Trace::InstRecord *traceData) const override;
};
 
class DebugStep : public ArmISA::ArmStaticInst
{
  public:
    DebugStep(ArmISA::ExtMachInst _machInst);
 
    Fault execute(ExecContext *xc,
                  Trace::InstRecord *traceData) const override;
};
 
} // namespace gem5
 
#endif