branch64.cc

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#include "arch/arm/insts/branch64.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
ArmISA::PCState
BranchImm64::branchTarget(const ArmISA::PCState &branchPC) const
{
    ArmISA::PCState pcs = branchPC;
    pcs.instNPC(pcs.pc() + imm);
    pcs.advance();
    return pcs;
}
 
ArmISA::PCState
BranchImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
{
    ArmISA::PCState pcs = branchPC;
    pcs.instNPC(pcs.pc() + imm);
    pcs.advance();
    return pcs;
}
 
ArmISA::PCState
BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
{
    ArmISA::PCState pcs = branchPC;
    pcs.instNPC(pcs.pc() + imm2);
    pcs.advance();
    return pcs;
}
 
std::string
BranchImmCond64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false, true, condCode);
    printTarget(ss, pc + imm, symtab);
    return ss.str();
}
 
std::string
BranchImm64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printTarget(ss, pc + imm, symtab);
    return ss.str();
}
 
std::string
BranchReg64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, op1);
    return ss.str();
}
 
std::string
BranchRegReg64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, op1);
    ccprintf(ss, ", ");
    printIntReg(ss, op2);
    return ss.str();
}
 
std::string
BranchRet64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    if (op1 != INTREG_X30)
        printIntReg(ss, op1);
    return ss.str();
}
 
std::string
BranchRetA64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    if (op1 != INTREG_X30)
        printIntReg(ss, op1);
    return ss.str();
}
 
std::string
BranchEret64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    return ss.str();
}
 
std::string
BranchEretA64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    return ss.str();
}
 
std::string
BranchImmReg64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, op1);
    ccprintf(ss, ", ");
    printTarget(ss, pc + imm, symtab);
    return ss.str();
}
 
std::string
BranchImmImmReg64::generateDisassembly(
        Addr pc, const loader::SymbolTable *symtab) const
{
    std::stringstream ss;
    printMnemonic(ss, "", false);
    printIntReg(ss, op1);
    ccprintf(ss, ", #%#x, ", imm1);
    printTarget(ss, pc + imm2, symtab);
    return ss.str();
}
 
} // namespace ArmISA
} // namespace gem5