#include <spatio_temporal_memory_streaming.hh>

Inheritance diagram for gem5::prefetch::STeMS:

Classes
struct	ActiveGenerationTableEntry
	Entry data type for the Active Generation Table (AGT) and the Pattern Sequence Table (PST) More...

struct	RegionMissOrderBufferEntry
	Data type of the Region Miss Order Buffer entry. More...

Public Member Functions
	STeMS (const STeMSPrefetcherParams &p)

	~STeMS ()=default

void	calculatePrefetch (const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses) override

Public Member Functions inherited from gem5::prefetch::Queued
	Queued (const QueuedPrefetcherParams &p)

virtual	~Queued ()

void	notify (const PacketPtr &pkt, const PrefetchInfo &pfi) override
	Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters.) More...

void	insert (const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority)

PacketPtr	getPacket () override

Tick	nextPrefetchReadyTime () const override

void	printQueue (const std::list< DeferredPacket > &queue) const

Public Member Functions inherited from gem5::prefetch::Base
	Base (const BasePrefetcherParams &p)

virtual	~Base ()=default

virtual void	setCache (BaseCache *_cache)

virtual void	notifyFill (const PacketPtr &pkt)
	Notify prefetcher of cache fill. More...

void	prefetchUnused ()

void	incrDemandMhsrMisses ()

void	pfHitInCache ()

void	pfHitInMSHR ()

void	pfHitInWB ()

void	regProbeListeners () override
	Register probe points for this object. More...

void	probeNotify (const PacketPtr &pkt, bool miss)
	Process a notification event from the ProbeListener. More...

void	addEventProbe (SimObject obj, const char name)
	Add a SimObject and a probe name to listen events from. More...

void	addTLB (BaseTLB *tlb)
	Add a BaseTLB object to be used whenever a translation is needed. More...

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (statistics::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Private Member Functions
void	checkForActiveGenerationsEnd ()
	Checks if the active generations have ended. More...

void	addToRMOB (Addr sr_addr, Addr pst_addr, unsigned int delta)
	Adds an entry to the RMOB. More...

void	reconstructSequence (CircularQueue< RegionMissOrderBufferEntry >::iterator rmob_it, std::vector< AddrPriority > &addresses)
	Reconstructs a sequence of accesses and generates the prefetch addresses, adding them to the addresses vector. More...

Private Attributes
const size_t	spatialRegionSize
	Size of each spatial region. More...

const size_t	spatialRegionSizeBits
	log_2 of the spatial region size More...

const unsigned int	reconstructionEntries
	Number of reconstruction entries. More...

AssociativeSet< ActiveGenerationTableEntry >	activeGenerationTable
	Active Generation Table (AGT) More...

AssociativeSet< ActiveGenerationTableEntry >	patternSequenceTable
	Pattern Sequence Table (PST) More...

CircularQueue< RegionMissOrderBufferEntry >	rmob
	Region Miss Order Buffer (RMOB) More...

unsigned int	lastTriggerCounter
	Counter to keep the count of accesses between trigger accesses. More...

Additional Inherited Members
Public Types inherited from gem5::prefetch::Queued
using	AddrPriority = std::pair< Addr, int32_t >

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject. More...

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Types inherited from gem5::prefetch::Queued
using	const_iterator = std::list< DeferredPacket >::const_iterator

using	iterator = std::list< DeferredPacket >::iterator

Protected Member Functions inherited from gem5::prefetch::Base
bool	observeAccess (const PacketPtr &pkt, bool miss) const
	Determine if this access should be observed. More...

bool	inCache (Addr addr, bool is_secure) const
	Determine if address is in cache. More...

bool	inMissQueue (Addr addr, bool is_secure) const
	Determine if address is in cache miss queue. More...

bool	hasBeenPrefetched (Addr addr, bool is_secure) const

bool	samePage (Addr a, Addr b) const
	Determine if addresses are on the same page. More...

Addr	blockAddress (Addr a) const
	Determine the address of the block in which a lays. More...

Addr	blockIndex (Addr a) const
	Determine the address of a at block granularity. More...

Addr	pageAddress (Addr a) const
	Determine the address of the page in which a lays. More...

Addr	pageOffset (Addr a) const
	Determine the page-offset of a More...

Addr	pageIthBlockAddress (Addr page, uint32_t i) const
	Build the address of the i-th block inside the page. More...

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Protected Attributes inherited from gem5::prefetch::Queued
std::list< DeferredPacket >	pfq

std::list< DeferredPacket >	pfqMissingTranslation

const unsigned	queueSize
	Maximum size of the prefetch queue. More...

const unsigned	missingTranslationQueueSize
	Maximum size of the queue holding prefetch requests with missing address translations. More...

const Cycles	latency
	Cycles after generation when a prefetch can first be issued. More...

const bool	queueSquash
	Squash queued prefetch if demand access observed. More...

const bool	queueFilter
	Filter prefetches if already queued. More...

const bool	cacheSnoop
	Snoop the cache before generating prefetch (cheating basically) More...

const bool	tagPrefetch
	Tag prefetch with PC of generating access? More...

const unsigned int	throttleControlPct
	Percentage of requests that can be throttled. More...

gem5::prefetch::Queued::QueuedStats	statsQueued

Protected Attributes inherited from gem5::prefetch::Base
BaseCache *	cache
	Pointr to the parent cache. More...

unsigned	blkSize
	The block size of the parent cache. More...

unsigned	lBlkSize
	log_2(block size of the parent cache). More...

const bool	onMiss
	Only consult prefetcher on cache misses? More...

const bool	onRead
	Consult prefetcher on reads? More...

const bool	onWrite
	Consult prefetcher on reads? More...

const bool	onData
	Consult prefetcher on data accesses? More...

const bool	onInst
	Consult prefetcher on instruction accesses? More...

const RequestorID	requestorId
	Request id for prefetches. More...

const Addr	pageBytes

const bool	prefetchOnAccess
	Prefetch on every access, not just misses. More...

const bool	prefetchOnPfHit
	Prefetch on hit on prefetched lines. More...

const bool	useVirtualAddresses
	Use Virtual Addresses for prefetching. More...

gem5::prefetch::Base::StatGroup	prefetchStats

uint64_t	issuedPrefetches
	Total prefetches issued. More...

uint64_t	usefulPrefetches
	Total prefetches that has been useful. More...

BaseTLB *	tlb
	Registered tlb for address translations. More...

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Detailed Description

Definition at line 60 of file spatio_temporal_memory_streaming.hh.

Constructor & Destructor Documentation

◆ STeMS()

gem5::prefetch::STeMS::STeMS ( const STeMSPrefetcherParams & p )

Definition at line 42 of file spatio_temporal_memory_streaming.cc.

References fatal_if, gem5::isPowerOf2(), and spatialRegionSize.

◆ ~STeMS()

gem5::prefetch::STeMS::~STeMS ( )

default

Member Function Documentation

◆ addToRMOB()

void gem5::prefetch::STeMS::addToRMOB	(	Addr	sr_addr,
		Addr	pst_addr,
		unsigned int	delta
	)

private

Adds an entry to the RMOB.

Parameters

sr_addr	Spatial region address
pst_addr	Corresponding PST address
delta	Number of entries skipped in the global miss order

Definition at line 112 of file spatio_temporal_memory_streaming.cc.

References gem5::prefetch::STeMS::RegionMissOrderBufferEntry::delta, gem5::prefetch::STeMS::RegionMissOrderBufferEntry::pstAddress, rmob, and gem5::prefetch::STeMS::RegionMissOrderBufferEntry::srAddress.

Referenced by calculatePrefetch().

◆ calculatePrefetch()

void gem5::prefetch::STeMS::calculatePrefetch	(	const PrefetchInfo &	pfi,
		std::vector< AddrPriority > &	addresses
	)

overridevirtual

◆ checkForActiveGenerationsEnd()

void gem5::prefetch::STeMS::checkForActiveGenerationsEnd ( )

private

Checks if the active generations have ended.

Definition at line 65 of file spatio_temporal_memory_streaming.cc.

References activeGenerationTable, gem5::prefetch::Base::blkSize, gem5::prefetch::Base::inCache(), gem5::prefetch::Base::inMissQueue(), patternSequenceTable, and gem5::prefetch::STeMS::ActiveGenerationTableEntry::update().

Referenced by calculatePrefetch().

◆ reconstructSequence()

void gem5::prefetch::STeMS::reconstructSequence	(	CircularQueue< RegionMissOrderBufferEntry >::iterator	rmob_it,
		std::vector< AddrPriority > &	addresses
	)