gem5 v23.0.0.1
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remote_gdb.cc
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1/*
2 * Copyright (c) 2021 Huawei International
3 * Copyright 2015 LabWare
4 * Copyright 2014 Google, Inc.
5 * Copyright (c) 2010 ARM Limited
6 * Copyright (c) 2020 Barkhausen Institut
7 * All rights reserved
8 *
9 * The license below extends only to copyright in the software and shall
10 * not be construed as granting a license to any other intellectual
11 * property including but not limited to intellectual property relating
12 * to a hardware implementation of the functionality of the software
13 * licensed hereunder. You may use the software subject to the license
14 * terms below provided that you ensure that this notice is replicated
15 * unmodified and in its entirety in all distributions of the software,
16 * modified or unmodified, in source code or in binary form.
17 *
18 * Copyright (c) 2017 The University of Virginia
19 * Copyright (c) 2002-2005 The Regents of The University of Michigan
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its
30 * contributors may be used to endorse or promote products derived from
31 * this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46/*
47 * Copyright (c) 1990, 1993 The Regents of the University of California
48 * All rights reserved
49 *
50 * This software was developed by the Computer Systems Engineering group
51 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
52 * contributed to Berkeley.
53 *
54 * All advertising materials mentioning features or use of this software
55 * must display the following acknowledgement:
56 * This product includes software developed by the University of
57 * California, Lawrence Berkeley Laboratories.
58 *
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions
61 * are met:
62 * 1. Redistributions of source code must retain the above copyright
63 * notice, this list of conditions and the following disclaimer.
64 * 2. Redistributions in binary form must reproduce the above copyright
65 * notice, this list of conditions and the following disclaimer in the
66 * documentation and/or other materials provided with the distribution.
67 * 3. All advertising materials mentioning features or use of this software
68 * must display the following acknowledgement:
69 * This product includes software developed by the University of
70 * California, Berkeley and its contributors.
71 * 4. Neither the name of the University nor the names of its contributors
72 * may be used to endorse or promote products derived from this software
73 * without specific prior written permission.
74 *
75 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
76 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
78 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
81 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
82 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
83 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
84 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
85 * SUCH DAMAGE.
86 *
87 * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
88 */
89
90/*-
91 * Copyright (c) 2001 The NetBSD Foundation, Inc.
92 * All rights reserved.
93 *
94 * This code is derived from software contributed to The NetBSD Foundation
95 * by Jason R. Thorpe.
96 *
97 * Redistribution and use in source and binary forms, with or without
98 * modification, are permitted provided that the following conditions
99 * are met:
100 * 1. Redistributions of source code must retain the above copyright
101 * notice, this list of conditions and the following disclaimer.
102 * 2. Redistributions in binary form must reproduce the above copyright
103 * notice, this list of conditions and the following disclaimer in the
104 * documentation and/or other materials provided with the distribution.
105 * 3. All advertising materials mentioning features or use of this software
106 * must display the following acknowledgement:
107 * This product includes software developed by the NetBSD
108 * Foundation, Inc. and its contributors.
109 * 4. Neither the name of The NetBSD Foundation nor the names of its
110 * contributors may be used to endorse or promote products derived
111 * from this software without specific prior written permission.
112 *
113 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
114 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
115 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
116 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
117 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
118 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
119 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
120 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
121 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
122 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
123 * POSSIBILITY OF SUCH DAMAGE.
124 */
125
126/*
127 * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
128 *
129 * Taken from NetBSD
130 *
131 * "Stub" to allow remote cpu to debug over a serial line using gdb.
132 */
133
134#include "arch/riscv/remote_gdb.hh"
135
136#include <string>
137
138#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_cpu.hh"
139#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_csr.hh"
140#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_fpu.hh"
141#include "arch/riscv/gdb-xml/gdb_xml_riscv_32bit_target.hh"
142#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_cpu.hh"
143#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_csr.hh"
144#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_fpu.hh"
145#include "arch/riscv/gdb-xml/gdb_xml_riscv_64bit_target.hh"
146#include "arch/riscv/mmu.hh"
147#include "arch/riscv/pagetable_walker.hh"
148#include "arch/riscv/regs/float.hh"
149#include "arch/riscv/regs/int.hh"
150#include "arch/riscv/regs/misc.hh"
151#include "arch/riscv/tlb.hh"
152#include "cpu/thread_state.hh"
153#include "debug/GDBAcc.hh"
154#include "mem/page_table.hh"
155#include "sim/full_system.hh"
156
157namespace gem5
158{
159
160using namespace RiscvISA;
161
162static RiscvType
163getRvType(ThreadContext* tc)
164{
165 auto isa = dynamic_cast<ISA*>(tc->getIsaPtr());
166 panic_if(!isa, "Cannot derive rv_type from non-riscv isa");
167 return isa->rvType();
168}
169
170template <typename xint>
171static void
172setRegNoEffectWithMask(
173 ThreadContext *context, RiscvType type, CSRIndex idx, xint val)
174{
175 RegVal oldVal, newVal;
176 RegVal mask = CSRMasks[type].at(idx);
177 oldVal = context->readMiscRegNoEffect(CSRData.at(idx).physIndex);
178 newVal = (oldVal & ~mask) | (val & mask);
179 context->setMiscRegNoEffect(CSRData.at(idx).physIndex, newVal);
180}
181
182template <typename xint>
183static void
184setRegWithMask(ThreadContext *context, RiscvType type, CSRIndex idx, xint val)
185{
186 RegVal oldVal, newVal;
187 RegVal mask = CSRMasks[type].at(idx);
188 oldVal = context->readMiscReg(CSRData.at(idx).physIndex);
189 newVal = (oldVal & ~mask) | (val & mask);
190 context->setMiscReg(CSRData.at(idx).physIndex, newVal);
191}
192
193RemoteGDB::RemoteGDB(System *_system, ListenSocketConfig _listen_config)
194 : BaseRemoteGDB(_system, _listen_config),
195 regCache32(this), regCache64(this)
196{
197}
198
199bool
200RemoteGDB::acc(Addr va, size_t len)
201{
202 if (FullSystem)
203 {
204 MMU *mmu = static_cast<MMU *>(context()->getMMUPtr());
205 unsigned logBytes;
206 Addr paddr = va;
207
208 PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read);
209 SATP satp = context()->readMiscReg(MISCREG_SATP);
210 if (pmode != PrivilegeMode::PRV_M &&
211 satp.mode != AddrXlateMode::BARE) {
212 Walker *walker = mmu->getDataWalker();
213 Fault fault = walker->startFunctional(
214 context(), paddr, logBytes, BaseMMU::Read);
215 if (fault != NoFault)
216 return false;
217 }
218 return true;
219 }
220
221 return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
222}
223
224void
225RemoteGDB::Riscv32GdbRegCache::getRegs(ThreadContext *context)
226{
227 DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
228 auto& RVxCSRMasks = CSRMasks[RV32];
229
230 // General registers
231 for (int i = 0; i < int_reg::NumArchRegs; i++) {
232 r.gpr[i] = context->getReg(intRegClass[i]);
233 }
234 r.pc = context->pcState().instAddr();
235
236 // Floating point registers
237 for (int i = 0; i < float_reg::NumRegs; i++)
238 r.fpu[i] = context->getReg(floatRegClass[i]);
239 r.fflags = context->readMiscRegNoEffect(
240 CSRData.at(CSR_FFLAGS).physIndex) & RVxCSRMasks.at(CSR_FFLAGS);
241 r.frm = context->readMiscRegNoEffect(
242 CSRData.at(CSR_FRM).physIndex) & RVxCSRMasks.at(CSR_FRM);
243 r.fcsr = context->readMiscRegNoEffect(
244 CSRData.at(CSR_FCSR).physIndex) & RVxCSRMasks.at(CSR_FCSR);
245
246 // CSR registers
247 r.cycle = context->readMiscRegNoEffect(
248 CSRData.at(CSR_CYCLE).physIndex);
249 r.cycleh = context->readMiscRegNoEffect(
250 CSRData.at(CSR_CYCLEH).physIndex);
251 r.time = context->readMiscRegNoEffect(
252 CSRData.at(CSR_TIME).physIndex);
253 r.timeh = context->readMiscRegNoEffect(
254 CSRData.at(CSR_TIMEH).physIndex);
255
256 // U mode CSR
257 r.ustatus = context->readMiscReg(
258 CSRData.at(CSR_USTATUS).physIndex) & RVxCSRMasks.at(CSR_USTATUS);
259 r.uie = context->readMiscReg(
260 CSRData.at(CSR_UIE).physIndex) & RVxCSRMasks.at(CSR_UIE);
261 r.utvec = context->readMiscRegNoEffect(
262 CSRData.at(CSR_UTVEC).physIndex);
263 r.uscratch = context->readMiscRegNoEffect(
264 CSRData.at(CSR_USCRATCH).physIndex);
265 r.uepc = context->readMiscRegNoEffect(
266 CSRData.at(CSR_UEPC).physIndex);
267 r.ucause = context->readMiscRegNoEffect(
268 CSRData.at(CSR_UCAUSE).physIndex);
269 r.utval = context->readMiscRegNoEffect(
270 CSRData.at(CSR_UTVAL).physIndex);
271 r.uip = context->readMiscReg(
272 CSRData.at(CSR_UIP).physIndex) & RVxCSRMasks.at(CSR_UIP);
273
274 // S mode CSR
275 r.sstatus = context->readMiscReg(
276 CSRData.at(CSR_SSTATUS).physIndex) & RVxCSRMasks.at(CSR_SSTATUS);
277 r.sedeleg = context->readMiscRegNoEffect(
278 CSRData.at(CSR_SEDELEG).physIndex);
279 r.sideleg = context->readMiscRegNoEffect(
280 CSRData.at(CSR_SIDELEG).physIndex);
281 r.sie = context->readMiscReg(
282 CSRData.at(CSR_SIE).physIndex) & RVxCSRMasks.at(CSR_SIE);
283 r.stvec = context->readMiscRegNoEffect(
284 CSRData.at(CSR_STVEC).physIndex);
285 r.scounteren = context->readMiscRegNoEffect(
286 CSRData.at(CSR_SCOUNTEREN).physIndex);
287 r.sscratch = context->readMiscRegNoEffect(
288 CSRData.at(CSR_SSCRATCH).physIndex);
289 r.sepc = context->readMiscReg(
290 CSRData.at(CSR_SEPC).physIndex);
291 r.scause = context->readMiscRegNoEffect(
292 CSRData.at(CSR_SCAUSE).physIndex);
293 r.stval = context->readMiscRegNoEffect(
294 CSRData.at(CSR_STVAL).physIndex);
295 r.sip = context->readMiscReg(
296 CSRData.at(CSR_SIP).physIndex) & RVxCSRMasks.at(CSR_SIP);
297 r.satp = context->readMiscRegNoEffect(
298 CSRData.at(CSR_SATP).physIndex);
299
300 // M mode CSR
301 r.mvendorid = context->readMiscRegNoEffect(
302 CSRData.at(CSR_MVENDORID).physIndex);
303 r.marchid = context->readMiscRegNoEffect(
304 CSRData.at(CSR_MARCHID).physIndex);
305 r.mimpid = context->readMiscRegNoEffect(
306 CSRData.at(CSR_MIMPID).physIndex);
307 r.mhartid = context->contextId();
308 r.mstatus = context->readMiscReg(
309 CSRData.at(CSR_MSTATUS).physIndex) & RVxCSRMasks.at(CSR_MSTATUS);
310 r.misa = context->readMiscRegNoEffect(
311 CSRData.at(CSR_MISA).physIndex) & RVxCSRMasks.at(CSR_MISA);
312 r.medeleg = context->readMiscRegNoEffect(
313 CSRData.at(CSR_MEDELEG).physIndex);
314 r.mideleg = context->readMiscRegNoEffect(
315 CSRData.at(CSR_MIDELEG).physIndex);
316 r.mie = context->readMiscReg(
317 CSRData.at(CSR_MIE).physIndex) & RVxCSRMasks.at(CSR_MIE);
318 r.mtvec = context->readMiscRegNoEffect(
319 CSRData.at(CSR_MTVEC).physIndex);
320 r.mcounteren = context->readMiscRegNoEffect(
321 CSRData.at(CSR_MCOUNTEREN).physIndex);
322 r.mstatush = context->readMiscReg(
323 CSRData.at(CSR_MSTATUSH).physIndex) & RVxCSRMasks.at(CSR_MSTATUSH);
324 r.mscratch = context->readMiscRegNoEffect(
325 CSRData.at(CSR_MSCRATCH).physIndex);
326 r.mepc = context->readMiscReg(
327 CSRData.at(CSR_MEPC).physIndex);
328 r.mcause = context->readMiscRegNoEffect(
329 CSRData.at(CSR_MCAUSE).physIndex);
330 r.mtval = context->readMiscRegNoEffect(
331 CSRData.at(CSR_MTVAL).physIndex);
332 r.mip = context->readMiscReg(
333 CSRData.at(CSR_MIP).physIndex) & RVxCSRMasks.at(CSR_MIP);
334
335 // H mode CSR (to be implemented)
336}
337
338void
339RemoteGDB::Riscv32GdbRegCache::setRegs(ThreadContext *context) const
340{
341 DPRINTF(GDBAcc, "setregs in remotegdb \n");
342 for (int i = 0; i < int_reg::NumArchRegs; i++)
343 context->setReg(intRegClass[i], r.gpr[i]);
344 context->pcState(r.pc);
345
346 // Floating point registers
347 for (int i = 0; i < float_reg::NumRegs; i++)
348 context->setReg(floatRegClass[i], r.fpu[i]);
349
350 setRegNoEffectWithMask(context, RV32, CSR_FFLAGS, r.fflags);
351 setRegNoEffectWithMask(context, RV32, CSR_FRM, r.frm);
352 setRegNoEffectWithMask(context, RV32, CSR_FCSR, r.fcsr);
353
354 // TODO: implement CSR counter registers for mcycle(h), minstret(h)
355
356 // U mode CSR
357 setRegNoEffectWithMask(context, RV32, CSR_USTATUS, r.ustatus);
358 setRegWithMask(context, RV32, CSR_UIE, r.uie);
359 setRegWithMask(context, RV32, CSR_UIP, r.uip);
360 context->setMiscRegNoEffect(
361 CSRData.at(CSR_UTVEC).physIndex, r.utvec);
362 context->setMiscRegNoEffect(
363 CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
364 context->setMiscRegNoEffect(
365 CSRData.at(CSR_UEPC).physIndex, r.uepc);
366 context->setMiscRegNoEffect(
367 CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
368 context->setMiscRegNoEffect(
369 CSRData.at(CSR_UTVAL).physIndex, r.utval);
370
371 // S mode CSR
372 setRegNoEffectWithMask(context, RV32, CSR_SSTATUS, r.sstatus);
373 setRegWithMask(context, RV32, CSR_SIE, r.sie);
374 setRegWithMask(context, RV32, CSR_SIP, r.sip);
375 context->setMiscRegNoEffect(
376 CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
377 context->setMiscRegNoEffect(
378 CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
379 context->setMiscRegNoEffect(
380 CSRData.at(CSR_STVEC).physIndex, r.stvec);
381 context->setMiscRegNoEffect(
382 CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
383 context->setMiscRegNoEffect(
384 CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
385 context->setMiscRegNoEffect(
386 CSRData.at(CSR_SEPC).physIndex, r.sepc);
387 context->setMiscRegNoEffect(
388 CSRData.at(CSR_SCAUSE).physIndex, r.scause);
389 context->setMiscRegNoEffect(
390 CSRData.at(CSR_STVAL).physIndex, r.stval);
391 context->setMiscRegNoEffect(
392 CSRData.at(CSR_SATP).physIndex, r.satp);
393
394 // M mode CSR
395 setRegNoEffectWithMask(context, RV32, CSR_MSTATUS, r.mstatus);
396 setRegNoEffectWithMask(context, RV32, CSR_MISA, r.misa);
397 setRegWithMask(context, RV32, CSR_MIE, r.mie);
398 setRegWithMask(context, RV32, CSR_MIP, r.mip);
399 context->setMiscRegNoEffect(
400 CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
401 context->setMiscRegNoEffect(
402 CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
403 context->setMiscRegNoEffect(
404 CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
405 context->setMiscRegNoEffect(
406 CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
407 context->setMiscRegNoEffect(
408 CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
409 context->setMiscRegNoEffect(
410 CSRData.at(CSR_MEPC).physIndex, r.mepc);
411 context->setMiscRegNoEffect(
412 CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
413 context->setMiscRegNoEffect(
414 CSRData.at(CSR_MTVAL).physIndex, r.mtval);
415
416 // H mode CSR (to be implemented)
417}
418
419void
420RemoteGDB::Riscv64GdbRegCache::getRegs(ThreadContext *context)
421{
422 DPRINTF(GDBAcc, "getregs in remotegdb, size %lu\n", size());
423 auto& RVxCSRMasks = CSRMasks[RV64];
424
425 // General registers
426 for (int i = 0; i < int_reg::NumArchRegs; i++) {
427 r.gpr[i] = context->getReg(intRegClass[i]);
428 }
429 r.pc = context->pcState().instAddr();
430
431 // Floating point registers
432 for (int i = 0; i < float_reg::NumRegs; i++)
433 r.fpu[i] = context->getReg(floatRegClass[i]);
434 r.fflags = context->readMiscRegNoEffect(
435 CSRData.at(CSR_FFLAGS).physIndex) & RVxCSRMasks.at(CSR_FFLAGS);
436 r.frm = context->readMiscRegNoEffect(
437 CSRData.at(CSR_FRM).physIndex) & RVxCSRMasks.at(CSR_FRM);
438 r.fcsr = context->readMiscRegNoEffect(
439 CSRData.at(CSR_FCSR).physIndex) & RVxCSRMasks.at(CSR_FCSR);
440
441 // CSR registers
442 r.cycle = context->readMiscRegNoEffect(
443 CSRData.at(CSR_CYCLE).physIndex);
444 r.time = context->readMiscRegNoEffect(
445 CSRData.at(CSR_TIME).physIndex);
446
447 // U mode CSR
448 r.ustatus = context->readMiscReg(
449 CSRData.at(CSR_USTATUS).physIndex) & RVxCSRMasks.at(CSR_USTATUS);
450 r.uie = context->readMiscReg(
451 CSRData.at(CSR_UIE).physIndex) & RVxCSRMasks.at(CSR_UIE);
452 r.utvec = context->readMiscRegNoEffect(
453 CSRData.at(CSR_UTVEC).physIndex);
454 r.uscratch = context->readMiscRegNoEffect(
455 CSRData.at(CSR_USCRATCH).physIndex);
456 r.uepc = context->readMiscRegNoEffect(
457 CSRData.at(CSR_UEPC).physIndex);
458 r.ucause = context->readMiscRegNoEffect(
459 CSRData.at(CSR_UCAUSE).physIndex);
460 r.utval = context->readMiscRegNoEffect(
461 CSRData.at(CSR_UTVAL).physIndex);
462 r.uip = context->readMiscReg(
463 CSRData.at(CSR_UIP).physIndex) & RVxCSRMasks.at(CSR_UIP);
464
465 // S mode CSR
466 r.sstatus = context->readMiscReg(
467 CSRData.at(CSR_SSTATUS).physIndex) & RVxCSRMasks.at(CSR_SSTATUS);
468 r.sedeleg = context->readMiscRegNoEffect(
469 CSRData.at(CSR_SEDELEG).physIndex);
470 r.sideleg = context->readMiscRegNoEffect(
471 CSRData.at(CSR_SIDELEG).physIndex);
472 r.sie = context->readMiscReg(
473 CSRData.at(CSR_SIE).physIndex) & RVxCSRMasks.at(CSR_SIE);
474 r.stvec = context->readMiscRegNoEffect(
475 CSRData.at(CSR_STVEC).physIndex);
476 r.scounteren = context->readMiscRegNoEffect(
477 CSRData.at(CSR_SCOUNTEREN).physIndex);
478 r.sscratch = context->readMiscRegNoEffect(
479 CSRData.at(CSR_SSCRATCH).physIndex);
480 r.sepc = context->readMiscReg(
481 CSRData.at(CSR_SEPC).physIndex);
482 r.scause = context->readMiscRegNoEffect(
483 CSRData.at(CSR_SCAUSE).physIndex);
484 r.stval = context->readMiscRegNoEffect(
485 CSRData.at(CSR_STVAL).physIndex);
486 r.sip = context->readMiscReg(
487 CSRData.at(CSR_SIP).physIndex) & RVxCSRMasks.at(CSR_SIP);
488 r.satp = context->readMiscRegNoEffect(
489 CSRData.at(CSR_SATP).physIndex);
490
491 // M mode CSR
492 r.mvendorid = context->readMiscRegNoEffect(
493 CSRData.at(CSR_MVENDORID).physIndex);
494 r.marchid = context->readMiscRegNoEffect(
495 CSRData.at(CSR_MARCHID).physIndex);
496 r.mimpid = context->readMiscRegNoEffect(
497 CSRData.at(CSR_MIMPID).physIndex);
498 r.mhartid = context->contextId();
499 r.mstatus = context->readMiscReg(
500 CSRData.at(CSR_MSTATUS).physIndex) & RVxCSRMasks.at(CSR_MSTATUS);
501 r.misa = context->readMiscRegNoEffect(
502 CSRData.at(CSR_MISA).physIndex) & RVxCSRMasks.at(CSR_MISA);
503 r.medeleg = context->readMiscRegNoEffect(
504 CSRData.at(CSR_MEDELEG).physIndex);
505 r.mideleg = context->readMiscRegNoEffect(
506 CSRData.at(CSR_MIDELEG).physIndex);
507 r.mie = context->readMiscReg(
508 CSRData.at(CSR_MIE).physIndex) & RVxCSRMasks.at(CSR_MIE);
509 r.mtvec = context->readMiscRegNoEffect(
510 CSRData.at(CSR_MTVEC).physIndex);
511 r.mcounteren = context->readMiscRegNoEffect(
512 CSRData.at(CSR_MCOUNTEREN).physIndex);
513 r.mscratch = context->readMiscRegNoEffect(
514 CSRData.at(CSR_MSCRATCH).physIndex);
515 r.mepc = context->readMiscReg(
516 CSRData.at(CSR_MEPC).physIndex);
517 r.mcause = context->readMiscRegNoEffect(
518 CSRData.at(CSR_MCAUSE).physIndex);
519 r.mtval = context->readMiscRegNoEffect(
520 CSRData.at(CSR_MTVAL).physIndex);
521 r.mip = context->readMiscReg(
522 CSRData.at(CSR_MIP).physIndex) & RVxCSRMasks.at(CSR_MIP);
523
524 // H mode CSR (to be implemented)
525}
526
527void
528RemoteGDB::Riscv64GdbRegCache::setRegs(ThreadContext *context) const
529{
530 DPRINTF(GDBAcc, "setregs in remotegdb \n");
531 for (int i = 0; i < int_reg::NumArchRegs; i++)
532 context->setReg(intRegClass[i], r.gpr[i]);
533 context->pcState(r.pc);
534
535 // Floating point registers
536 for (int i = 0; i < float_reg::NumRegs; i++)
537 context->setReg(floatRegClass[i], r.fpu[i]);
538
539 setRegNoEffectWithMask(context, RV64, CSR_FFLAGS, r.fflags);
540 setRegNoEffectWithMask(context, RV64, CSR_FRM, r.frm);
541 setRegNoEffectWithMask(context, RV64, CSR_FCSR, r.fcsr);
542
543 // TODO: implement CSR counter registers for mcycle, minstret
544
545 // U mode CSR
546 setRegNoEffectWithMask(context, RV64, CSR_USTATUS, r.ustatus);
547 setRegWithMask(context, RV64, CSR_UIE, r.uie);
548 setRegWithMask(context, RV64, CSR_UIP, r.uip);
549 context->setMiscRegNoEffect(
550 CSRData.at(CSR_UTVEC).physIndex, r.utvec);
551 context->setMiscRegNoEffect(
552 CSRData.at(CSR_USCRATCH).physIndex, r.uscratch);
553 context->setMiscRegNoEffect(
554 CSRData.at(CSR_UEPC).physIndex, r.uepc);
555 context->setMiscRegNoEffect(
556 CSRData.at(CSR_UCAUSE).physIndex, r.ucause);
557 context->setMiscRegNoEffect(
558 CSRData.at(CSR_UTVAL).physIndex, r.utval);
559
560 // S mode CSR
561 setRegNoEffectWithMask(context, RV64, CSR_SSTATUS, r.sstatus);
562 setRegWithMask(context, RV64, CSR_SIE, r.sie);
563 setRegWithMask(context, RV64, CSR_SIP, r.sip);
564 context->setMiscRegNoEffect(
565 CSRData.at(CSR_SEDELEG).physIndex, r.sedeleg);
566 context->setMiscRegNoEffect(
567 CSRData.at(CSR_SIDELEG).physIndex, r.sideleg);
568 context->setMiscRegNoEffect(
569 CSRData.at(CSR_STVEC).physIndex, r.stvec);
570 context->setMiscRegNoEffect(
571 CSRData.at(CSR_SCOUNTEREN).physIndex, r.scounteren);
572 context->setMiscRegNoEffect(
573 CSRData.at(CSR_SSCRATCH).physIndex, r.sscratch);
574 context->setMiscRegNoEffect(
575 CSRData.at(CSR_SEPC).physIndex, r.sepc);
576 context->setMiscRegNoEffect(
577 CSRData.at(CSR_SCAUSE).physIndex, r.scause);
578 context->setMiscRegNoEffect(
579 CSRData.at(CSR_STVAL).physIndex, r.stval);
580 context->setMiscRegNoEffect(
581 CSRData.at(CSR_SATP).physIndex, r.satp);
582
583 // M mode CSR
584 setRegNoEffectWithMask(context, RV64, CSR_MSTATUS, r.mstatus);
585 setRegNoEffectWithMask(context, RV64, CSR_MISA, r.misa);
586 setRegWithMask(context, RV64, CSR_MIE, r.mie);
587 setRegWithMask(context, RV64, CSR_MIP, r.mip);
588 context->setMiscRegNoEffect(
589 CSRData.at(CSR_MEDELEG).physIndex, r.medeleg);
590 context->setMiscRegNoEffect(
591 CSRData.at(CSR_MIDELEG).physIndex, r.mideleg);
592 context->setMiscRegNoEffect(
593 CSRData.at(CSR_MTVEC).physIndex, r.mtvec);
594 context->setMiscRegNoEffect(
595 CSRData.at(CSR_MCOUNTEREN).physIndex, r.mcounteren);
596 context->setMiscRegNoEffect(
597 CSRData.at(CSR_MSCRATCH).physIndex, r.mscratch);
598 context->setMiscRegNoEffect(
599 CSRData.at(CSR_MEPC).physIndex, r.mepc);
600 context->setMiscRegNoEffect(
601 CSRData.at(CSR_MCAUSE).physIndex, r.mcause);
602 context->setMiscRegNoEffect(
603 CSRData.at(CSR_MTVAL).physIndex, r.mtval);
604
605 // H mode CSR (to be implemented)
606}
607
608bool
609RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
610{
617#define GDB_XML(x, s) \
618 { \
619 x, std::string(reinterpret_cast<const char *>(Blobs::s), \
620 Blobs::s##_len) \
621 }
622 static const std::map<std::string, std::string> annexMaps[enums::Num_RiscvType] = {
623 [RV32] = {GDB_XML("target.xml", gdb_xml_riscv_32bit_target),
624 GDB_XML("riscv-32bit-cpu.xml", gdb_xml_riscv_32bit_cpu),
625 GDB_XML("riscv-32bit-fpu.xml", gdb_xml_riscv_32bit_fpu),
626 GDB_XML("riscv-32bit-csr.xml", gdb_xml_riscv_32bit_csr)},
627 [RV64] = {GDB_XML("target.xml", gdb_xml_riscv_64bit_target),
628 GDB_XML("riscv-64bit-cpu.xml", gdb_xml_riscv_64bit_cpu),
629 GDB_XML("riscv-64bit-fpu.xml", gdb_xml_riscv_64bit_fpu),
630 GDB_XML("riscv-64bit-csr.xml", gdb_xml_riscv_64bit_csr)},
631 };
632 auto& annexMap = annexMaps[getRvType(context())];
633 auto it = annexMap.find(annex);
634 if (it == annexMap.end())
635 return false;
636 output = it->second;
637 return true;
638}
639
640BaseGdbRegCache *
641RemoteGDB::gdbRegs()
642{
643 BaseGdbRegCache* regs[enums::Num_RiscvType] = {
644 [RV32] = &regCache32,
645 [RV64] = &regCache64,
646 };
647 return regs[getRvType(context())];
648}
649
650} // namespace gem5
GDB_XML
#define GDB_XML(x, s)
remote_gdb.hh
DPRINTF
#define DPRINTF(x,...)
Definition trace.hh:210
gem5::ArmISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, ListenSocketConfig _listen_config)
Definition remote_gdb.cc:204
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:107
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition thread_context.hh:89
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition thread_context.cc:180
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition thread_context.cc:188
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
full_system.hh
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
len
uint16_t len
Definition helpers.cc:62
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::i
Bitfield< 7 > i
Definition misc_types.hh:67
gem5::ArmISA::intRegClass
constexpr RegClass intRegClass
Definition int.hh:173
gem5::ArmISA::va
Bitfield< 8 > va
Definition misc_types.hh:330
gem5::RiscvISA::RV32
constexpr enums::RiscvType RV32
Definition pcstate.hh:54
gem5::RiscvISA::RiscvType
enums::RiscvType RiscvType
Definition pcstate.hh:53
gem5::RiscvISA::CSRData
const std::unordered_map< int, CSRMetadata > CSRData
Definition misc.hh:494
gem5::RiscvISA::CSRMasks
const std::unordered_map< int, RegVal > CSRMasks[enums::Num_RiscvType]
Definition misc.hh:925
gem5::RiscvISA::RV64
constexpr enums::RiscvType RV64
Definition pcstate.hh:55
gem5::X86ISA::val
Bitfield< 63 > val
Definition misc.hh:776
gem5::X86ISA::floatRegClass
constexpr RegClass floatRegClass
Definition float.hh:143
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition gpu_translation_state.hh:38
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition types.hh:249
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
gem5::getRvType
static RiscvType getRvType(ThreadContext *tc)
Definition remote_gdb.cc:163
gem5::setRegNoEffectWithMask
static void setRegNoEffectWithMask(ThreadContext *context, RiscvType type, CSRIndex idx, xint val)
Definition remote_gdb.cc:172
gem5::RegVal
uint64_t RegVal
Definition types.hh:173
gem5::setRegWithMask
static void setRegWithMask(ThreadContext *context, RiscvType type, CSRIndex idx, xint val)
Definition remote_gdb.cc:184
page_table.hh
Declarations of a non-full system Page Table.
pagetable_walker.hh
thread_state.hh
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