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gem5 v23.0.0.1
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#include <isa.hh>
Public Types | |
| using | Params = RiscvISAParams |
Public Types inherited from gem5::BaseISA | |
| typedef std::vector< const RegClass * > | RegClasses |
Public Types inherited from gem5::SimObject | |
| typedef SimObjectParams | Params |
Public Member Functions | |
| void | clear () override |
| PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
| void | clearLoadReservation (ContextID cid) override |
| RegVal | readMiscRegNoEffect (RegIndex idx) const override |
| RegVal | readMiscReg (RegIndex idx) override |
| void | setMiscRegNoEffect (RegIndex idx, RegVal val) override |
| void | setMiscReg (RegIndex idx, RegVal val) override |
| virtual const std::unordered_map< int, CSRMetadata > & | getCSRDataMap () const |
| virtual const std::unordered_map< int, RegVal > & | getCSRMaskMap () const |
| bool | alignmentCheckEnabled () const |
| bool | inUserMode () const override |
| void | copyRegsFrom (ThreadContext *src) override |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. | |
| ISA (const Params &p) | |
| void | handleLockedRead (const RequestPtr &req) override |
| bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) override |
| void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) override |
| void | globalClearExclusive () override |
| void | resetThread () override |
| RiscvType | rvType () const |
Public Member Functions inherited from gem5::BaseISA | |
| virtual PCStateBase * | newPCState (Addr new_inst_addr=0) const =0 |
| virtual void | clear () |
| virtual void | clearLoadReservation (ContextID cid) |
| virtual RegVal | readMiscRegNoEffect (RegIndex idx) const =0 |
| virtual RegVal | readMiscReg (RegIndex idx)=0 |
| virtual void | setMiscRegNoEffect (RegIndex idx, RegVal val)=0 |
| virtual void | setMiscReg (RegIndex idx, RegVal val)=0 |
| virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
| virtual void | setThreadContext (ThreadContext *_tc) |
| virtual uint64_t | getExecutingAsid () const |
| virtual bool | inUserMode () const =0 |
| virtual void | copyRegsFrom (ThreadContext *src)=0 |
| virtual void | resetThread () |
| const RegClasses & | regClasses () const |
| virtual void | handleLockedRead (const RequestPtr &req) |
| virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
| virtual bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) |
| virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
| virtual void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) |
| virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
| virtual void | handleLockedSnoopHit () |
| virtual void | handleLockedSnoopHit (ExecContext *xc) |
| virtual void | globalClearExclusive () |
| virtual void | globalClearExclusive (ExecContext *xc) |
Public Member Functions inherited from gem5::SimObject | |
| const Params & | params () const |
| SimObject (const Params &p) | |
| virtual | ~SimObject () |
| virtual void | init () |
| init() is called after all C++ SimObjects have been created and all ports are connected. | |
| virtual void | loadState (CheckpointIn &cp) |
| loadState() is called on each SimObject when restoring from a checkpoint. | |
| virtual void | initState () |
| initState() is called on each SimObject when not restoring from a checkpoint. | |
| virtual void | regProbePoints () |
| Register probe points for this object. | |
| virtual void | regProbeListeners () |
| Register probe listeners for this object. | |
| ProbeManager * | getProbeManager () |
| Get the probe manager for this object. | |
| virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
| Get a port with a given name and index. | |
| virtual void | startup () |
| startup() is the final initialization call before simulation. | |
| DrainState | drain () override |
| Provide a default implementation of the drain interface for objects that don't need draining. | |
| virtual void | memWriteback () |
| Write back dirty buffers to memory using functional writes. | |
| virtual void | memInvalidate () |
| Invalidate the contents of memory buffers. | |
| void | serialize (CheckpointOut &cp) const override |
| Serialize an object. | |
| void | unserialize (CheckpointIn &cp) override |
| Unserialize an object. | |
Public Member Functions inherited from gem5::EventManager | |
| EventQueue * | eventQueue () const |
| void | schedule (Event &event, Tick when) |
| void | deschedule (Event &event) |
| void | reschedule (Event &event, Tick when, bool always=false) |
| void | schedule (Event *event, Tick when) |
| void | deschedule (Event *event) |
| void | reschedule (Event *event, Tick when, bool always=false) |
| void | wakeupEventQueue (Tick when=(Tick) -1) |
| This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
| void | setCurTick (Tick newVal) |
| EventManager (EventManager &em) | |
| Event manger manages events in the event queue. | |
| EventManager (EventManager *em) | |
| EventManager (EventQueue *eq) | |
Public Member Functions inherited from gem5::Serializable | |
| Serializable () | |
| virtual | ~Serializable () |
| virtual void | serialize (CheckpointOut &cp) const =0 |
| Serialize an object. | |
| virtual void | unserialize (CheckpointIn &cp)=0 |
| Unserialize an object. | |
| void | serializeSection (CheckpointOut &cp, const char *name) const |
| Serialize an object into a new section. | |
| void | serializeSection (CheckpointOut &cp, const std::string &name) const |
| void | unserializeSection (CheckpointIn &cp, const char *name) |
| Unserialize an a child object. | |
| void | unserializeSection (CheckpointIn &cp, const std::string &name) |
Public Member Functions inherited from gem5::Drainable | |
| DrainState | drainState () const |
| Return the current drain state of an object. | |
| virtual void | notifyFork () |
| Notify a child process of a fork. | |
Public Member Functions inherited from gem5::statistics::Group | |
| Group (Group *parent, const char *name=nullptr) | |
| Construct a new statistics group. | |
| virtual | ~Group () |
| virtual void | regStats () |
| Callback to set stat parameters. | |
| virtual void | resetStats () |
| Callback to reset stats. | |
| virtual void | preDumpStats () |
| Callback before stats are dumped. | |
| void | addStat (statistics::Info *info) |
| Register a stat with this group. | |
| const std::map< std::string, Group * > & | getStatGroups () const |
| Get all child groups associated with this object. | |
| const std::vector< Info * > & | getStats () const |
| Get all stats associated with this object. | |
| void | addStatGroup (const char *name, Group *block) |
| Add a stat block as a child of this block. | |
| const Info * | resolveStat (std::string name) const |
| Resolve a stat by its name within this group. | |
| void | mergeStatGroup (Group *block) |
| Merge the contents (stats & children) of a block to this block. | |
| Group (const Group &)=delete | |
| Group & | operator= (const Group &)=delete |
Public Member Functions inherited from gem5::Named | |
| Named (const std::string &name_) | |
| virtual | ~Named ()=default |
| virtual std::string | name () const |
Protected Member Functions | |
| bool | hpmCounterEnabled (int counter) const |
Protected Member Functions inherited from gem5::BaseISA | |
| SimObject (const Params &p) | |
Protected Member Functions inherited from gem5::Drainable | |
| Drainable () | |
| virtual | ~Drainable () |
| virtual DrainState | drain ()=0 |
| Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight. | |
| virtual void | drainResume () |
| Resume execution after a successful drain. | |
| void | signalDrainDone () const |
| Signal that an object is drained. | |
Protected Attributes | |
| RiscvType | rv_type |
| std::vector< RegVal > | miscRegFile |
| bool | checkAlignment |
| const int | WARN_FAILURE = 10000 |
| const Addr | INVALID_RESERVATION_ADDR = (Addr)-1 |
| std::unordered_map< int, Addr > | load_reservation_addrs |
Protected Attributes inherited from gem5::BaseISA | |
| ThreadContext * | tc = nullptr |
| RegClasses | _regClasses |
Protected Attributes inherited from gem5::SimObject | |
| const SimObjectParams & | _params |
| Cached copy of the object parameters. | |
Protected Attributes inherited from gem5::EventManager | |
| EventQueue * | eventq |
| A pointer to this object's event queue. | |
Additional Inherited Members | |
Static Public Member Functions inherited from gem5::SimObject | |
| static void | serializeAll (const std::string &cpt_dir) |
| Create a checkpoint by serializing all SimObjects in the system. | |
| static SimObject * | find (const char *name) |
| Find the SimObject with the given name and return a pointer to it. | |
| static void | setSimObjectResolver (SimObjectResolver *resolver) |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
| static SimObjectResolver * | getSimObjectResolver () |
| There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
Static Public Member Functions inherited from gem5::Serializable | |
| static const std::string & | currentSection () |
| Gets the fully-qualified name of the active section. | |
| static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
| Generate a checkpoint file so that the serialization can be routed to it. | |
| using gem5::RiscvISA::ISA::Params = RiscvISAParams |
| gem5::RiscvISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 246 of file isa.cc.
References gem5::BaseISA::_regClasses, gem5::ArmISA::ccRegClass, clear(), gem5::X86ISA::floatRegClass, gem5::ArmISA::intRegClass, gem5::ArmISA::matRegClass, gem5::ArmISA::miscRegClass, miscRegFile, gem5::RiscvISA::NUM_MISCREGS, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, and gem5::ArmISA::vecRegClass.
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inline |
Definition at line 123 of file isa.hh.
References checkAlignment.
Referenced by gem5::RiscvISA::RiscvStaticInst::alignmentOk().
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 282 of file isa.cc.
References gem5::RiscvISA::INITIAL, gem5::RiscvISA::MISCREG_ARCHID, gem5::RiscvISA::MISCREG_IMPID, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_NMIE, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MISCREG_VENDORID, miscRegFile, gem5::Named::name(), panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, rv_type, and gem5::ArmISA::status.
Referenced by ISA().
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inlineoverridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 96 of file isa.hh.
References INVALID_RESERVATION_ADDR, and load_reservation_addrs.
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overridevirtual |
Implements gem5::BaseISA.
Definition at line 268 of file isa.cc.
References gem5::X86ISA::floatRegClass, gem5::ThreadContext::getReg(), gem5::ArmISA::intRegClass, gem5::ThreadContext::pcState(), gem5::ThreadContext::setReg(), and gem5::BaseISA::tc.
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inlinevirtual |
Definition at line 113 of file isa.hh.
References gem5::RiscvISA::CSRData.
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inlinevirtual |
Definition at line 118 of file isa.hh.
References gem5::RiscvISA::CSRMasks, and rv_type.
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 748 of file isa.cc.
References gem5::ThreadContext::contextId(), gem5::ThreadContext::getCpuPtr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), and gem5::BaseCPU::wakeup().
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 690 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, load_reservation_addrs, and gem5::BaseISA::tc.
Reimplemented from gem5::BaseISA.
Definition at line 676 of file isa.cc.
References gem5::ThreadContext::contextId(), DPRINTF, gem5::Packet::getAddr(), INVALID_RESERVATION_ADDR, load_reservation_addrs, and gem5::BaseISA::tc.
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 700 of file isa.cc.
References gem5::ThreadContext::contextId(), gem5::curTick(), DPRINTF, INVALID_RESERVATION_ADDR, load_reservation_addrs, gem5::ThreadContext::readStCondFailures(), gem5::ThreadContext::setStCondFailures(), gem5::BaseISA::tc, warn, and WARN_FAILURE.
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protected |
Definition at line 327 of file isa.cc.
References gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_MCOUNTEREN, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SCOUNTEREN, miscRegFile, panic, gem5::RiscvISA::PRV_M, gem5::RiscvISA::PRV_S, gem5::RiscvISA::PRV_U, and readMiscRegNoEffect().
Referenced by readMiscReg().
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overridevirtual |
Implements gem5::BaseISA.
Definition at line 262 of file isa.cc.
References gem5::RiscvISA::MISCREG_PRV, miscRegFile, and gem5::RiscvISA::PRV_U.
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inlineoverridevirtual |
Implements gem5::BaseISA.
Definition at line 366 of file isa.cc.
References gem5::ThreadContext::contextId(), gem5::Clocked::curCycle(), DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::getInterruptController(), hpmCounterEnabled(), gem5::mbits(), gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_CYCLEH, gem5::RiscvISA::MISCREG_HARTID, gem5::RiscvISA::MISCREG_HPMCOUNTER03, gem5::RiscvISA::MISCREG_HPMCOUNTER03H, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_HPMCOUNTER31H, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_INSTRET, gem5::RiscvISA::MISCREG_INSTRETH, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_MEPC, gem5::RiscvISA::MISCREG_SEPC, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TIME, gem5::RiscvISA::MISCREG_TIMEH, gem5::Named::name(), panic, readMiscRegNoEffect(), gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, rv_type, setMiscRegNoEffect(), gem5::ArmISA::status, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::BaseCPU::totalInsts(), gem5::X86ISA::val, and warn.
Implements gem5::BaseISA.
Definition at line 356 of file isa.cc.
References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_MISCREGS, and panic_if.
Referenced by hpmCounterEnabled(), readMiscReg(), and setMiscReg().
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 756 of file isa.cc.
References gem5::RiscvISA::Reset::invoke(), and gem5::BaseISA::tc.
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inline |
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overridevirtual |
Serialize an object.
Output an object's state into the current checkpoint section.
| cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 662 of file isa.cc.
References DPRINTF, miscRegFile, and SERIALIZE_CONTAINER.
Implements gem5::BaseISA.
Definition at line 521 of file isa.cc.
References gem5::PCStateBase::as(), gem5::bits(), gem5::ThreadContext::getCpuPtr(), gem5::BaseCPU::getInterruptController(), gem5::ThreadContext::getMMUPtr(), gem5::RiscvISA::i, gem5::RiscvISA::MISCREG_CYCLE, gem5::RiscvISA::MISCREG_HPMCOUNTER31, gem5::RiscvISA::MISCREG_IE, gem5::RiscvISA::MISCREG_IP, gem5::RiscvISA::MISCREG_ISA, gem5::RiscvISA::MISCREG_PMPADDR00, gem5::RiscvISA::MISCREG_PMPADDR15, gem5::RiscvISA::MISCREG_PMPCFG0, gem5::RiscvISA::MISCREG_PMPCFG1, gem5::RiscvISA::MISCREG_PMPCFG2, gem5::RiscvISA::MISCREG_PMPCFG3, gem5::RiscvISA::MISCREG_PRV, gem5::RiscvISA::MISCREG_SATP, gem5::RiscvISA::MISCREG_STATUS, gem5::RiscvISA::MISCREG_TSELECT, gem5::RiscvISA::MiscRegNames, gem5::Named::name(), panic, gem5::ThreadContext::pcState(), gem5::RiscvISA::PRV_M, readMiscRegNoEffect(), gem5::RiscvISA::RV32, gem5::RiscvISA::RV64, rv_type, setMiscRegNoEffect(), gem5::RiscvISA::STATUS_SXL_MASK, gem5::RiscvISA::STATUS_UXL_MASK, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::X86ISA::val, and warn.
Implements gem5::BaseISA.
Definition at line 511 of file isa.cc.
References DPRINTF, miscRegFile, gem5::RiscvISA::MiscRegNames, gem5::RiscvISA::NUM_MISCREGS, panic_if, and gem5::X86ISA::val.
Referenced by readMiscReg(), and setMiscReg().
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overridevirtual |
Unserialize an object.
Read an object's state from the current checkpoint section.
| cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 669 of file isa.cc.
References DPRINTF, miscRegFile, and UNSERIALIZE_CONTAINER.
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protected |
Definition at line 75 of file isa.hh.
Referenced by alignmentCheckEnabled().
Definition at line 81 of file isa.hh.
Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedSnoop(), and handleLockedWrite().
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protected |
Definition at line 82 of file isa.hh.
Referenced by clearLoadReservation(), globalClearExclusive(), handleLockedRead(), handleLockedSnoop(), and handleLockedWrite().
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protected |
Definition at line 74 of file isa.hh.
Referenced by clear(), hpmCounterEnabled(), inUserMode(), ISA(), readMiscRegNoEffect(), serialize(), setMiscRegNoEffect(), and unserialize().
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protected |
Definition at line 73 of file isa.hh.
Referenced by clear(), getCSRMaskMap(), newPCState(), readMiscReg(), rvType(), and setMiscReg().
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protected |
Definition at line 80 of file isa.hh.
Referenced by handleLockedWrite().