gem5 v23.0.0.1
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fs_workload.cc
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1/*
2 * Copyright (c) 2021 Huawei International
3 * All rights reserved
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
30
31#include "arch/riscv/faults.hh"
34#include "base/loader/symtab.hh"
36#include "sim/system.hh"
37
38namespace gem5
39{
40
41namespace RiscvISA
42{
43
44void
46{
48
49 if (params().dtb_filename != "") {
50 inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
51 params().dtb_addr);
52
53 auto *dtb_file = new loader::DtbFile(params().dtb_filename);
54
55 if (!dtb_file->addBootCmdLine(
56 commandLine.c_str(), commandLine.size())) {
57 warn("couldn't append bootargs to DTB file: %s\n",
58 params().dtb_filename);
59 }
60
61 dtb_file->buildImage().offset(params().dtb_addr)
62 .write(system->physProxy);
63 delete dtb_file;
64
65 for (auto *tc: system->threads) {
66 tc->setReg(int_reg::A1, params().dtb_addr);
67 }
68 } else {
69 warn("No DTB file specified\n");
70 }
71
72 for (auto *tc: system->threads) {
74 tc->activate();
75 }
76}
77
78} // namespace RiscvISA
79} // namespace gem5
const std::string commandLine
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition faults.cc:173
PortProxy physProxy
Port to physical memory used for writing object files into ram at boot.
Definition system.hh:323
Threads threads
Definition system.hh:310
System * system
Definition workload.hh:81
This implements an image file format to support loading and modifying flattened device tree blobs for...
const Params & params() const
#define warn(...)
Definition logging.hh:256
#define inform(...)
Definition logging.hh:257
constexpr RegId A1
Definition int.hh:102
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....

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