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mem
ruby
network
simple
routing
BaseRoutingUnit.hh
Go to the documentation of this file.
1
/*
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* Copyright (c) 2021 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
20
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_NETWORK_SIMPLE_BASEROUTINGUNIT_HH__
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#define __MEM_RUBY_NETWORK_SIMPLE_BASEROUTINGUNIT_HH__
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#include <vector>
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#include "
mem/ruby/network/Network.hh
"
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#include "
mem/ruby/slicc_interface/Message.hh
"
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#include "params/BaseRoutingUnit.hh"
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#include "
sim/sim_object.hh
"
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namespace
gem5
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{
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54
namespace
ruby
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{
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class
Switch;
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class
BaseRoutingUnit
:
public
SimObject
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{
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public
:
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PARAMS
(
BaseRoutingUnit
);
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BaseRoutingUnit
(
const
Params
&
p
)
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:
SimObject
(
p
)
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{
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}
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virtual
void
addOutPort
(
LinkID
link_id,
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const
std::vector<MessageBuffer*>
& m_out_buffer,
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const
NetDest
& routing_table_entry,
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const
PortDirection
&direction,
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int
link_weight) = 0;
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struct
RouteInfo
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{
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RouteInfo
(
const
NetDest
&dests,
const
LinkID
link_id)
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:
m_destinations
(dests),
m_link_id
(link_id)
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{}
80
const
NetDest
m_destinations
;
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const
LinkID
m_link_id
;
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};
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virtual
void
route
(
const
Message
&msg,
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int
vnet,
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bool
deterministic,
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std::vector<RouteInfo>
&out_links) = 0;
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89
void
init_parent
(
Switch
*parent_switch)
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{
m_parent_switch
= parent_switch; }
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protected
:
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94
Switch
*
m_parent_switch
;
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};
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98
}
// namespace ruby
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}
// namespace gem5
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#endif // __MEM_RUBY_NETWORK_SIMPLE_BASEROUTINGUNIT_HH__
gem5::ruby::BaseRoutingUnit::RouteInfo::m_destinations
const NetDest m_destinations
Definition:
BaseRoutingUnit.hh:80
gem5::ruby::BaseRoutingUnit::m_parent_switch
Switch * m_parent_switch
Definition:
BaseRoutingUnit.hh:94
gem5::ruby::PortDirection
std::string PortDirection
Definition:
TypeDefines.hh:44
std::vector
STL vector class.
Definition:
stl.hh:37
gem5::ruby::BaseRoutingUnit::BaseRoutingUnit
BaseRoutingUnit(const Params &p)
Definition:
BaseRoutingUnit.hh:64
gem5::ruby::Switch
Definition:
Switch.hh:78
gem5::SimObject::Params
SimObjectParams Params
Definition:
sim_object.hh:170
gem5::ruby::BaseRoutingUnit::RouteInfo::m_link_id
const LinkID m_link_id
Definition:
BaseRoutingUnit.hh:81
gem5::ruby::BaseRoutingUnit::RouteInfo
Definition:
BaseRoutingUnit.hh:75
gem5::ruby::BaseRoutingUnit::addOutPort
virtual void addOutPort(LinkID link_id, const std::vector< MessageBuffer * > &m_out_buffer, const NetDest &routing_table_entry, const PortDirection &direction, int link_weight)=0
gem5::VegaISA::p
Bitfield< 54 > p
Definition:
pagetable.hh:70
gem5::ruby::BaseRoutingUnit::init_parent
void init_parent(Switch *parent_switch)
Definition:
BaseRoutingUnit.hh:89
sim_object.hh
gem5::SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:146
gem5::ruby::BaseRoutingUnit::route
virtual void route(const Message &msg, int vnet, bool deterministic, std::vector< RouteInfo > &out_links)=0
gem5::ruby::BaseRoutingUnit::PARAMS
PARAMS(BaseRoutingUnit)
gem5::ruby::NetDest
Definition:
NetDest.hh:45
gem5::ruby::BaseRoutingUnit::RouteInfo::RouteInfo
RouteInfo(const NetDest &dests, const LinkID link_id)
Definition:
BaseRoutingUnit.hh:77
gem5::ruby::LinkID
unsigned int LinkID
Definition:
TypeDefines.hh:41
Network.hh
gem5::ruby::BaseRoutingUnit
Definition:
BaseRoutingUnit.hh:59
gem5::ruby::Message
Definition:
Message.hh:62
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
Message.hh
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